RU2368097C1 - Television system - Google Patents

Abstract

FIELD: physics, radio engineering.

SUBSTANCE: invention is related to radio communication engineering, may be used for digital broadcasting. Results are achieved by transfer of information along single radio channel and its reception by single track, and also by the fact that the following components are introduced in television system on transmitting side - photoelectric transducer, CID-matrix, three coders, and transmitter is arranged as single-channel, single track of video signal codes reception and processing is available on receiving side, and device of video information display is represented by flat-panel light diode screen.

EFFECT: reduced energy intensity of system (3 times) versus prototype and increased brightness of displayed image.

19 dwg, 2 tbl

Description

The invention relates to radio communications technology and can be used for digital broadcasting.

The prototype adopted "Digital television system" [1], containing on the transmitting side a photovoltaic converter / photoelectric converter /, generating three analog color signals R, G, B, three ADCs of a video signal, a master oscillator and a frequency synthesizer, two ADCs of a sound signal, three code shapers , two self-propelled pulse distributors / SRI / and a transmitter of radio signals from three channels, on the receiving side containing a control unit, three paths for receiving and processing codes of video signals, each of which includes a radio signal receiving unit, an amplifier diodes, a bipolar amplitude detector and a channel for processing signal codes / R, G, В /, including the first and second pulse generators, two registers, a code processing unit / doubling the number of samples in a line /, the first block of delays, the adder and the second block of delays, the receiving side has six blocks of pulse amplifiers, a radiation modulation block, horizontal and vertical blocks, two amplifiers and two piezoelectric deflectors, a matte screen, a channel for generating control signals and two sound channels. On the transmitting side, the signals R, G, B are separately encoded in 550 lines of a frame of 1000 samples per line. Frame rate 25 Hz, each of two fields. Information is transmitted by three channels, for each color signal its own channel, two carrier frequencies are used. The receiving side receives three radio signals in parallel in three paths, selects the horizontal and frame sync pulses of the SSI, CSI, doubles the number of samples in each row and doubles the number of lines in the frame. We withstand at the receiving side 2000 _count × 1100 _lines × 25 Hz. The image is reproduced by electron-optical scanning / lowercase and frame / and projecting the frame on a matte screen. The disadvantages of the prototype: high energy consumption of the system / information transfer through three channels and its reception in three paths /, the need for precise alignment of the photomultiplier, insufficient brightness of the reproduced image on the matte screen.

The purpose of the invention is to reduce the energy intensity of the system, increase the brightness of the reproduced image and the exclusion of horizontal and vertical scans on the receiving side. Technical results include a three-fold reduction in the energy intensity of the system, a change in the design of the photomultiplier, and an increase in the brightness of the reproduced image. Technical results are achieved by transmitting information over one radio channel and receiving it in one path, introducing into the photomultiplier a PZI matrix / charge injection device / made using the Foveon XZ technology [2, p. 522], and introducing a flat-panel LED screen / SD- on the receiving side screen.

The essence of the invention is that in the television system on the transmitting side, an FDI matrix is introduced into the photomultiplier, three encoders and the transmitter are single-channel, on the receiving side there is one channel for receiving the radio signal and two receiving registers are introduced, and in each channel of the color signal R, G, B a decoder, a frame code storage device and a control signal generator are introduced, and the video information display device is represented by a flat-panel LED screen. The transmitting side in FIG. 1, the structure of the digital rod in FIG. 2, the encoder in FIG. 3, the operation diagrams of the encoder in FIG. 4, the code generator in FIG. 5, the receiving side in FIG. 6, the spectrum of the amplitude-modulated signal in FIG. .7, bipolar amplitude detector in FIG. 8, decoder in FIG. 9, code processing unit in FIG. 10, frame code storage in FIG. 11, register block in FIG. 12, 13, (control signal generator in FIG. 14 , the block of allocation of codes SSI / CSI / in Fig. 15, the SD cell in Fig. 16, the matrix element in Fig. 17, the arrangement of the matrix elements in the LED screen in Fig. 18, belt diagrams of the system in Fig. 19. On the transmitting side, a video mode of 800 × 1000 × 25 Hz is used, where: 800 is the number of encoded samples in a line, 1000 is the number of encoded lines in a frame, 25 Hz is the frame rate. digital conversion of signals R, G, B is:

f _ADC = 25 Hz × 1000 _lines × 800 _count = 20 MHz,

После кодеров формируются два потока кодов: первый состоит из 13-разрядных суммарных кодов, который включает в себя один 9-разрядный код сигнала R и четыре разряда /с 1-го по 4-й/ сигнала G, второй поток состоит из 14-разрядных суммарных кодов, который включает в себя один 9-разрядный код сигнала В и пять разрядов /с 5-го по 9-й/ сигнала G.line frequency: 25 Hz × 1000 _pages = 25 kHz. When forming a digital image, there will always be consecutive codes of equal magnitude, and the higher the sampling frequency / 20 MHz /, the more equal codes there will be. When compressing the stream of each color signal, the encoder accepts a lower compression coefficient equal to 4. When compressing the code stream four times, the sampling frequency at the output of each encoder will be equal to

After the encoders, two code streams are formed: the first consists of 13-bit sum codes, which includes one 9-bit code of the R signal and four bits / from 1st to 4th / of the G signal, the second stream consists of 14-bit total codes, which includes one 9-bit code of signal B and five bits / from 5th to 9th / of signal G.

Following the encoders, the code generator from two streams generates one code stream at its output.

The clock frequency during the formation of a common single stream of codes is:

f _t = 5 MHz × 14 = 70 MHz,

where: 5 MHz - sampling rate of codes in encoders,

14 - the number of bits in the total stream code.

период следования разрядов в коде 14,28 нс

The period of the codes in the stream at the output of the encoder

discharge period in the code 14.28 ns

The carrier frequency of the transmitter is received:

f _n = 70 MHz × 15 = 1050 MHz.

The upper side frequency f _in = 1050 + 70 MHz = 1120 MHz.

The lower side frequency f _nn = 1050-70 MHz = 980 MHz.

On the receiving side, the number of samples in a row doubles, and the video mode is reproduced: 1600 × 1000 _pages × 25 Hz.

The resolution of the frame is 1600 × 1000 = 1.6 × 10 ⁶ pixels.

The transmitting side includes / Fig. 1 / photovoltaic converter 1 / FEP /, which is a sensor of the three primary colors R, G, B and contains a lens 2, in the focal plane of which is located the photosensitive side of the matrix PZI 3 - charge-injection device made according to the technology of the company Foveon ХЗ from a three-layer CMOS sensor [2, p.552, 3, p.832-835], with an optical resolution of 1600 × 1000 and providing 24-bit color depth, from the first to the third conclusions of the FDI matrix 3 are connected respectively to the inputs of the preliminary amplifiers 4 / R /, 5 / G /, 6 / V /, before The first side includes the first 7, second 8, third 9 ADCs of the video signals, the first 10 and second 11 ADCs of the sound signal, serially connected the master oscillator 12 of the sinusoidal oscillations and the synthesizer 13 frequencies, the first 14, the second 15, the third 16 encoders, the encoder 17 codes, the first 18 and second 19 keys, the first self-propelled distributor of 20 pulses / SRI /, which generates an SSI horizontal sync pulse code, the second SRI 21, which generates a CSI HR sync pulse code, and transmitter 22, which includes a carrier frequency amplifier 23 connected in series, amplitude m a modulator 24 and an output amplifier 25. The amplitude modulator 24 consists of a series-connected ring modulator and a bandpass filter [4, p.234], the carrier frequency is suppressed in the ring modulator, the bandpass filter filters the lower side frequency. The upper modulated lateral frequency of 1120 MHz with the information of codes K, G, B in block 24 is output to the output amplifier 25, with a stability of the carrier frequency of 10 ^-7 it takes up on the air the band ± 112 Hz or only 224 Hz. The ADCs 7, 8, 9 are identical and are accepted without changes from the prototype [1, p. 9, Fig. 3]. ADC 10, 11 of the sound signal are also received from the prototype without changes [1, p. 9, Fig. 4]. The ADCs 10, 11 convert audio signals into 14-bit codes, which are received with sampling of 75 kHz from the ADC 10 to the third information input of block 17, from the ADC 11 to the fourth information input of block 17.

The encoders 14, 15, 16 are identical, each includes / Fig. 3/ series-connected register 26, comparison circuit 27 / comparator /, pulse counter 28 and decoder 49, series-connected block of delay elements 30, block of 31 keys and buffer storage 32 of frame codes . Information inputs are bitwise integrated first-eighth inputs of the register 26, the first inputs 1-8 of the comparison circuit 27 and the inputs of the block 30 delay elements. The outputs are the first to ninth outputs of the buffer storage 32 frame codes, the volume of which is at least 200 × 10 ³ nine-bit frame codes. The control input is the control input / 5 MHz / block 32. The generator 17 codes includes / Fig.5/ four channels, the first and second channels are identical. The first channel includes a series-connected first block of 33 AND elements, the first 34 and second 35 OR elements, the first output key 36 and the first SRI 37, the second channel includes the second block 38 of AND elements, the third 39 and fourth 40 OR elements, the second output key 41 and second SRI 42. The third channel includes a third block of AND elements 43, a fifth 44 element OR, and a third SRI 45, the fourth channel includes a fourth block 46 of AND elements, a sixth element OR 47, and a fourth SRI 48. Code generator 17 includes a first 49, a second 50, third 53 keys and serially connected mid a pulse counter 51 and a decoder 52. The information inputs of block 17 are: the first are the first from the first to 14 inputs of a block 33 containing 14 AND elements, the second are the first from the first to 14th inputs of a block of 38 I elements containing 14 AND elements, the third - the first inputs of the 14 elements AND block 43, the fourth - the first inputs of the 14 elements AND block 46, the fifth - the third input of the second element OR 35 connected to the output of the SRI 20 through key 53, the sixth - the third input of the fourth element OR 40, connected to the output of the SRI 21. The first output of block 17 are the combined outputs of the output lyuchey 36, 41, the second - a third output of the decoder 52 is connected to the input of the HRE 20, giving at its input a signal U _n starts. The control inputs of block 17 are: the first is the combined inputs of the keys 49, 50 and the counting input of the counter 51 pulses / 5 MHz /, the second is the combined signal inputs / 70 MHz / output keys 36, 41, the third is the control input / 25 kHz / counter 51 pulses, fourth - the control input of the third key 53 / U _p 25 Hz /. The first output of the decoder 52 is connected to the first control input of the key 49, the second output is connected to the second control input of the key 49 and to the first input of the key 50, the third output of the decoder 52 is connected to the second control input of the key 50 and is the second output of the block 17. The second inputs of the blocks 33, 38, 43 and 46 are connected respectively to the outputs of PRI 37, 42, 45, 48.

The output of the first key 49 is connected to the inputs of the SRI 37 and 42, the output of the second key 50 is connected to the inputs / U _p / SRI 45 and 48. The input of the third key 53 is the fifth information input of block 17, the output of the key is connected to the third input of the first OR 35 element.

The receiving side includes / FIG. 6 / antenna, control unit 54 / channel selection / and a path for receiving and processing video signal codes, a video information display device, a channel for generating control signals and two identical sound channels. The path for the reception and processing of codes of video signals receives and processes the codes for video signals R, G, B and includes serially connected radio signal receiving unit 55, radio frequency amplifier 56 and bipolar amplitude detector 57, signal channel R, signal channel G and signal channel B. Signal channel R includes serially connected first pulse shaper 58, first receiving register 59 containing 14 bits, R signal register 60, decoder 61, processing / doubling / code unit 62, frame code storage 63 and control signal generator 64 als. The channel of the signal G includes serially connected register 65 of the signal G, decoder 66, block 67 processing / doubling / codes, the drive 68 code codes frame and the generator 69 of the control signals. The signal channel B includes serially connected a second pulse shaper 70, a second receiving register 71 containing 14 bits, a signal B register 72, a decoder 73, a processing / doubling / code unit 74, a frame code storage 75 and a control signal shaper 76. The outputs of the drivers 64, 69, 76 of the control signals are connected to the corresponding inputs of the flat-panel LED screen 77 / LED screen /. The order of operation of the receiving side is determined by the channel for generating control signals, which includes a serially connected block 78 for selecting horizontal sync pulses / CCI /, a frequency synthesizer 79, a key 80, a counter 81 pulses, a decoder 82 and a block 83 for selecting frame sync pulses / CSI /. Sound channels 84, 85 are identical, they are used without changes, as in the prototype, each of them contains a converter of sound codes to analog signals / DAC /, a power amplifier and a loudspeaker. The decoders are identical, and each decoder 31, 66, 73 includes / Fig. 9/ connected in series the first nine-bit register 86, the drive 87 code frame with a capacity of 200,000 9-bit codes / 200 _count × 1000 _lines /, the second nine-bit register 88, the first block 89 keys of eight keys and a third eight-bit register 90, connected in series to the second block of keys 91 / of eight keys /, eight-bit subtracting counter 92 and decoder 93, the first 94, second 95, third 96 and fourth 97 keys. The decoder information input is the first to ninth inputs of the first register 86, the output is the first to eighth outputs of the third register 90. The control inputs are: the first is the combined control input of the register 86 and the signal input / 5 MHz / of the third key 96, the second is the combined signal inputs / 20 MHz / keys 94, 95, 97. The output of the ninth category of the second register 88 is connected in parallel to the first control input of the second key 95, to the second control inputs of the third 96 and fourth 97 keys and the first key 93, to the second control input of the first block of keys and to the first control input of the second block of keys. The output of the first key 94 is connected to the first control input of the third register 90, the second control input of which is connected to the output of the second key 95, to which the counting input of the subtracting pulse counter 92 is connected, the output of the decoder 93 is connected in parallel to the first control input of the first key block 89, to the second control input of the second key block 91, to the first control inputs of the keys 94, 96, 97 and to the second control input of the second key 95. The output of the third key 96 is connected to the control input of the drive 87 frame codes, output the fourth key 97 is connected to the control input of the second register 88. The code processing units 62, 37, 74 are identical, each includes / trigger 10 / trigger 98, the input of which is the control input of the block, the first 99 and second 100 key blocks / each of 8 keys /, first 101, second 102, third 103, fourth 104 registers, adder 105, fifth 106 and sixth 107 registers that store codes 50 ns, and 16 diodes. The information input of the code processing unit is bitwise integrated 1-8 inputs of blocks 99, 100 keys. The outputs are the bitwise combined outputs 0-7 of the adder 105 and the outputs / 1-8 / of the registers 106, 107. The inputs of the registers 101 and 102 are bitwise combined and connected to the 1-8 outputs of the first block of 99 keys, the outputs of these registers 102 and 101 through the diodes are bitwise combined and connected to the first group of inputs of the adder 105. The inputs of the registers 103 and 104 are bitwise combined and connected to 1-8 outputs of the second block of keys 100, the outputs of the keys 104 and 103 through the diodes are bitwise combined and connected to the second group of inputs of the adder 105. Output 1 of the trigger connected to control in parallel the input inputs of the second 102, third 103 and fifth 106 registers and to the control input of the key block 99. The second output of trigger 98 is connected in parallel to the control inputs of the first 101, fourth 104 and sixth 107 registers and to the control input of the second block of keys 100. Drives 63, 68, 75 frame codes are identical, each includes / 11 / blocks 108 registers by the number of lines in the frame 108 _1-1000 .

The information input of the frame code storage device is the bitwise integrated 1-8 inputs of all blocks of 108 registers. Output is the output of register blocks 108, only outputs 12.8 × 10 ^6/1600 × 8 × 1000 /. The control inputs are: the first is the first control input U _to / 25 Hz / of the first block 108 ₁ registers, the second is the combined second control inputs of blocks of 108 registers / 25 kHz /, the third is the combined third control inputs of U _d / 40 MHz / blocks of 108 registers . The control output of each previous block of registers is the first control input for each subsequent block of 108 registers. The control output of the last / 1000th / block 108 registers is connected in parallel to the fourth control inputs of all blocks 108 registers. The blocks 108 of the registers are identical, each includes / Fig. 12, 13 / first 109 and second 110 keys, a distributor 111 pulses and eight registers 112 _1-8 , each of which includes 1600 bits / according to the number of samples in the line /. The information inputs of the register block are bitwise combined from the first to the eighth third inputs of the bits of eight registers 112. The outputs are the parallel outputs of all bits / 1600 / eight registers, the total outputs from the block 108 12800/1600 × 8 /. The outputs of 1000 blocks of registers are the outputs of each block of the drive codes 63, 68, 75 - 12.8 × 10 ⁶ . The control inputs of the block 108 of the registers are: the first is the first control input / 25 Hz / first key 109, the second is the signal input U _vy / 25 kHz / second key 110, the third is the signal input U _d / 40 MHz / first key 109, the fourth is the first control input of the second key 110. The last output / 1600 / of block 111 is the control output of each block 108, connected to the first control input of the first key 109 in the next block 108 of the registers. The output of the first key 109 is connected to the input of the pulse distributor 111, the outputs of which are sequentially, starting from the first, connected to the first / clock / inputs of the bits in parallel to eight registers 112. The output of the second key is connected in parallel to the second inputs of the bits of eight registers 112 and to the second control input of its 110 of the key, one pulse passed, _Uout, closes the key 110. The outputs of the drives 63, 66, 75 of the frame codes are connected / Fig. 6/ to the information inputs of their drivers 64, 69, 76 of the control signals, the purpose of which is to perform the formation of a “code - the number of radiation pulses” for each incoming code, forming the duty cycle of the LED emissions for the frame period. Each of the blocks 64, 68, 76 includes “code - number of radiation pulses” converters according to the number of samples in the line / 1600 / and the number of units / 1000 / in the frame, i.e. 1.6 × 10 ⁶ . Blocks 64, 69, 76 are identical, each includes / FIG. 14/ pulse shaper block 113 containing identical pulse shaping circuits by the number of converters 1.6 × 10 ⁶ , the input of block 113 is the control input / 25 Hz / block 64/69, 76 / and includes converters "code - the number of pulses of radiation", which in the number of frame resolutions is 1.6 × 10 ⁶ . Each converter includes a sequentially connected decoder 114, the information inputs of which 1-8 are information inputs of the converter, the key block 115 of 255 keys and the output key 116, includes a self-propelled pulse distributor 117 / SRI /, the input / U _p / of which is connected to the corresponding output in block 113, and 255 outputs of 255 bits of which are connected to the signal inputs of the corresponding keys in block 115, and includes a power source 118, 255 outputs of the decoder 114 are connected to the first control inputs / U _from / 255 keys of block 115, the outputs of which are combined, the combined output is connected to the control input / U _from / the output key 116, the signal input of which is connected to the output of the power supply 118. Information inputs of block 64 are information inputs of all decoders 114, outputs are outputs of output keys 116. The initial state of output keys 116 and keys in blocks 115 is closed.

, 40 мс длительность кадра, 255 - разрешение 8-разрядного кода, т.е. число выходов с блока 117. Светодиод за период кадра через равные интервалы времени выдает число импульсных излучений пропорционально величине кода цветового сигнала. Чем больше код, тем больше импульсных излучений за период кадра. Пример распределения импульсов излучений за кадр соответственно величинам кодов в таблице I.The control input / 25 Hz / block 113 receives the signal U _к / 25 Hz /, which is simultaneously fed to the inputs of the pulse shaper circuits forming pulses U _{p of the} corresponding amplitude and duration for the SRI 117. With the arrival of the code at the inputs of the decoder 114, the signals from its corresponding the outputs open the corresponding keys in block 115, through which the signals from the outputs of the corresponding bits SRI 117 pass and arrive at the control input U _{from the} output key 116, which in the open state energizes its LED in the LED screen. Light pulses of LEDs of the same duration. The output key 116 opens each time for a duration of 156 μs

, 40 ms frame duration, 255 - resolution of an 8-bit code, i.e. the number of outputs from block 117. The LED for the period of the frame at equal time intervals gives the number of pulsed emissions in proportion to the value of the color signal code. The larger the code, the more pulsed emissions per frame period. An example of the distribution of radiation pulses per frame according to the code values in table I.

Table 1 Block 114 input code The distribution of radiation pulses in the frame period The number of emissions 00000000 00 ... 000 0 00000001 00 ... 128 00 one 00000010 00 ... 88 176 00 2 00000011 00 ... 64 128 192 00 3 . . . . . . . . . 11111110 1,2,3,4 ... 254 00 254 11111111 1,2,3,4 ... 254 255 255 0 - no radiation, 1,2,3 - 255 - sequence numbers of radiation pulses in the frame period.

Following radiation pulses in the frame period at equal time intervals contributes to the natural perception of the image by human vision in terms of color accuracy and brightness. The inertia of the LEDs should be up to 1 μs. With the end of the frame period in blocks 63, 68, 75, all frame codes of the signals R, G, B are concentrated, which, with the arrival of the signal from the last block of 108 ₁₀₀₀ registers (Fig. 11/), are output to the shapers 64, 69, 76 of the control signals, in which The new codes are simultaneously converted to the number of radiation pulses by the LEDs of the LED screen. Modern technologies in electronics allow each of the blocks 63, 68, 75 and 64, 69, 76 to be executed with a single chip. The flat-panel LED screen 77 represents a set of radiating elements in the matrix according to the number of frame resolutions 1.6 × 10 ⁶ , which are performed in glass / or other appropriate material / LED screen 77, the LED screen includes a glass screen and a matrix of radiating elements in number frame resolution. Each emitting element includes three LED cells / LED cells /, each of which emits one of the primary colors R, G, B. The LED cell contains / Fig. 16/ a white LED 122 and a corresponding color filter 123. Three LED cells make up the radiating element of the matrix / Fig.17/, the arrangement of the elements of the matrix and LED cells in the screen of Fig. 18. The level of brightness of the radiation of an SD cell is perceived by vision in proportion to the number of pulses of the LED radiation per frame period, which can be from one / 156 μs / to 255/40 ms /. The total radiation of the three primary colors by three LED cells forms both the brightness and the color tone of one pixel on the screen. As light-emitting diodes (as soon as the technology for their manufacture is ready), LEDs with polymer organic molecules can be used — LEDs of the SDT / or LED technology [5, p. 43], or super-bright LEDs of the Nichia and Ledtronics firms [6, p. 47]. LEDs of both CDT and super-bright technologies are executed in the screen material by the microelectronic technology. The dimensions of the super-bright LEDs are taken with a diameter of 0.5 mm / 16 /, the size of one emitting element in this case will be 1 × 1 mm / 17 /, and the size of the LED screen 77 will be:

horizontally 1600 × 1 mm = 1600 mm,

vertical 1000 × 1 mm = 1000 mm,

188 cm or 74 ".

Block 78 allocation of horizontal sync pulses SSI and block 83 allocation of frame sync pulses / CSI / are identical, each includes / Fig.15 / counter 119 pulses, decoder 120, element HE 121 and two diodes. Counter 119 4-bit. The information input of the block 78/83 / is its counting input 1 of the counter 119 pulses, the control input is the control input 2 of the counter 119, which is connected via the diode to the output of the second pulse shaper 70/6 /. In block 83 of the selection of the CSI, the information input of the block is connected to the output of the pulse shaper 70, and the control input is also connected through the diode to the output of the pulse shaper 58. The output of block 78, 83 is the output of the decoder 120, which is connected through the diode to the output of the element HE 121, and together they are connected to the control input of the counter 119 pulses after the diode. The SSI code is represented by a 14-bit code from one unit. The CSI code is also a 14-bit code of 14 units. The SSI code enters the counting input of block 78, the CSI code enters the counting input of block 83 from the pulse shaper 70, and the control input of block 83 is connected to the output of block 58.

The operation of the blocks 78/83 /, Fig. 15.

With the receipt of the SSI code at the counting input of the counter 119, he counts 14 pulses in a row / code 1110 /. As a result, signals appear at the outputs of the first or third bits of counter 119, which are decoded by decoder 120, and a horizontal sync pulse SSI appears at the output of block 78. When the SSI code arrives at the counting input of the counter 119 from the output of the block 70 / Fig.6/, there are no code pulses / Fig.2/. Starting from the second line code, from block 70, codes will go to the control input 2 of counter 119, and with the arrival of each code unit, counter 119 will be reset to zero and will not be able to reach account 14/1110 /. In parallel to the counting input of counter 119, codes also go from block 58, in which there are always ones and zeros, and for each zero, element NOT 121 gives a signal that also resets counter 119 pulses. In addition, when the SSI is output from the output of the decoder 120, it goes through the diode to the control input of the counter 119 and resets it. Thus, the circuit block 78/83 / eliminates the appearance of a false signal SSI / CSI /. In block 83, when the CSI code is transmitted from the pulse generator 70 to the counting input of the counter 119, signals that are decoded by the block 120 appear at the outputs of the 1-3 bits of the counter 119, and a frame sync pulse of the CSI appears at the output of the block 83. When the CSI code arrives at the counting input of block 83, pulses do not go from the output of block 58 to its control input. Further, the operation of block 83 is similar to the operation of block 78. Photoelectric converter 1 by a matrix of PZI 3 generates three analog video signals of primary colors. Lens 2 creates an image in the focal plane in which the photosensitive side of the FDI array 3 is located. The optical resolution of the array is at least 800 × 1000 _lines . The FDI matrix is made three-layer according to the HZ technology [3, p. 832]. Ha each of the three layers of the FDI matrix from key 18 receives pulses of 25 kHz line frequency for reading the vertical signals of pixels, the second input of the matrix of FDI from key 19 receives 20 MHz pulses for reading the R, G, V pixels horizontally [3, p .832]. Analog signals from the matrix of the FDI 3 are fed to the inputs of the preamplifiers 4, 5, 6, the outputs of which are fed to the inputs of the ADCs, respectively 7, 8, 9, the outputs of which are 8-bit codes of color signals with sampling rate of 20 MHz received at the inputs of their encoders 14 , 15, 16. Synchronization of reading signals from the FDI matrix is performed by a signal of a frame frequency of 25 Hz by opening the keys 18, 19 for a frame duration of 40 ms. The synthesizer 13 outputs a frequency from the first output pulses of 20 MHz sampling codes ADC 7-9 and the signal input of the key 19 from the second output pulses of 5 MHz signals U _vyd with encoders 14-15, with the third output pulses 75 kHz sampling audio codes with the fourth — 70 MHz clock pulses for the 17 code generator, from the fifth — 25 kHz line frequency pulses to the signal input of the key 18, to the third input of the block 17 and to the third inputs of the ADC 10, 11, from the sixth output pulses of 25 Hz frame frequency to the control inputs keys 18, 19, from the seventh output of the sine wave carrier pilots at 1050 MHz transmitter 22 ^-7 10 with stability. The ADCs 7, 8, 9 convert the analog signals into 8-bit codes, coming in parallel form to the encoders 14, 15, 16.

The work of the encoders, Fig.3.

. При коэффициенте сжатия выше 4 эта частота 5 МГц выдачи будет тем более удовлетворять. Схема 27 сравнения выполняет сравнение кодов по величине и представляется двумя микросхемами 530CП1 с временем срабатывания 18 нс [9, c.279]. При неравенстве А>В появляется сигнал на выходе 2 блока 27 /в микросхеме выход 5 [9 c.272 рис.2.190]/, при равенстве кодов А=В сигнал с выхода 1 /в микросхеме выход 7/. При равенстве кодов сигнал с выхода 1 блока 27, закрывает ключи в блоке 31, поступает счетным импульсом в счетчик 28 импульсов и как сигнал U_выд на первый управляющий вход регистра 26. Счетчик 28 производит счет импульсов с выхода 1 блока 27, пока идут коды, равные по величине. Счетчик 28 восьмиразрядный, максимальный код в нем 11111111 /255/, отсюда и максимальный коэффициент сжатия 255. Счетчик из микросхем К531ИЕ160 с временем срабатывания 8 нс [9, c.428]. При появлении неравных кодов со схемы 27 следует сигнал с выхода 2 или 3 /А<В/, которые объединены, сигнал с них используется для выдачи кода числа равных кодов из счетчика 28 через диоды в 1-8 входы блока 32 и для заполнения в блоке 32 девятого разряда, с которого сигнал используется для опознания по нему кода числа равных кодов при декодировании. Этот же сигнал открывает ключи в блоке 31 /вход 1/ и обнуляет регистр 26 вход 2. Выданный перед этим с блока 32 код является первым кодом последовательности, по диаграмме I фиг.4 они помечены крестиками. Коды, равные по величине и подсчитанные счетчиком 28, исключаются из потока, диаграмма III фиг.4, за счет их и идет сжатие. Емкость буферного накопителя 32 кодов соответствует числу 9-разрядных кодов в кадре /200×10³/ для обеспечения темпа следования с частотой 5 МГц. При следовании подряд кодов, равных по величине, более 255 в работу вступает дешифратор 29. При коде 11111111 дешифратор 29 выдает сигнал, который одновременно открывает ключи в блоке 31 /вход 1/, обнуляет регистр 26, сигналом U_выд выдает код из счетчика 28 /вход 1/ и обнуляет счетчик /вход 2/, а в девятый разряд блока 32 поступает сигнал опознания кода числа равных кодов. Пропускная способность кодера определяется временем срабатывания схемы сравнения 27, которая обеспечивает до 40 Мбайт/с, и удовлетворяет требуемой 20 Мбайт/с. С выходов кодеров 14, 15, 16 коды в параллельном виде поступают на первый и второй информационные входы формирователя 17 кодов, который /фиг.5/ первым кодом в строке выдает код ССИ, из сжатого потока кодов формирует и выдает со второго по 197-й коды сигналов R, G, В и затем три кода сигнала звука /198, 199, 200-й отсчеты строки/, фиг.2. Код КСИ является первым кодом строки только в первой строке каждого кадра, при этом коде сигнала ССИ нет. Код ССИ является в каждой строке первым, начиная со второй строки, при этом нет кода КСИ /фиг.2/. Единицы кода R и 1-4 разряды кода G представляются на выходке блока 17 положительными полусинусоидами моночастоты 70 МГц, единицы в кодах В и 5-9 разрядах кода G единицы представляются отрицательными полусинусоидами той же частоты 70 МГц.8-bit codes in parallel form are received at 1-8 inputs of register 26, at the first inputs of the comparison circuit 27, and at the inputs of the block 30 of delay elements. The initial state of the keys in block 31 is open. The code in block 30 is delayed by the response time of the comparison circuit / 18 ns / and enters through the public keys of block 31 to 1-8 inputs of the buffer storage 32 frame codes with a capacity of 200 × 10 ³ 9-bit codes. Comparison scheme 27 compares the magnitude of each previous and subsequent codes in order to identify their equality or inequality. When unequal codes are followed, they pass through block 30, the public keys of block 31 and go to the first and eighth inputs of the buffer storage 32 codes. The issuance of codes from block 32 is performed by a signal _Uout 5 MHz from the output 2 of block 13. The receipt of codes in block 32 when following unequal codes occurs with a frequency of 20 MHz. In the general stream of codes there are a large number of codes of equal size. The encoder compresses the stream of codes with a floating coefficient from 1 to 255. The smallest total compression coefficient is taken to be 4, so the frequency of issuing codes from block 32 is taken at 5 MHz

. With a compression ratio above 4, this frequency of 5 MHz output will be all the more satisfying. The comparison circuit 27 compares the codes in magnitude and is represented by two 530CP1 microcircuits with a response time of 18 ns [9, p.279]. With the inequality A> B, a signal appears at the output of block 2 27 / in the output 5 circuit [9 c.272 fig. 2.190] /, with the equality of the codes A = B, the signal from output 1 / in the output circuit 7 /. If the codes are equal, the signal from the output 1 of block 27 closes the keys in block 31, arrives as a counting pulse in the counter 28 pulses and as a signal U _comes to the first control input of the register 26. The counter 28 counts the pulses from the output 1 of block 27, while the codes go, equal in magnitude. The counter 28 is eight-bit, the maximum code in it is 11111111/255 /, hence the maximum compression ratio is 255. The counter is made of K531IE160 microcircuits with a response time of 8 ns [9, p. 428]. When uneven codes appear from circuit 27, a signal is output from output 2 or 3 / A <B /, which are combined, the signal from them is used to output a code for the number of equal codes from counter 28 through diodes to 1-8 inputs of block 32 and for filling in the block 32 of the ninth digit, from which the signal is used to identify by it the code of the number of equal codes during decoding. The same signal opens the keys in block 31 / input 1 / and resets register 26 to input 2. The code previously issued from block 32 is the first code in the sequence; they are marked with crosses in diagram I of figure 4. Codes of equal magnitude and counted by the counter 28 are excluded from the flow, diagram III of figure 4, due to them and there is compression. The capacity of the buffer storage 32 codes corresponds to the number of 9-bit codes in the frame / 200 × 10 ³ / to ensure the repetition rate with a frequency of 5 MHz. When following consecutive codes, equal in magnitude to the work of more than 255 enters the decoder 29. When the code 11111111 decoder 29 outputs a signal which simultaneously opens in block 31 the keys / Input 1 / resets the register 26, U _vyd outputs a code signal from the counter 28 / input 1 / and resets the counter / input 2 /, and the ninth digit of block 32 receives a signal to identify the code for the number of equal codes. The bandwidth of the encoder is determined by the response time of the comparison circuit 27, which provides up to 40 MB / s and satisfies the required 20 MB / s. From the outputs of the encoders 14, 15, 16, the codes are sent in parallel to the first and second information inputs of the code generator 17, which / Fig. 5/ gives the SSI code as the first code in the line, generates and issues the second and 197th codes from the compressed code stream signal codes R, G, B and then three audio signal codes / 198, 199, 200th samples of the line /, Fig.2. The CSI code is the first code of the line only in the first line of each frame, while there is no signal of the CSI. The CSI code is the first in each line, starting from the second line, while there is no CSI code / 2 /. Units of the R code and 1–4 bits of the G code are represented at the output of block 17 by positive half-sine waves of the monofrequency of 70 MHz; units in codes B and 5–9 bits of the code G units are represented by negative half-sines of the same frequency of 70 MHz.

The operation of the shaper 17 codes, Fig.5.

. Выходной ключ 36 в открытом состоянии пропускает одну положительную полусинусоиду на выход, выходной ключ 41 в открытом состоянии пропускает на выход одну отрицательную полусинусоиду. Выходы ключей объединены и являются первым выходом блока 17, выходной сигнал с которого представляется полными или неполными синусоидами моночастоты 70 МГц со стабильностью 10^-7. Очередность следования кодов в строке определяется счетчиком 51 импульсов и дешифратором 52. Счетчик 51 8-разрядный, ведет счет импульсов строки 5 МГц с 1-го по 200-й. При коде 00000001 импульс с первого выхода дешифратора 52 открывает ключ 49. При этом открытый ключ 49 пропускает импульсы 5 МГц, идет формирование кодов строки со второго отсчета по 197-й. С приходом на вход счетчика 51 197-го импульса сигнал со второго выхода дешифратора 52 закроет ключ 49 и открывает ключ 50, при этом формируются три кода 3в1 и три кода 3в2. Импульсы кода 3в1 с элемента ИЛИ 44 поступают на второй вход элемента ИЛИ 35 и открывают на время своей длительности ключ 36, импульсы кода 3в2 с элемента ИЛИ 47 поступают на второй вход элемента ИЛИ 40 и открывают на время своей длительности /14 нс/ выходной ключ 41. С приходом в счетчик 51 200-го импульса строки с третьего выхода дешифратора 52 импульс закрывает ключ 50 и как сигнал пуска U_п запускает СРИ 20, выдающий последовательный код из 14 единиц код ССИ на третий вход элемента ИЛИ 35, код ССИ проходит через открытый ключ 53, который закрывается импульсом 25 Гц кадра только на время 200 нс, когда идет код КСИ с СРИ 21 на третий вход элемента ИЛИ 40. По окончании периода кадра очередной кадровый импульс КСИ закрывает ключ 53 на длительность 200 нс /14,28 нс×14 разр/ и передним фронтом запускает СРИ 21, который выдает 14-и разрядный код КСИ. Сигналы КСИ представляются на выходе блока 17 14-ю отрицательными полусинусоидами, сигналы ССИ представляются 14-ю положительными полусинусоидами. Когда идет код ССИ, нет кода КСИ, и наоборот, при коде КСИ нет кода ССИ. Радиосигналы на приемной стороне принимаются блоком 55 /фиг.6/, являющимся селектором каналов с электронной настройкой. Блок 55 включает входную цепь, усилитель радиочастоты и смеситель. Радиочастотный сигнал через петлю связи поступает на смеситель, на второй вход которого с синтезатора 79 частот /вход 3/ подается частота, равная несущей частоте передатчика 22, необходимая для детектирования однополосного сигнала [7, с.146]. Сигнал со смесителя, являющийся выходным сигналом блока 55, поступает на вход усилителя 56 радиочастоты, где усиливается до необходимой величины и поступает на вход двухполярного амплитудного детектора 57, выполненного по схеме на фиг.8. Диод Д1 выделяет положительную огибающую модулирующего сигнала /фиг.19, диагр.9/. Диод Д2 из модулирующей выделяет огибающие положительных полусинусоид - символы единиц сигнала R и 1-4 разряды сигнала G. Диод Д3 из модулирующей выделяет огибающие отрицательных полусинусоид - символы единиц сигнала В и 5-9 разрядов сигнала G. С первого выхода блока 57 продетектированные положительные полусинусоиды частоты 70 МГц поступают на вход первого формирователя 58 импульсов, со второго выхода блока 57 продетектированные отрицательные полусинусоиды 70 МГц поступают на вход второго формирователя 70 импульсов. Формирователи 58, 70 импульсов выполнены по схеме несимметричного триггера с эмиттерной связью [8, с.209], формирующей прямоугольные импульсы из гармонически изменяющихся сигналов. Импульсы имеют одну полярность и длительность, равную длительности импульсов на передающей стороне. Единицы в кодах представляются импульсом, нули - их отсутствием. При включении питания ключ 80 в закрытом состоянии. Порядок работы приемной стороны определяется сигналами с канала формирования управляющих сигналов, задающая роль принадлежит блоку 78 выделения ССИ. При каждом приходе на вход блока 78 кода из 14 единиц /при отсутствии импульсов с блока 70/ на выходе блока 78 появляется строчный синхроимпульс ССИ, поступающий на первые вход синтезатора 79 частот и открывающий ключ 80. По ССИ выполняется точная подстрока /синхронизация/ частоты в блоке 79, собственная частота которого имеет стабильность 10^-6. Вторые входы блока 79 подключены к второй группе выходов блока 54 /выбора каналов/, сигнал с которого определяет частоту, выдаваемую с блока 79 на третий вход блока 65. Синтезатор 79 частот выдает: с первого выхода импульсы 5 МГц, со второго выхода импульсы 75 кГц дискретизации сигналов звука, с третьего - колебания несущей частоты, с четвертого - импульсы двойной частоты дискретизации кодов 40 МГц, с пятого - импульсы дискретизации кодов 20 МГц, с шестого - импульсы тактовой частоты 70 МГц на первые управляющие входы приемных регистров 59 и 71. С формирователя 58 импульсов коды поступают на информационный вход первого приемного регистра 59, с второго формирователя 70 импульсов импульсы кодов поступают на информационный вход второго приемного регистра 71. Приемный регистр 59 14-разрядный и принимает в 1-9 разряды 9-разрядный код сигнала R, в 10-13 разряды принимает с первого по четвертый разряды сигнала G. Приемный регистр 71 тоже 14-разрядный и принимает в 1-9 разряды 9-и разрядные коды сигнала В, в 10-14 разряды принимает с пятого по девятый разряды сигнала G. С приемных регистров 59, 71 сигналы U_выд 5 МГц выдают коды сигналов R, G, В в регистры соответственно 60 сигнала R, 65 сигнала G и 72 сигнала В. С выходов этих регистров сигналы кодов R, G, В выдаются c частотой 5 МГц в cвои декодеры соответственно 61, 66, 73.Timing diagrams of the operation of block 17 in Fig. 19. Block 17 converts parallel codes into sequential ones and replaces the representation of units from pulses with positive and negative half-sine waves in them. At the first information input in block 33, 1–9 bits of code R and 1–4 bits of code G are received, at the second information input in block 38, 5–9 bits of code G and 1–9 bits of code B are received, at the third information input in block 43, 1-14 bits of the sound signal from the ADC 10 3v1 are received, in the fourth, 1-14 bits of the second sound signal from the ADC 11 3v2 enter the block 46. The second inputs of the AND elements of the blocks 33, 38 receive sequentially 14 pulses from the outputs of the SRI 37, 42, the start signal U _p which comes from the first key 49. From the outputs of the blocks 33 and 38, the pulses of the codes are sequentially through the OR 34, 35 and 39, 40 arrive at the control inputs of the output keys 36, 41 and open them for a duration of 14.3 ns

. The output key 36 in the open state passes one positive sine wave to the output, the output key 41 in the open state passes one negative sine wave to the output. The key outputs are combined and are the first output of block 17, the output signal from which is represented by full or incomplete sinusoids of the 70 MHz monofrequency with a stability of 10 ^-7 . The sequence of codes in the line is determined by the counter 51 pulses and the decoder 52. The counter 51 is 8-bit, counts the pulses of the line 5 MHz from the 1st to the 200th. With the code 00000001, the pulse from the first output of the decoder 52 opens the key 49. In this case, the public key 49 transmits 5 MHz pulses, and line codes are being generated from the second sample to the 197th. With the arrival at the input of the counter 51 of the 197th pulse, the signal from the second output of the decoder 52 will close the key 49 and open the key 50, and three codes 3v1 and three codes 3v2 are generated. Pulses of the 3v1 code from the OR element 44 are fed to the second input of the OR element 35 and open the key 36 for the duration of their duration, the pulses of the 3v1 code from the OR element 44 are fed to the second input of the OR element 40 and open for the duration of their duration / 14 ns / output key 41 With the arrival in the counter 51 of the 200th pulse of the line from the third output of the decoder 52, the pulse closes the key 50 and as a start signal U _p starts the SRI 20, issuing a sequential code of 14 units, the SSI code to the third input of the OR element 35, the SSI code passes through the open key 53, which is closed by pulse 2 5 Hz of the frame only for a time of 200 ns, when the CSI code from the SRI 21 goes to the third input of the OR element 40. At the end of the frame period, the next frame pulse of the CSI closes the key 53 for a duration of 200 ns / 14.28 ns × 14 bits / and a leading edge launches SRI 21, which issues a 14-bit CSI code. CSI signals are represented at the output of block 17 by 14th negative half-sine waves, SSI signals are represented by 14th positive half-sine waves. When the ID code is on, there is no ID code, and vice versa, with the ID code there is no ID code. The radio signals at the receiving side are received by the block 55/6 /, which is a channel selector with electronic tuning. Block 55 includes an input circuit, a radio frequency amplifier, and a mixer. The radio frequency signal through the communication loop is fed to the mixer, the second input of which from the frequency synthesizer 79 / input 3 / is supplied with a frequency equal to the carrier frequency of the transmitter 22, necessary for detecting a single-band signal [7, p.146]. The signal from the mixer, which is the output signal of block 55, is fed to the input of the radio frequency amplifier 56, where it is amplified to the required value and fed to the input of the bipolar amplitude detector 57, made according to the scheme in Fig. 8. Diode D1 selects the positive envelope of the modulating signal / Fig. 19, Fig. 9 /. The diode D2 from the modulating one selects the envelopes of the positive half-sinusoids - symbols of signal units R and 1-4 bits of the signal G. The diode D3 from the modulating one selects the envelopes of the negative half-sinusoids - symbols of the units of signal B and 5-9 bits of the signal G. From the first output of block 57, the detected positive half-sine waves frequencies of 70 MHz are fed to the input of the first pulse shaper 58, from the second output of block 57 the detected negative half-sine waves of 70 MHz are fed to the input of the second pulse shaper 70. Shapers 58, 70 pulses are made according to the scheme of an asymmetric trigger with emitter coupling [8, p.209], forming rectangular pulses from harmonically changing signals. The pulses have one polarity and a duration equal to the duration of the pulses on the transmitting side. Units in codes are represented by momentum, zeros are represented by their absence. When you turn on the power, the key 80 is in the closed state. The order of operation of the receiving side is determined by the signals from the channel for generating control signals, the decisive role belongs to block 78 allocation SSI. Each time a code of 14 units arrives at the input of block 78 / in the absence of pulses from block 70 / at the output of block 78, an SSI horizontal sync pulse arrives at the first input of the frequency synthesizer 79 and opens the key 80. The SSI performs exact substring / synchronization / frequencies in block 79, whose natural frequency has a stability of 10 ^-6 . The second inputs of block 79 are connected to the second group of outputs of block 54 / channel selection /, the signal from which determines the frequency output from block 79 to the third input of block 65. Frequency synthesizer 79 produces: 5 MHz pulses from the first output, 75 kHz pulses from the second output sampling of sound signals, from the third - carrier frequency fluctuations, from the fourth - pulses of double sampling frequency codes 40 MHz, from the fifth - pulses of sampling codes 20 MHz, from the sixth - pulses of a clock frequency of 70 MHz to the first control inputs of receiving registers 59 and 71. С formirova Firing 58 pulses, the codes go to the information input of the first receive register 59, from the second pulse generator 70, the pulses of codes go to the information input of the second receive register 71. The receive register 59 is 14-bit and receives a 9-bit code of the R signal in 1–9 bits 10-13 digits receive the first to fourth digits of the signal G. The receiving register 71 is also 14-bit and receives 9-digit digits of the signal B in 1-9 digits, and receives the fifth to ninth digits of the G signal in 10-14 digits receiving registers 59, 71 signals U _vyd 5MHz give ode signals R, G, B, respectively in the registers 60 of the signal R, signals G 65 and 72 outputs the signal V. With these registers the signals R, G codes c are issued in the frequency of 5 MHz in cvoi decoders respectively 61, 66, 73.

The operation of the decoders, Fig.9.

The codes are sent in parallel to the first register 86, from which they are issued with a frequency of 5 MHz to the drive 87 frame codes, which have a capacity of 200 × 10 ³ 9-bit codes. From the drive 87, the codes are issued by signals _Uout 5 MHz from the key 96. When the key 96 is closed, the drive 87 accumulates codes. The initial state of the keys in block 91 is closed, in block 89 is open, keys 94, 96, 97 are open, key 95 is closed. In 1–6 bits of the second register 88, 1–8 information bits of codes are received, and if there is a number of equal codes in the ninth bit of the code recognition signal, it enters the 9th bit of register 88. From register 88, the code is issued with a signal from key 97 already with a frequency 20 MHz While the codes 88 without the identification signal in the 9th category arrive in the register 88, they enter through the public keys in block 89 into the third register 90, and from it they are issued by the signal U _iss1 from the key 94 to the decoder input. The signal U _vyd1 when issuing the code and resets the bits of register 90. When the code 88 receives an identification signal in the ninth digit, the signal from the ninth category of register 88 closes the keys in block 89 / input 2 /, closes the keys 94, 96, 97, opens the key 96 and the keys in block 91. The issuance of codes from the register 88 is interrupted, and the drive 87 codes accumulates the codes of the frame, as it continues to receive codes. The code of the number of equal codes through the public keys of block 91 enters the subtractive counter 92 pulses, to the counting input of which from the key 95 pulses of 20 MHz are received. The pulse from the key 95 comes in and as a signal U _vy2 to the second control input of the register 90 and outputs the code contained in it, but does not reset it. Therefore, while the counter 92 is subtracting, the same code is issued from register 90, these codes were removed when the stream was compressed in the encoder on the transmitting side. From the output of register 90 there is a 100% restored stream of codes. From register 90, only 8-bit codes with a sampling rate of 20 MHz go to block 62. Upon completion of the subtraction in counter 92, a code of zeros enters decoder 93. From the output of the decoder 93, the signal simultaneously closes the keys in block 91, closes the key 95, opens the keys in block 89 / input I / and keys 94, 96, 97. From drive 87, codes are again sent to register 88, from it through the keys of block 89 - in register 90, the processes are repeated. The decoder throughput is determined by the response time of 10.5 ns of the counter 92, which is from 100IE137 microcircuits [9, p. 428], plus the response time of the decoder 93 6 ns / 100ID161 [9, p. 433]. Code stream recovery rate up to 50 MB / s. Recovered stream of codes with a frequency of 20 MHz and the number of samples per line 800 pieces / 200 × 4 coefficients. compression / arrives at the input of block processing / doubling / codes / 800 × 2 /. Doubling of samples is performed by obtaining intermediate / average / codes between each passing and the following code. The blocks perform the addition of codes and the division of the sum code into two, and the division is carried out without time: by dropping the least significant digit in the sum code, as when dividing the decimal number by ten. The discarding of the least significant bit in the sum code is performed by connecting the outputs of the adder 105 / Fig. 10/ and the outputs of the registers 106 and 107.

Adder output 0 one 2 3 four 5 6 7 8 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ register outputs one 2 3 four 5 6 7 8

, т.е. 40 МГц. Процесс сложения в сумматоре 105 занимает 25 нс, сумматор может быть выполнен из микросхем К555ИМ6 [9, с.258]. После включения питания в регистрах 101-104 /фиг.10/ нули. С приходом первого импульса 20 МГц в триггер 98 с его первого выхода сигнал U_выд1 одновременно: выдает "код 0" с регистра 102 на первые входы сумматора 105, из регистра 103 выдает "код 0" в регистр 107 и через диоды на вторые входы сумматора, сигналы выдачи и обнуляют регистры 101-104, открывает ключи в блоке 99 на время прохода следующего кода через ключи, регистры 101 и 102 заполняются кодом "код 1. В сумматоре идет сложение "код 0+код 0". По окончании сложения код суммы из сумматора идет на выход и при этом делится на 2. Код №1

. Регистры 106 и 107 выполняют хранение кодов на 50 нс, причем первая часть хранения 25 нс приходится на время сложения кодов в сумматоре 105. С приходом второго импульса 20 МГц в триггер 98 он же обнуляет сумматор, а сигнал со второго выхода триггера U_выд2 одновременно: выдает из регистра 107 на выход код №2 "код 0", с регистра 101 "код 1" в регистр 106 и через диоды в сумматор 105, с регистра 104 "код 0" в сумматор, открывает ключи в блоке 100, и регистры 103, 104 заполняются кодом "код 2". В сумматоре идет сложение "код 0 + код 1", по окончании сложения код суммы идет на выход с делением его на 2: код №3

. С приходом третьего импульса на вход триггера он обнуляет сумматор, а сигнал с его первого выхода U_выд3 одновременно: выдает с регистра 106 код №4 "код 1" на выход блока 62, из регистра 102 "код 1" в сумматор, из регистра 103 "код 2" в регистр 107 и через диоды в сумматор 105, открывает ключи в блоке 99, и регистры 101, 102 заполняются кодом "код 3". В сумматоре идет сложение "код 1 + код 2", код суммы идет с делением на выход: код №5

. С приходом четвертого импульса в триггер 98 он обнуляет сумматор, а сигнал U_выд4 со второго выхода триггера одновременно: выдает код №6 "код 2" из регистра 107 на выход, с регистра 101 выдает "код 3" в регистр 106 и через диоды в сумматор, с регистра 104 "код 2" в сумматор, открывает ключи в блоке 100, и регистры 103, 104 заполняются кодом "код 4". В сумматоре идет сложение с делением на 2, код №7

.Bit 0 means transfer to the high bit with the sum of codes in the adder 105. Doubling the samples in a row reduces the code repetition period by half, which is 25 ns

, i.e. 40 MHz. The addition process in the adder 105 takes 25 ns, the adder can be made of K555IM6 microcircuits [9, p. 258]. After turning on the power in the registers 101-104 / Fig.10/ zeros. With the arrival of the first 20 MHz pulse to trigger 98 from its first output, the signal U _vyd1 simultaneously: provides a "code 0" from register 102 to the first inputs of the adder 105, from register 103 gives a "code 0" to register 107 and through diodes to the second inputs of the adder , the issuing signals and reset the registers 101-104, opens the keys in block 99 while the next code passes through the keys, the registers 101 and 102 are filled with the code "code 1. In the adder, the addition is" code 0 + code 0 ". At the end of addition, the sum code from the adder goes to the output and at the same time is divided by 2. Code No. 1

. Registers 106 and 107 store the codes for 50 ns, the first part of the storage being 25 ns during the addition of codes in the adder 105. With the arrival of a second 20 MHz pulse in trigger 98, it also resets the adder, and the signal from the second output of trigger U _vyd2 simultaneously: gives code No. 2 "code 0" from register 107 to output, from register 101 "code 1" to register 106 and through diodes to adder 105, from register 104 "code 0" to adder, opens the keys in block 100, and registers 103 , 104 are filled with the code "code 2". In the adder is the addition of "code 0 + code 1", at the end of the addition, the sum code goes to the output by dividing it by 2: code No. 3

. With the arrival of the third pulse at the trigger input, it resets the adder, and the signal from its first output is U _vd3 simultaneously: it sends code No. 4 "code 1" from register 106 to the output of block 62, from register 102 "code 1" to the adder, from register 103 "code 2" to the register 107 and through the diodes to the adder 105, opens the keys in block 99, and the registers 101, 102 are filled with the code "code 3". In the adder is the addition of "code 1 + code 2", the sum code is divided by the output: code No. 5

. With the arrival of the fourth pulse in trigger 98, it resets the adder, and the signal U _vy4 from the second output of the trigger at the same time: gives code No. 6 "code 2" from register 107 to the output, from register 101 issues "code 3" to register 106 and through diodes to the adder, from register 104 "code 2" to the adder, opens the keys in block 100, and the registers 103, 104 are filled with the code "code 4". In the adder is addition with division by 2, code No. 7

.

. С приходом шестого и следующих импульсов в триггер 98 процессы повторяются. Выходы 0-7 сумматора 105 и выходы 1-8 регистров 106, 107 поразрядно объединены и являются выходами блока 62 /67, 74/. Коды с частотой 40 МГц в параллельном виде поступают на информационные входы накопителей 63, 68, 75 кодов кадра.With the arrival of the fifth pulse in the trigger 98, it resets the adder 105, and the signal from the first output of the trigger U _vyd5 at the same time: issues code 8 "code 3" from register 106, issues 3 code from register 102 to the adder, 103 "code from register 103 4 "into the register 107 and through the diodes to the adder, opens the keys in block 99, and the registers 101, 102 are filled with the code" code 5 ". In the adder is the addition of "code 3 + code 4", and the sum code is divided by the output: code number 9

. With the arrival of the sixth and subsequent pulses in the trigger 98, the processes are repeated. The outputs 0-7 of the adder 105 and the outputs 1-8 of the registers 106, 107 are bitwise integrated and are outputs of the block 62/67, 74 /. Codes with a frequency of 40 MHz in parallel are fed to the information inputs of drives 63, 68, 75 frame codes.

The work of the blocks 63, 68, 75, 11, 12.

The code signals in block 63 are fed to the third inputs of the bits of 8 registers 112 _1-8 . The filling of the line registers begins with the opening of the frame signal U _to 25 Hz of the first key 109 in the first block 108 ₁ registers / 11 /. The key 109 passes pulses U _d 40 MHz to the input of the pulse distributor 111, the clock pulses from which are sequentially fed to the first / clock / bit inputs in parallel with eight registers 112. By filling the registers 112 from the last output / 1600th / block 111, the signal U _З closes key 109 and as a control output signal opens the key 109 in the next block 108 ₂ registers, registers 112 which are filled with codes of the second line. For a frame period of 40 ms, the registers 112 of all blocks 108 _1-1000 registers are sequentially filled with codes. From block 108 _{1000, the} output control signal is supplied in parallel to the fourth control inputs of all blocks 108 (Fig. 11/) and opens the second keys 110 / Fig. 12/ in them, which pass one signal U _output , which synchronously generates from all blocks of 108 registers frame codes in the shaper 64/69, 76 / control signals / 6 /. Each drive of frame codes 63, 68, 75 has 12.8 × 10 ⁶ outputs / 1600 × 8 × 1000 /, which are connected to the same inputs in blocks 64, 69, 76, each of which has 1.6 × 10 ⁶ converters "code - the number of pulses of radiation". The outputs of the three blocks 64, 69, 76/3 × 1.6 × 10 ⁶ / 4.8 × 10 ^{6 are} connected to the same inputs in the LED screen 77. Due to the large number of connections, the execution of frame code storage devices and control signal conditioners must be performed on the back side of the SD screen, in a single and non-separable design with it.

System operation.

FEP 1 generates analog video signals R, G, B, which are converted by ADCs 7-9 at a frequency of 20 MHz into 8-bit codes. Codes enter encoders 14, 15, 16, in which the code streams are compressed with a compression ratio of at least 4. From the encoders, the compressed code streams with a frequency of 5 MHz are fed to the first and second information inputs of the code generator 17, the audio inputs of which are 3 and 4 signals from the ADC 10, 11, the fifth and sixth information inputs of block 17 receive the SSI and CSI codes. In block 17, the codes of color signals are converted from parallel to serial, and the unit symbols in them are replaced from pulses by positive and negative half-sinusoids of the 70 MHz monofrequency. The output signal from block 17 modulates the carrier frequency in the amplitude modulator 24. Information of codes of color signals, sound and clock pulses of the SSI, CSI is transmitted by the upper side frequency of the modulated carrier. The receiving side receives radio signals in a single path for receiving and processing codes, performs bipolar amplitude detection, selects the clock pulses of the SSI, CSI, the representation of unit symbols returns to the pulses. The signal code R and 1-4 bits of the code G go to the first receive register 59 / Fig.6/, the signal code B and 5-9 bits of the code G go to the second receive register 71. Decoders 61, 66, 73 restore the original code streams, then blocks 62, 67, 74 double the number of samples in rows. For the first period of the frame, the drives 63, 68, 75 focus all the frame codes, and the signal U _{to the} next frame simultaneously outputs all the frame codes of the R, G, B signals to their control signal generators 64, 69, 76, in which the codes are converted to the number of pulses emissions of LEDs in the frame period. The video mode 1600 × 1000 × 25 Hz is reproduced on the LED screen 77. The system lacks horizontal and vertical scans; two sound channels reproduce stereo sound. System specifications in table 2.

table 2 Specifications Values Transmission side Carrier frequency 1050 MHz / option / Transmission of information codes R, G, B upper lateral frequency 1120 MHz Occupied band on air with stability carrier frequency 10 ^-7 ± 112 Hz or 224 Hz System Clock 70 MHz Imaging FDI matrix ADC Sample Rate 20 MHz Lowest Flow Compression four codes Frame Rate / Line Frequency 25 Hz / 25 kHz ADC output video mode 1000 _pp × 800 _count × 25 Hz Receiving side Playable video mode 1000 _pp × 1600 _count × 25 Hz Frame resolution 1.6 × 10 ⁶ pixels Image playback LEDs on the screen 1600 × 1000 mm / option /

Used sources.

1. Patent No. 2214693, cl. H04N 11/24, bull. 29 from 10.20.03, prototype.

2. Murakhovsky V.I. Computer device. M., 2003, p. 522, 553.

3. Kolesnichenko OV, Shishigin I.V. PC hardware. 5th ed., St. Petersburg, 2004, p. 832, 833, 835.

4. Radio transmitting devices. M.S. Shumilin et al., M., 1981, p. 234, 235.

5. "Home computer" No. 12, 2006, p. 43.

6. "Radio" No. 9, 2004, p. 47.

7. Radio communications, broadcasting and television. Ed. A.D. Fortushenko, M., 1981, p. 146.

8. Barkan V.F., Zhdanov V.K. Amplification and impulse technology. M., 1981, p. 209.

9. Digital integrated circuits. Minsk, 1991, p. 258, 279, 272, 428, 433.

Claims (1)

Television system  containing the transmitting side,  including photoelectric converter / photomultiplier /,  comprising a lens and three preamplifiers,  and including the first one,  second and third analog-to-digital converters / ADC / video signal,  the inputs of which are connected to the outputs of the corresponding pre-amplifiers of the solar cells,  the first and second ADCs of the sound signal,  to the information inputs of which a sound signal is applied,  serially connected master oscillator of sinusoidal oscillations and frequency synthesizer,  code generator  the corresponding information input of which is connected to the output of the first ADC sound signal,  first and second self-propelled pulse distributors / SRI /,  the outputs of the first SRI are combined,  and the combined output is connected to the corresponding information input of the code generator,  the input of the first SRI is connected to the second output of the code generator,  the input of the second SRI is connected to the sixth output of the frequency synthesizer,  and its outputs are combined,  the combined output is connected to the corresponding information input of the code generator,  the first output of the frequency synthesizer is connected to the control / clock / inputs of the first to third ADCs of the video signal,  the second - to the first control inputs of the first and second ADCs of the sound signal and to the corresponding control input of the code generator,  the third - to the second control inputs of the first and second ADC sound signal,  the fourth - to the corresponding input of the code generator,  fifth - to the corresponding input of the code generator and to the third control inputs of the first and second ADCs of the sound signal,  radio transmitter  containing a serially connected carrier frequency amplifier,  amplitude modulator  the second input of which is connected to the first output of the code generator,  and an output amplifier,  the code generator comprises four channels, the first channel includes a first block of AND elements connected in series  the first and second elements OR and the first output key,  and the first self-propelled pulse distributor / SRI /,  the second channel includes a series-connected second block of elements AND,  the third and fourth elements OR and the second output key,  and second SRI,  the third channel includes a third block of AND elements,  fifth element OR,  the output of which is connected to the second input of the second OR element,  and the third SRI,  the fourth channel includes a fourth block of AND elements,  sixth element OR,  the output of which is connected to the second input of the fourth OR element,  and the fourth SRI,  the second inputs of the first,  second  third  the fourth blocks of elements AND are connected to the outputs, respectively, of the first,  second  third and fourth SRI,  the shaper codes include the first and second keys and sequentially connected pulse counter and decoder,  the output of the first key is connected to the inputs of the first and second SRI,  the output of the second key is connected to the inputs of the third and fourth SRI,  the first output of the decoder is connected to the first control input of the first key,  the second output of the decoder is connected to the second control input of the first key and to the first control input of the second key,  the third output of the decoder is the second output of the code generator,  whose first output is the combined outputs of the output keys,  the first inputs of the blocks of elements And the third and fourth channels are the corresponding information inputs of the code generator,  the third input of the fourth OR element is also the corresponding information input of the code generator,  whose control inputs are:  one - the combined signal inputs of the first and second keys and the counting input of the pulse counter,  to others, the combined signal inputs of the first and second output keys,  next is the control input of the pulse counter,  and containing the receiving side,  including antenna  Control block,  a path for receiving and processing video signal codes,  whose input is connected to the antenna,  and the second inputs are connected to the first group of outputs of the control unit,  channel for generating control signals,  a video information display device and two sound channels,  the path for receiving and processing codes of video signals contains a series-connected unit for receiving radio signals,  whose first input is connected to the antenna,  the second group of inputs is connected to the first group of outputs of the control unit,  radio frequency amplifier  bipolar amplitude detector,  signal channel R,  signal channel G and signal channel B,  the signal channel R contains a first pulse shaper,  the input of which is connected to the first output of a bipolar amplitude detector,  signal register R and code processing unit,  the signal channel contains a second pulse shaper,  the input of which is connected to the second output of the bipolar amplitude detector,  signal register B and code processing unit,  signal channel G contains a signal register G and a code processing unit,  the channel for generating control signals contains sequentially connected block selection horizontal sync pulse / SSI /,  the first input of which is connected to the output of the first pulse shaper in the signal channel R,  frequency synthesizer  key,  pulse counter and decoder,  and a frame sync pulse allocation unit / CSI /,  the first input of which is connected to the output of the second pulse shaper in the signal channel B,  the second inputs of the frequency synthesizer are connected to the second group of outputs of the control unit,  the first output of the frequency synthesizer is connected to the signal input of the key,  the second output is connected to the corresponding control inputs of the first and second sound channels,  the third output is connected to the third input of the radio signal receiving unit,  the fifth output is connected to the control inputs of the code processing units in the signal channels R,  G  AT,  the first output of the decoder is connected in parallel to the corresponding control inputs of the first and second sound channels,  the second output of the decoder is connected to the corresponding control inputs of the first and second sound channels and to the control inputs of the pulse counter and key,  the first control input of which is connected to the output of the SSI allocation block,  the information input of the first sound channel is connected to the output of the pulse shaper in the signal channel R,  the information input of the second sound channel is connected to the output of the pulse shaper in the signal channel B,  code processing units are identical,  each includes a trigger,  the input of which is the control input of the block,  about first to fourth registers,  adder,  fifth and sixth registers and 16 diodes,  the first to eighth inputs of the first and second registers are bitwise combined,  the outputs of the first register are connected to the inputs of the fifth register and through the diodes to the first inputs of the adder,  the outputs of the second register are connected to the first inputs of the adder,  the first to eighth exits of the third and fourth registers are bitwise combined,  the outputs of the third register are connected to the inputs of the sixth register and through diodes to the second inputs of the adder,  to which the outputs of the fourth register are connected,  the first trigger output is connected in parallel to the control inputs of the second,  third and fifth registers,  the second trigger output is connected in parallel to the control inputs of the first,  fourth and sixth registers,  characterized in  that the first and second keys are entered on the transmitting side,  the control inputs of which are combined and connected to the sixth output of the frequency synthesizer,  introduced first,  second and third encoders,  the information inputs of which are connected to the outputs of the first,  second  third ADC video signal  the control inputs of the encoders are combined and connected to the second output of the frequency synthesizer,  the first to ninth outputs of the first and first to fourth outputs of the second encoder are connected to the first information input of the code generator,  the fifth to ninth outputs of the second encoder and the first to ninth outputs of the third encoder are connected to the second information input of the code generator,  the third and fourth information inputs of which are connected respectively to the outputs of the first and second ADCs of the sound signal,  the fifth and sixth information inputs of the code generator are connected to the outputs of the first and second SRI,  the signal input of the first key and the third control input of the code generator are connected to the fifth output of the frequency synthesizer,  to the first output of which the signal input of the second key is connected,  the first and second control inputs of the code generator are connected respectively to the second and fourth outputs of the frequency synthesizer,  the seventh output of which is connected to the input of the carrier frequency amplifier of the radio signal transmitter,  in FEP introduced a matrix of FDI,  the photosensitive side of which is located in the focal plane of the lens,  the first and second control inputs of the FDI matrix are connected to the outputs of the first and second keys,  from the first to the third outputs of the FDI matrix are connected respectively to the inputs of the first,  second  third preamplifiers,  the first to third encoders are identical,  each contains a series-connected register,  comparison chart  pulse counter and decoder,  series-connected block of delay elements,  key block and buffer storage of frame codes,  information inputs of the encoder are bitwise integrated 1-8 inputs of the register,  the first inputs of the comparison circuit and 1-8 inputs of the block of delay elements,  the outputs are 1-9 outputs of the buffer code storage frame  the control input of which is the control input of the encoder,  the first output of the comparison circuit is connected to the first control input of the register,  to the counting input of the pulse counter and to the second control input of the key block,  the second and third outputs of the comparison circuit are combined,  the combined output is connected to the second control input of the register,  to the first control input of the key block,  to the first input of the pulse counter and to the ninth input of the buffer storage of frame codes,  1-8 outputs of the pulse counter are connected to the inputs of the decoder and through diodes to the first to eighth inputs of the buffer storage of frame codes,  the decoder output is connected to the second control input of the pulse counter,  and through the diode to the first control input of the key block,  in the code generator first  second  the third and fourth information inputs are the first inputs of the elements And the first,  second  third and fourth blocks of elements And,  a third key is entered into the code generator,  the output of which is connected to the third input of the second OR element,  the signal input of the third key is the fifth information input of the code generator,  the sixth information input of which is the third input of the fourth OR element,  the third output of the decoder is connected to the second control input of the second key,  signal inputs of the first,  the second keys and the counting input of the pulse counter combined with them are the first control input of the code generator,  the combined signal inputs of the first and second output keys are the second control input,  the control input of the pulse counter is the third control input and the control input of the third key is the fourth control input of the code generator,  on the receiving side a flat panel LED screen / LED screen / is introduced,  in the channel of the signal R introduced the first receiving register,  the information input of which is connected to the output of the first pulse shaper,  the outputs of the first to ninth bits of the receiving register are connected to the inputs of the signal register R,  decoder introduced  information inputs of which are connected to the first to ninth outputs of the signal register R,  and the first to eighth outputs of the decoder are connected to the first to eighth inputs of the code processing unit,  introduced sequentially connected drive codes frame and driver control signals,  information inputs of the frame code storage device are connected to the first to eighth outputs of the code processing unit,  in the channel of the signal entered the second receiving register,  the information input of which is connected to the output of the second pulse shaper,  the outputs of the first to ninth bits of the second receiving register are connected to the inputs of the signal register B,  decoder introduced  information inputs of which are connected to the first to ninth outputs of signal register B,  and the first to eighth outputs of the decoder are connected to the first to eighth inputs of the code processing unit,  and sequentially connected frame code storage device and control signal generator,  information inputs of the frame code storage device are connected to the first to eighth outputs of the code processing unit,  a decoder is introduced into the signal channel G,  the information inputs of which are connected to the first to ninth outputs of the signal register G,  the inputs of the first or fourth bits of which are connected to the outputs of 10-13 bits in the first receiving register,  and the inputs of the fifth to ninth digits are connected to the outputs of the tenth to fourteenth digits in the second receiving register,  1-8 decoder outputs are connected to 1-8 inputs of the code processing unit,  introduced sequentially connected drive codes frame and driver control signals,  information inputs of the frame code storage device are connected to 1-8 outputs of the code processing unit,  the first control inputs of the first and second receiving registers are combined and connected to the sixth output / 70 MHz / frequency synthesizer,  second control inputs of the first and second receiving registers,  control inputs of the signal registers R,  G  In and the first control inputs of the decoders are combined and connected to the first output / 5 MHz / frequency synthesizer,  the second control inputs of the decoders are combined and connected to the fifth output / 20 MHz / frequency synthesizer,  to the fourth output of which the combined third control inputs of the / 40 MHz / frame code storage devices are connected,  the second control inputs of which are combined and connected to the output of the SSI allocation block,  the first control inputs / 25 Hz / drive codes of the frame and the control inputs of the shapers of the control signals are combined and connected to the output of the allocation unit KSI,  the outputs of the control signal conditioners are connected to the corresponding inputs of the LED screen,  which contains screen glass and a matrix made of emitting elements made in it according to the frame resolution number / 1600 × 1000 /,  each radiating element includes three LED cells,  each of which emits one of the primary colors R,  G  AT,  LED cell / LED cell / includes a white LED and the corresponding color filter on the emitting side,  the control input of each LED is connected to the corresponding output of the corresponding driver of control signals,  the information input of the first sound channel is connected to the output of the first pulse shaper,  the information input of the second sound channel is connected to the output of the second pulse shaper,  decoders are identical  each includes a series-connected first register,  frame code storage  second register  first block of keys and third register,  serially connected second block of keys,  subtracting pulse counter and decoder,  first to fourth keys,  information input of the decoder are the first to ninth inputs of the bits of the first register,  the output of the decoder is 1-8 outputs of the third register,  the first control input is the combined first control input of the first register and the signal input of the third key,  the second control input is the combined signal inputs of the first,  second and fourth keys,  the output of the first key is connected to the first control input of the third register,  the second control input of which and the counting input of the subtracting pulse counter are connected to the output of the second key,  the third key output is connected to the control input of the frame code storage device,  the output of the fourth key is connected to the control input of the second register,  the output of the ninth category of which is connected in parallel to the second control inputs of the first,  third and fourth keys,  to the first control input of the second key,  to the second - the control input of the first block of keys and to the first control input of the second block of keys,  the decoder output is connected in parallel to the first control input of the first key block to the second control input of the second key block,  to the first control inputs of the first,  third and fourth keys and to the second control input of the second key,  the first and second key blocks are entered into each code processing block,  1-8 inputs of which are bitwise combined and are informative inputs of the block,  the bitwise combined inputs of the first and second registers are connected to the outputs of the first block of keys,  the bitwise combined inputs of the third and fourth registers are connected to the outputs of the second block of keys,  the control input of the first block of keys is connected to the first output of the trigger,  the control input of the second block of keys is connected to the second output of the trigger,  1-8 outputs of the fifth and sixth registers and 0-7 outputs of the adder are bitwise combined and are 1-8 outputs of the code processing unit,  frame code drives are identical,  the information inputs of each are connected to the outputs of the code processing unit of their channel,  frame code store includes register blocks according to the number of frame lines,  information inputs are bitwise combined the first to eighth inputs of all register blocks,  control inputs are:  the first is the first control input of the first block of registers,  the second is the combined second control inputs of the register blocks,  the third is the combined third control inputs of the register blocks,  the control output of each previous block of registers is the first control input of each subsequent block of registers,  the control output of the last / 1000 / register block is connected in parallel to the fourth control inputs of all register blocks,  the outputs of the drive code frame are parallel outputs of all blocks of registers / 1600 × 8 × 1000 /,  register blocks are identical,  each includes the first and second keys,  pulse distributor and eight registers,  the information input is the bitwise combined third inputs of the bits of eight registers,  the outputs are the parallel outputs of all bits of eight registers / 1600 × 8 /,  control inputs are:  the first is the first control input of the first key,  the second is the signal input of the second key,  the third is the signal input of the first key,  fourth - the first control input of the second key,  the output of the first key is connected to the input of the pulse distributor,  whose outputs are sequential,  starting from the first  connected to the first / clock / control inputs of the bits of eight registers,  the last output of the pulse distributor is connected to the second control input of the first key and is the control output,  connected to the first control input of the next block of registers,  the output of the second key is connected to the second inputs of the bits in parallel to eight registers and to the second control input of the second key,  control signal generators are identical,  each includes a pulse shaper unit,  the input of which is the control input of the driver of the poisonous signals,  and converters "code - the number of pulses of radiation" by the number of frame resolutions / 1600 × 1000 /,  each of the converters contains a decryptor connected in series,  1-8 whose inputs are the inputs of the Converter,  a key block of 255 keys and an output key,  self-propelled pulse distributor / SRI / from the corresponding number of digits,  the outputs of which are connected to the signal inputs of the corresponding keys in the key block,  and power source  the output of which is connected to the signal input of the output key,  the corresponding outputs of the decoder are connected to the control inputs of the corresponding keys in the key block,  whose outputs are combined  the combined output is connected to the control input of the output key,  the output of which is the output of the Converter "code - the number of pulses of radiation",  the block of pulse shapers includes a pulse shaping circuit according to the number of converters "code - the number of pulses of radiation",  the output of each pulse shaping circuit is connected to the SRI input of its converter,  the information inputs of the driver of the control signals are the inputs of the decoders of all converters,  the outputs are the outputs of all converters,  the block allocation CSI and block allocation CSI identical  each includes a pulse counter,  decoder,  NOT element and two diodes,  information input is the counting input of the pulse counter,  to which the input of the element is NOT connected,  the control input is the combined control input of the pulse counter and the output of the element is NOT,  through the first diode connected to the output of the corresponding pulse shaper,  The outputs of the 1-3 senior bits of the pulse counter are connected to 1-3 inputs of the decoder,  the output of which is the output of the unit and is connected through the second diode to the control input of the pulse counter and to the output of the element NOT.

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