RU2351094C1 - Stereotelevision system - Google Patents

Abstract

FIELD: physics; radio.

SUBSTANCE: present invention pertains to wireless communication technology and can be used for digital television broadcasting. The outcome is achieved by that, in the stereotelevision system, at the transmitting side in the photoelectric converter, there are two reflecting prisms, a moveable flat mirror, a trigger and an actuating mechanism. The radio signal transmitter has two channels. At the receiving end there is a flat panel photodiode screen/LED-screen/ and in each signal channel R, G, B there is a first and second code accumulators and a control signal unit.

EFFECT: reduced power consumption of the system, increased brightness of the image and accuracy of colour transfer.

23 dwg

Description

The invention relates to radio communications technology and can be used for digital television broadcasting.

The prototype adopted "Stereotelevision System" [1], containing on the transmitting side a photoelectric converter / photomultiplier /, forming two images of the same space, six ADCs of a video signal, two ADCs of a sound signal, a sinusoidal oscillation generator and frequency synthesizer, three code shapers, two self-propelled pulse distributors , pulse counter, trigger, two keys and a transmitter of three channels, on the receiving side containing an antenna, a control unit, three paths for receiving and processing codes of video signals, a control channel signals, two channels of sound reproduction and a flat-panel LCD monitor. Each path for the reception and processing of video signal codes includes a series-connected radio signal receiving unit, a radio frequency amplifier and a bipolar amplitude detector, first and second pulse shapers, and a channel of one of the three signals R, G, B, each of which includes the first and second signal registers / R, G, B /, code processing unit / doubling samples /, the first delay block and the adder, the second delay block, the first and second row code stores. The receiving side contains an IR transmitter on the LCD monitor body and includes ZD glasses with an IR receiver on their frame. The transmitting side performs photoelectric conversion in parallel to the right and left frames of the stereo pair, encodes their signals in 8-I, bit codes and transmits the information of the codes with three radio channels of the transmitter. The video mode on the transmitting side is 512 _lines × 640 _samples × 60 Hz. The receiving side receives three radio signals in parallel with three reception paths, amplifies, detects, doubles the samples in lines from 640 to 1280, doubles the number of lines from 512 to 1024, selects horizontal sync pulses / SSI /, stereo pulses / SIS /, and plays on the LCD screen monitor sequentially right and left frames of a stereo pair with a frequency of 60 Hz / 30 + 30 /. The viewer perceives the image surround through ZD glasses. Video mode on the LCD monitor screen is 1024 × 1280 × 60 Hz. The disadvantages of the prototype are: parallel conversion of the signals of the right and left frames complicates the photomultiplier, the transmission of information by three radio channels and two carriers increases the energy consumption of the system, the use of an LCD monitor reduces the accuracy of color reproduction and introduces inertia in the control of the image on the screen.

The purpose of the invention is to simplify the photomultiplier, reducing the energy intensity of the system, increasing the brightness of the reproduced image and the reliability of color reproduction. Technical results include a reduction in the photomultiplier of the second conversion channel, a reduction in the third transmission and reception channel in the system, an increase in image brightness at the receiving side, and color accuracy. The results are achieved by sequential photoelectric conversion of the right and then left frames of the stereo pair, the transmission of frame code information by two channels of the radio signal transmitter and at one carrier frequency, the increase in image brightness and color accuracy by introducing a flat-panel LED screen / LED screen / and control signal blocks on the receiving side. On the transmitting side, a video mode of 500 _pages × 800 _samples × 50 Hz is used, where 500 is the number of encoded lines in a frame on the transmitter side, 800 is the number of encoded samples in a line, 50 Hz is the frame rate. Each stereo pair includes sequentially the following right and left frames / 25 Hz + 25 Hz /, the frequency of stereo pairs 25 Hz. Information is transmitted by the upper and lower side frequencies of one carrier frequency. The line scan is progressive without reverse moves in both lines and frames. Sampling frequency in the ADC is

f _d = 500 _lines × 500 Hz × 800 _count = 20 MHz.

, длительность кадра 20 мск

. Частота колебания пьезодефлектора при развертке строк

. За один период колебания развертывается две строки. Период следования кодов видеосигнала

. Частота колебаний пьезодефлектора при развертке кадров 25 Гц: за один период развертываются два кадра: вниз - правый кадр, вверх - левый кадр. Тактовая частота на передающей сторонеLine frequency f _c = 500 × 50 Hz = 25 kHz, line duration 40 Moscow time

, frame duration 20 Moscow time

. Piezo deflector oscillation frequency when scanning lines

. For one period of oscillation, two lines are deployed. Video Signal Codes Period

. The frequency of oscillations of the piezoelectric deflector when the frame scan is 25 Hz: two frames are deployed in one period: down - the right frame, up - the left frame. Transmit Clock

f _t = 20 MHz × 8 bit = 160 MHz,

8 bits - the number of bits in the code. The carrier frequency of the transmitter is taken f _ns = 160 MHz × 15 = 2400 MHz, the upper side frequency f _vb = 2400 + 160 = 2560 MHz, lower side frequency

f _n.b. = 2400-160 = 2240 MHz. The video mode reproduced on the receiving side is 1000 _pages × 1600 _counts × 50 Hz. The resolution of the reproduced frame is 1000 × 1600 = 1600000 pixels.

The essence of the invention is that in a stereo television system containing on the transmitting side of the photoconductor, three ADCs, a frequency synthesizer, two code shapers, two self-propelled pulse distributors and a radio signal transmitter, on the receiving side, including two paths for receiving and processing video signal codes, a video information display device with an IR transmitter on its body, ZD glasses with an IR receiver on the frame, a channel for generating control signals and two sound reproduction channels, two reflective channels are introduced into the photomultiplier on the transmitting side ism, a movable plane mirror, the key, the trigger and the actuator, the radio transmitter is adapted two-channel and the reception side video display device is represented by a flat panel LED screen and each channel signal R, G, B enter the first and second drives codes and power control signals.

The transmitting side in Fig. 1, the formation of the raster in Fig. 2, the shape of the control voltages in Fig. 3, the structure of the digital streams in Fig. 4, the ADC of the video signal in Fig. 5, the piezoelectric reflector design in Fig. 6, the first code generator in Fig. 7, the second code generator in Fig. 8, the receiving side in Fig. 9, the circuit diagram of a bipolar amplitude detector in Fig. 10, the code processing unit in Fig. 11, the first delay block in Fig. 12, the frame code storage in Fig. 13 , the block of registers in Fig.14 and 15, the block of control signals in Fig.16, the LED cell in Fig.17, the composition and the matrix element frame in Fig. 18, the arrangement of the matrix elements in the LED screen in Fig. 19, the SSI horizontal sync pulse allocation unit in Fig. 20, the SIS stereo pair sync pulse allocation unit in Fig. 21, the frequency spectra of the transmitter signals in Fig. 22, temporary diagrams of the system in Fig.23.

The transmitting side contains / Fig. 1 / photoelectric converter 1 / photomultiplier /, which is a sensor of the video signals of two frames of the stereo pair / right and left /, generates three signals in succession first of the right frame R _P , G _P. In _P , then three video signals of the left frame R _L , G _L , V _L , includes the first 2 and second 3 reflective prisms with full internal reflection, changing the direction of the rays of the field of view by 90 ° [2 p.225], a movable plane mirror 4 s mirror coatings on both external planes with a vertical axis of rotation, the rotations of the mirror 4 are performed in the direction of the prism 2, then 90 ° in the direction of the prism 3, the rotation frequency of 50 Hz is performed in series with the first key 5, trigger 6 and the actuator 7 in accordance with the control trigger signals 6. The second reflective prism is located at an appropriate distance to the left of the right reflective prism 2, their optical axes are parallel and after reflection coincide with the geometric center of a flat mirror 4, located in the center of the distance between the reflective prisms 2 and 3, and having two fixed positions, the first under 45 ° to the sighting axis of the first reflective prism 2, the second under 45 ° to the sighting axis of the second reflective prism 3, at both positions, the sighting axis of the flat mirror 4 coincides with the optical axis of the FEZ lens 8, which includes a first amplifier 9 and a first piezoelectric deflector 10 connected in series with a reflector at the end, a first positive reference voltage source 11, a second negative reference voltage source 12, a second amplifier 13 and a second piezoelectric deflector 14 with an end-reflector in series, and a third positive reference voltage source 15 , the fourth negative reference voltage source 16, a horizontal scanning unit 17 from a driving generator 18 and an output stage 19, a vertical scanning unit 20 from the last of the connected element And 21, the master oscillator 22 and the summing amplifier 23, the first dichroic mirror 24 and the second dichroic mirror 25, located one after the other and against the reflector of the second piezoelectric deflector 14, first 26, second 27, third 28 micro lenses, first 29, second 30 , third 31 photodetectors, first 32, second 33, third 34 preamplifiers. The transmitting side includes a second key 35, first 36, second 37, third 38 ADCs of the video signal of colors R, G, B, respectively, a sinusoidal oscillation generator 39 and a frequency synthesizer 40 connected in series, the first 41 and second 42 code generators, the first self-propelled pulse distributor 43, serially connected two-bit counter 44 pulses and a second self-propelled distributor of pulses 45, the first 46 and second 47 ADCs of the sound signal, the input of which is given sound signals, the transmitter 48 radio signals from two channels. The first channel includes a carrier frequency amplifier 49 connected in series, an amplitude modulator 50 and an output amplifier 51, the second channel includes an amplitude modulator 52 and an output amplifier 53. Each of the amplitude modulators 50 and 52 consists of a ring modulator and a bandpass filter connected in series [3 p.234 ], filtering out one of the side frequencies in the spectrum of the amplitude-modulated carrier / Fig. 22/. Three ADCs 36, 37, 38 are identical (Fig. 5/), each includes an amplifier 54 and a piezoelectric deflector 55 with a reflector at the end, a positive reference voltage source 56, a negative reference voltage source 57, an emitter from a pulsed LED 58, aperture diaphragm 59, and a micro lens 60, line 61 of the multi-element photodetector and encoder 62. All piezoelectric deflectors 10, 14, 55 are end bimorph piezoelectric elements with a light reflector on the free end, are structurally made [4 p. the inner electrode 65, the first 66 and the second 67 outer electrodes. One end of the piezoelectric plates is fixed in the holder 68, and a light reflector 69 is located on the free end of the plates. The first code generator 41 includes / Fig. 7/ three channels.

The first channel includes a series-connected block of AND elements 70, a first 71 and a second 72 OR elements, and an output switch 73, and a self-propelled pulse distributor 74. The second channel includes a second block of 75 AND elements, a third 76 and a fourth 77 OR elements, and an output switch 78, and a self-propelled pulse distributor 79. The third channel includes two blocks 80, 83 AND elements, the fifth 81 and sixth 84 OR elements, and two self-propelled pulse distributors 82, 85, includes the first 86 and second 87 keys, and the pulse counter 88 in series, and a decoder 89, which has three output: the first is connected to the first control input of the key 86, the second is connected to the second control input of the key 86 and to the first control input of the key 87, the third is connected to the second control input of the second key 87 and is the second output of block 41, the first output of which is combined the output outputs of the output keys 73, 78. The first or third information inputs of the code generator 41 are: the first - the first inputs of block 70, the second - the first inputs of block 75 of elements AND, the third - the first inputs of blocks 80, 83 of elements I. The fourth information input of block 41 are the third inputs of the second and fourth elements OR 72, 77. The first control input is the combined inputs / 20 MHz / signal inputs of the keys 86, 87 and the counting input / U _mid / counter 88 pulses, the second is the combined signal inputs / 160 MHz / output keys 73, 78, the third - the manager input / 25 kHz / counter 88 pulses. The second generator 42 codes includes / Fig.8/ two channels. The first contains a series-connected block of 90 AND elements, the first 91 and second 92 OR elements, and an output switch 93, and a self-propelled pulse distributor 94, the second channel includes a series-connected first block of 95 AND elements, a third OR element 96, the output of which is connected to the second input the second second OR element 92 in the first channel, and the first self-propelled pulse distributor 97, and includes the second AND element block 98, the fourth 99 and the fifth 100 OR elements, and the output switch 101, and the second self-propelled distributor body 102 pulses. Code generator 42 includes first 103, second 104 keys, pulse counter 105 and decoder 106, the first to third outputs of which are connected: the first to the first control input of the key 103, the second to the second control input of the key 103 and the first control input of the key 104 , the third - to the second control input of the key 104. The information inputs are: the first - the first inputs of the block of 90 elements And the first channel, the second - the first inputs of the blocks 96, 98 of the AND elements, the third-third input of the element 92 OR, the fourth - the second input of the element 100 OR. The output is the combined outputs of the output keys 93, 101. The control inputs are: the first is the combined inputs / 20 MHz / keys 103, 104 and the counting input of the pulse counter 105, the second is the signal inputs / 160 MHz / output keys 93, 101, the third is the control input U _{0 of the} counter 105 pulses.

, 171_1-500. Информационным входом каждого накопителя кодов являются поразрядно объединенные 1-8 входы 500 блоков 171 регистров. Информационные входы накопителей кодов подключены: 118 к выходам сумматора 116, 119 к выходам второго блока 117 задержек, 126 к выходам сумматора 124, 127 к выходам блока 125, 139 к входам сумматора 137, 140 к выходам блока 138 задержек. Управляющими входами являются: первым - вход /50 Гц/ триггера 170, вторым - объединенные вторые управляющие входы /U_выд 25 кГц/ блоков 171_1-500, третьим - объединенные третьи управляющие входы /U_д 40 МГц/ блоков 171_1-500. Первый управляющий выход каждого предыдущего блока 171 регистров подключен к первому управляющему входу каждого последующего блока 171 регистров, первый управляющий выход последнего 171₅₀₀ блока через диод подключен параллельно к четвертым управляющим входам всех блоков 171 регистров. Второй управляющей выход каждого последующего блока 171 регистров подключен к пятому управляющему входу каждого предыдущего блока регистров, и второй управляющий выход первого блока 171 регистров через диод подключен параллельно к четвертым управляющим входам всех блоков 171_1-500 регистров. Первый выход триггера 170 подключен к первому управляющему входу первого блока регистров 171₁, второй выход триггера 170 подключен к пятому управляющему входу последнего блока 171₅₀₀ регистров. Выходами каждого блока накопителя кодов являются выходы всех блоков 171 регистров, которых 6400000/1600×8×500/. Блоки 171 регистров идентичны, каждый включает /фиг.14, 15/ первый 172, второй 173, третий 174 ключи, первый 175 и второй 176 распределители импульсов и восемь регистров 177_1-8. Информационными входами блока регистров являются поразрядно объединенные третьи входы разрядов восьми регистров 177. Выходами являются параллельные выходы всех разрядов восьми регистров 177, которых 12800/1600×8/. Управляющими входами блоков 171 регистров являются: первым - первый управляющий вход первого ключа 172, вторым - сигнальный вход /25 кГц/ третьего ключа 174, третьим - объединенные сигнальные входы /40 МГц/ первого 172 и второго 173 ключей, четвертым - первый управляющий вход третьего ключа 174, пятым - первый управляющий вход второго ключа 173. Первый управляющий вход первого ключа 172 в первом блоке 171₁ регистров подключен к первому выходу триггера 170, первый управляющий вход второго ключа 173 в последнем блоке 171₅₀₀ регистров является пятым управляющим входом и подключен к второму выходу триггера 170. Выход первого ключа 172 подключен к входу первого распределителя 175 импульсов, выходы которого последовательно с первого по 1600-й подключены к первым входам разрядов параллельно восьми регистров 177. Последний выход /1600/ распределителя 175 импульсов в блоках 171_1-499 является первым управляющим выходом, подключенным к первому управляющему входу каждого последующего блока 171 регистров. Последний выход /1600/ распределителя 175 импульсов в блоке 171₅₀₀ регистров является первым управляющим выходом и подключен через диод параллельно к четвертым управляющим входам всех блоков 171 регистров. Выход второго ключа 173 подключен к входу распределителя 176 импульсов, выходы которого последовательно подключены, начиная с первого, к первым входам разрядов параллельно восьми регистров 177 в обратном порядке: первый выход подключен к первым входам последних/1600/ разрядов регистров, последний 1600-й выход подключен к первым входам первых разрядов восьми регистров. Последний выход блока 176 в блоках 171_2-500 регистров является вторым управляющим выходом, который от каждого последующего блока 171 регистров подключен к пятому управляющему входу каждого предыдущего блока 171_499-1 регистров. Последний выход /1600/ распределителя 176 импульсов в блоке 171₁ регистров является вторым управляющим выходом и подключен через диод к четвертым управляющим входам всех блоков 171 регистров. Выход третьего ключа 174 подключен параллельно к вторым входам всех разрядов восьми регистров 177 и к своему второму управляющему входу, прошедший импульс U_выд закрывает и ключ 174. Выходы накопителей кодов 118, 119, 126, 127, 139, 140 /фиг.9/ подключены к информационным входам блоков соответственно 120, 128, 141 управляющих сигналов, назначение которых выполнять преобразование "код - число импульсов" для получения управляющих сигналов к выходному ключу 181 для подключения источника питания к светодиодам. Число управляющих сигналов к выходному ключу 181 /фиг.16/ соответствует величине кода цветового сигнала. Каждый из блоков 120, 128, 141 содержит /фиг.16/ формирователь 178 импульсов и преобразователей "код - число импульсов" соответственно разрешения в кадре 1600000 /1600×1000/. Преобразователи идентичны, каждый включает последовательно соединенные дешифратор 179, блок 180 ключей, содержащий 255 ключей, и выходной ключ 181 и включает самоходный распределитель 182 импульсов и источник 183 питания светодиода. Входы блоков 182 объединены и подключены к выходу формирователя 178 импульсов, сигнальный вход каждого выходного ключа 181 подключен к выходу своего источника 183 питания. Информационным входом преобразователя являются с первого по восьмой входы дешифратора 179, имеющего 255 выходов, подключенных к управляющим входам U_от ключей в блоке 180. Самоходный распределитель 182 импульсов имеет 255 разрядов, каждый из которых имеет свой выход, который подключен к сигнальному входу соответствующего ключа в блоке 180. Выходы всех ключей блока 180 объединены, и объединенный выход подключен к первому управляющему входу U_от ключа 181. Исходное состояние выходных ключей 181 закрытое. Формирователь 178 импульсов формирует приходящий кадровый импульс по длительности и амплитуде и выдает его на входы всех самоходных распределителей 182 импульсов. Преобразователи "код - число импульсов" работают идентично. С приходом импульса запуска U_п с выхода блока 178 самоходные распределители 182 запускаются, по мере продвижения импульса по 255 разрядам с выхода каждого разряда сигналы поступают на сигнальные входы соответствующих ключей в блоке 180. При отсутствии кода на входе дешифратора 179 ключи в блоке 180 закрыты. С приходом кода в дешифратор 179 сигналы U_от его выходов открывают соответствующие ключи в блоке 180, которые пропускают на управляющий вход выходного ключа 181 импульсы последовательно с соответствующих разрядов блока 182. Длительность каждого импульса составляет 78 мкс

. Выходной ключ 181 открывается каждым импульсом с блока 180 на длительность 78 мкс, и соответствующий светодиод в СД-экранн зачитывается на длительность импульса 78 мкс, т.е. дает излучение. Блоки 180 и 182 производят равномерное распределение импульсов запитывания светодиода в периоде кадра. Пример распределения импульсов излучения в периоде кадра соответственно величине кода приводится в таблице. Выходами блока управляющих сигналов 120 являются выходы 1600000 выходных ключей 181, каждый из которых подключен к своему светодиоду в СД-экране.The receiving side includes / FIG. 9 / antenna, control unit 107 / channel selection /, first and second paths for receiving and processing video signal codes, a video information display device, a channel for generating control signals and two sound reproduction channels. The first path for receiving and processing codes of video signals receives and processes the codes of signals R _P , G _P and R _L , G _L and includes serially connected radio signal receiving unit 108, a radio frequency amplifier 109 and a bipolar amplitude detector 110, first 111 and second 112 pulse shapers, and includes a signal channel R containing series-connected register 113 of the signal R, block 114 for processing codes / doubling codes in line /, the first block 115 delays and the adder 116, the second block 117 delays and the entered first drive 118 codes / intermediate frame track /, a second drive 119 codes / current frame lines / and a control signal unit 120, and includes a signal channel G containing serially connected G signal register 121, code processing / code doubling unit 122, a first delay unit 123 and an adder 124, the second block 125 delays and entered the first drive 126 codes / intermediate lines of the frame /, the second drive 127 codes / current lines / and block 128 of the control signals. The second path for the reception and processing of codes of video signals receives and processes the codes of signals In _p , V _l , includes a block 129 for receiving radio signals, a radio frequency amplifier 130 and a bipolar amplitude detector 131, first 132 and second 133 pulse shapers and includes a signal channel B containing serially connected a signal B register 134, a code processing unit 135, a first delay unit 136 and an adder 137, a second delay unit 138 and a first code store 139, a second code store 140, and a control signal unit 141 are input. The receiving side includes a flat-panel LED screen 142 / LED screen /, an IR transmitter 143 on the housing of the LED screen, ZD glasses 144 with an IR receiver 145 on the frame of the ZD glasses. The operating side of the receiving side determines the channel for generating control signals, which includes a serially connected block 146 for selecting horizontal sync pulses / SSI /, a frequency synthesizer 147, a first key 148, a pulse counter 149 and a decoder 150, includes a stereo pair / SIS / sync pulses block 151 ₁ and a second key 151 ₂ . The receiving side includes identical first 152, second 153 sound reproduction channels. Each of the channels contains a converter of sound codes to analog signals / DAC /, a power amplifier and a loudspeaker. The image from the SD screen by the viewer is perceived as surround through the ZD glasses. When the right and left frames are played sequentially on the screen, the stereopairs of the glass of the ZD glasses alternately lose transparency and each eye sees its own frame. Glasses of glasses are made by the technology of LCD cells of the translucent type, used as electronically-controlled filters / shutters / [5 c.558-565]. With the arrival of the SIS signal in the IR transmitter 143, it emits an IR pulse received by the IR receiver 145, which provides a control signal to the LCD cells of the left glass of glasses, dimming it for 20 ms, then the IR receiver itself issues a second LCD control signal - cells of the right glass, darkened it for 20 ms, then the processes are repeated. Blocks 114, 122, 135 of the code processing are identical / 11 /, each includes a trigger 154, the input of which is the control input of the block, the first 155, the second 156 key blocks / 8 pieces each /, the first 157, the second 158, the third 159 the fourth 160 registers, the first 161 and second 162 blocks of delays, the adder 163 and 16 diodes. The information inputs of block 114 are the first and eighth inputs of the blocks 155, 156 of the keys, which are bitwise combined; they receive video signal codes in parallel form from register R 113 with a frequency of 20 MHz. The outputs are the bitwise combined outputs of the adder 163 and delay units 161, 162. The repetition rate of codes from blocks 114, 122, 135 40 MHz / after 25 ns /. Blocks 161, 162 carry out a delay of codes by 50 ns, the first half of which 25 ns falls on the time of addition of codes in the adder 163, which performs addition for 25 ns. The first delay blocks 115, 123, 136 are identical (Fig. 12/), each includes an And 164 element, the first 165, the second 166 keys, the first 167, the second 168 pulse distributors and eight registers 169 _1-8 each of which contains 1600 bits / each number of samples per line. Blocks 115, 123, 135 delay line codes by a line duration of 40 μs. The information input of the block is the bitwise integrated second inputs of the bits from the first to eighth registers 169. The outputs are the bitwise integrated 1-8 outputs of eight registers 169. The first and second control inputs of the block are the first / 50 Hz / and the second / 25 kHz / inputs of the And 164 element , the third control input is the combined signal inputs of the keys 165, 166. The first 118, 126, 139 and second 119, 127, 140 code stores are identical, each includes a trigger 170/13 / and blocks of 171 registers for the number of half lines of the frame

, 171 _1-500 . The information input of each drive code is bitwise integrated 1-8 inputs of 500 blocks of 171 registers. The information inputs of the code storage devices are connected: 118 to the outputs of the adder 116, 119 to the outputs of the second delay unit 117, 126 to the outputs of the adder 124, 127 to the outputs of the unit 125, 139 to the inputs of the adder 137, 140 to the outputs of the delay unit 138. The control inputs are: the first is the input / 50 Hz / trigger 170, the second is the combined second control inputs / U _output 25 kHz / blocks 171 _1-500 , the third is the combined third control inputs / U _d 40 MHz / blocks 171 _1-500 . The first control output of each previous block 171 registers is connected to the first control input of each subsequent block 171 registers, the first control output of the last 171 ₅₀₀ blocks through a diode is connected in parallel to the fourth control inputs of all blocks 171 registers. The second control output of each subsequent block 171 registers connected to the fifth control input of each previous block of registers, and the second control output of the first block 171 registers through a diode connected in parallel to the fourth control inputs of all blocks 171 _1-500 registers. The first output of the trigger 170 is connected to the first control input of the first block of registers 171 ₁ , the second output of the trigger 170 is connected to the fifth control input of the last block of 171 ₅₀₀ registers. The outputs of each block of code storage are the outputs of all blocks of 171 registers, of which 6400000/1600 × 8 × 500 /. Blocks 171 registers are identical, each includes /ig.14, 15 / first 172, second 173, third 174 keys, first 175 and second 176 pulse distributors and eight registers 177 _1-8 . The information inputs of the register block are the bitwise combined third inputs of the bits of the eight registers 177. The outputs are the parallel outputs of all the bits of the eight registers 177, of which 12800/1600 × 8 /. The control inputs of the blocks 171 registers are: the first is the first control input of the first key 172, the second is the signal input / 25 kHz / third key 174, the third is the combined signal inputs / 40 MHz / first 172 and second 173 keys, the fourth is the first control input of the third key 174, the fifth - the first control input of the second switch 173. The first control input of the first switch 172 in the first block ₁ of registers 171 is connected to first output of the flip-flop 170, a first control input of the second switch 173 in the last block of registers _171,500 is the fifth control input and connected to the second output of the flip-flop 170. The output of the first switch 172 is connected to the input of the first pulse distributor 175 which outputs sequentially from the first to 1600th connected to first inputs of parallel eight bits of the register 177. Last Out / 1600 / pulse distributor 175 in blocks 171 _1-499 is the first control output connected to the first control input of each subsequent block 171 registers. The last output / 1600 / of the 175 pulse distributor in the block 171 ₅₀₀ registers is the first control output and is connected via a diode in parallel to the fourth control inputs of all blocks 171 registers. The output of the second key 173 is connected to the input of the pulse distributor 176, the outputs of which are sequentially connected, starting from the first, to the first inputs of the bits in parallel of eight registers 177 in the reverse order: the first output is connected to the first inputs of the last / 1600 / bits of the registers, the last 1600th output connected to the first inputs of the first bits of eight registers. The last output of block 176 in blocks 171 of _2-500 registers is the second control output, which from each subsequent block of 171 registers is connected to the fifth control input of each previous block 171 _{499-1 of} registers. The last output / 1600 / of the pulse distributor 176 in the block 171 ₁ registers is the second control output and is connected via a diode to the fourth control inputs of all blocks 171 registers. The output of the third key 174 is connected in parallel to the second inputs of all the bits of the eight registers 177 and to its second control input, the transmitted pulse _Uout closes the key 174. The outputs of the codes 118, 119, 126, 127, 139, 140 / Fig. 9/ are connected to the information inputs of the blocks, respectively, 120, 128, 141 control signals, the purpose of which is to perform the conversion "code - the number of pulses" to receive control signals to the output key 181 for connecting the power source to the LEDs. The number of control signals to the output key 181/16 / corresponds to the value of the color signal code. Each of the blocks 120, 128, 141 contains (Fig. 16/) a pulse shaper 178 and converters "code-number of pulses", respectively, the resolution in the frame 1600000/1600 × 1000 /. The converters are identical, each including a decryptor 179 connected in series, a key block 180 containing 255 keys, and an output key 181, and includes a self-propelled pulse distributor 182 and an LED power supply 183. The inputs of the blocks 182 are combined and connected to the output of the pulse shaper 178, the signal input of each output key 181 is connected to the output of its power source 183. The information input of the converter is the first through eighth inputs of the decoder 179, which has 255 outputs connected to the control inputs U _{of the} keys in block 180. The self-propelled pulse distributor 182 has 255 bits, each of which has its own output, which is connected to the signal input of the corresponding key in block 180. The outputs of all the keys of block 180 are combined, and the combined output is connected to the first control input U _from key 181. The initial state of the output keys 181 is closed. The pulse shaper 178 generates an incoming frame pulse in duration and amplitude and provides it to the inputs of all self-propelled pulse distributors 182. Code-to-pulse converters work identically. With the arrival of the start pulse U _p from the output of block 178, self-propelled distributors 182 are started, as the pulse moves 255 bits from the output of each bit, the signals are fed to the signal inputs of the corresponding keys in block 180. If there is no code at the input of the decoder 179, the keys in block 180 are closed. With the arrival of the code in the decoder 179, the U signals _from its outputs open the corresponding keys in block 180, which pass pulses to the control input of the output key 181 in series from the corresponding bits of block 182. The duration of each pulse is 78 μs

. The output key 181 is opened by each pulse from block 180 for a duration of 78 μs, and the corresponding LED in the LED screen is read out for a pulse duration of 78 μs, i.e. gives radiation. Blocks 180 and 182 produce a uniform distribution of the power pulses of the LED in the frame period. An example of the distribution of radiation pulses in the frame period according to the code value is given in the table. The outputs of the control signal block 120 are the outputs of 1,600,000 output keys 181, each of which is connected to its own LED in the LED screen.

0 - no LED emitted,

1 2 3 ... 128 ... 255 - numbers of radiation pulses in the frame period. The distribution of radiation pulses in the period of the frame, at equal time intervals contribute to better reliability of color reproduction during image reproduction. The inertia of the applied LEDs is not more than 1 μs. Upon completion of the accumulation by blocks 118, 119, 126, 127, 139, 140 of the frame codes, the signal U _K 50 Hz starts in blocks 120, 128 and 141 all self-propelled valves 182/16 / and the signal codes R, G, B arrive synchronously in decoders 179 are converted to the number of control pulses in proportion to the size of the code. Each LED in the LED screen 142 is powered from a source 183 by the number of pulsed emissions, respectively, the value of the code. Flat-panel LED screen 142 is a set of matrix elements, respectively, of a frame resolution of 1600000/1600 × 1000 /, performed in the glass of the LED screen, and includes screen glass and matrix elements according to the number of frame resolutions. Each element includes three emitting LED cells / LED cells /, each of which emits one of the primary colors R, Q, B. The LED cell contains / FIG. 17 / a white LED 184 and a color filter 185 of the primary colors. Three LED cells make up the matrix element / Fig. 18/, the arrangement of the matrix elements and LED cells in the LED screen in Fig.19. The control input of each LED is connected to the output of its code-to-number of pulses converter in blocks 120 / signal R /, 128 / signal G /, 141 / signal В /. The level of brightness of the radiation of the LED cell is perceived by sight in proportion to the number of pulses of the radiation of the LED over the frame period. The total radiation of the three primary colors to the three LED cells R, G, B forms a color tone for vision and, accordingly, its brightness of one element / pixel /. As light-emitting diodes, super-bright white LEDs of the Nichia, Ledtronics, and Kingbright firms are used [6 p. 47]. The LEDs are executed by the method of microelectronic technology in the glass of the screen, the size of the LEDs is 0.25 × 0.25 mm / Fig.17/. Modern technologies allow each of the blocks 118, 119, 126, 127, 139, 140 and 120, 128, 142 to be executed in one chip. The size of one matrix element is 0.5 × 0.5 mm / Fig. 18/. The size of the LED screen 142 is:

horizontally 1600 × 0.5 mm = 800 mm,

vertically 1000 × 0.5 mm = 500 mm, diagonally 1886 mm, or 74 inches. Block 146 allocation of horizontal sync pulses SSI includes / Fig.20/ first 186, second 187, third 188 pulse counters, first 189, second 190 elements And, from the first 191 to third 193 elements NOT and a diode. With the arrival of three codes of 8 units 11111111 synchronously at the counting inputs of the counters, 11111111 at the block output, an SSI clock pulse of line / 25 kHz / appears. With other codes, at least one of them will have a zero at which the element will NOT reset all counters, and there will be no false SSI at the output of the block. Block 151 ₁ allocation of clock pulses of stereopairs SIS includes / Fig.21/ first 194, second 195 pulse counters, first 196 and second 197 elements And, two elements 198, 199 NOT and a diode. With the arrival of two codes of 8 units simultaneously at the counting inputs of the counters and at the input of the And element 197 of the SSI pulse from block 146, an SIS pulse of 25 Hz appears at the output of block 151 ₁ .

FEP 1 generates three analog video signals R _P , G _P , V _P right frame. The rays of the right field of view through the reflecting prism 2 and a flat mirror 4 in the first fixed position enter the lens 8, focusing the image in the plane of the reflector of the piezoelectric deflector 10. The reflector has a width of 0.01 mm and a length of 5 mm / 0.01 mm × 500 lines /, the dimensions of the deploying element 0.01 × 0.01 mm According to the control voltages (Fig. 3/) from the amplifier 9, the piezoelectric deflector 10 vibrates the end face with the reflector relative to the reflector of the piezoelectric deflector 14, scanning the right image. The period of the control voltage is equal to the duration of two lines / Fig.2/. Block 17 provides a linearly varying voltage in the water of an isosceles triangle / 3 /. The oscillation frequency of the piezoelectric deflector 10 12.5 kHz. The piezoelectric deflector 14 performs a frame scan of two frames: when scanning downward, the right frame of the stereo pair goes, while scanning upward there is a left frame. The piezoelectric deflector 14 oscillates at a frequency of 25 Hz, which is 50 frames per second. Frame scan without reverse moves. The width of the reflector of the piezoelectric deflector is 14 0.01 mm, the length is 8 mm / 0.01 mm × 800 counts /. The formation of the left frame is when you scan the piezoelectric deflector 14 up. At the end of the period of the right frame, the second pulse of 50 Hz arrives at the input of the first key 5, from the second output of trigger 6, a signal is sent to the actuator 7, which rotates the flat mirror 4 in one ms by 90 ° towards the second reflective prism 3 / second position /. The rays of the second field of vision of the left through the prism 3 of the mirror 4 into the lens 8. The following is a similar process for the formation of video signals of the left frame R _L , G _L , V _L. As the actuator 7, a PED piezoelectric motor is used [7 p.40], operating in step mode with a turn time of 1 ms, weight 10 g / 15 W /, controlled by signals from trigger 6. The summing amplifier 23 of the vertical scanning unit 20 performs the summation line voltage from the master oscillator 22 with pulses of 25 kHz line frequency. Each impulse of a line moves the next line at the end of its course (Fig.2/) by a step in one line, 500 lines are obtained, all active. From the output of the summing amplifier 23, the amplifier 13 receives a linearly varying and step voltage / 3 / amplified to the required value by the amplifier 13 [4 p. 122]. Mixed color rays reflected from the reflector of the piezoelectric deflector 14 are sent to their micro-lenses 26 / R /, 27 / B /, 28 / G /, which collect them into their photodetectors 29, 30, 31, from which the analog video signals are fed to pre-amplifiers 32, 34 , 33, from which they are fed to the information inputs of the ADC 36, 37, 38, respectively. To synchronize the start of the PEC and ADC 36-38 from the right frame of the stereo pair, keys 5 and 35 are opened with each start of the right frame of the stereo pair with a pulse of 25 Hz from the output of the And element 21 blocks 20 frame scan. Key 35 begins to pass 20 MHz sampling pulses to the ADC control inputs with the start of the period of the stereo frame’s right frame. The key 5 determines the rotation of the mirror 4 in the first fixed position / to the reflecting prism 2 / with the right frame.

выходной ключ 73, на сигнальный вход которого поступают синусоидальные колебания частоты 160 МГц. Выходной ключ 73 в открытом состоянии пропускает одну положительную полусинусоиду на выход. Аналогичный процесе проходит код, поступивший на первые входы блока 75 элементов И, импульсы с которого открывают на время своей длительности /6,25 нс/ второй выходной ключ 78, который в открытом состоянии пропускает одну отрицательную полусинусоиду. Выходы ключей 73, 78 объединены. На выходе блока 41 выходной сигнал представляется полными или неполными синусоидами частоты 160 МГц со стабильностью 10^-7. Нули представляются отсутствием полусинусоид. Эти сигналы и модулируют несущую частоту 2400 МГц в модуляторе 50 передатчика 48. Очередность формирования сигналов ССИ, кодов отсчетов строки и кодов звука определяют сигналы с дешифратора 89. В исходном состоянии ключ 86 закрыт. Счетчик 88 импульсов 10-разрядный, ведет счет 800 импульсов дискретизации строки. При коде 00000001 в дешифраторе 89 с его первого выхода импульс открывает ключ 86, пропускающий сигналы 20 МГц в качестве сигналов U_П в блок 74, 79, и со второго отсчета строки формируются коды видеосигналов по 797 отсчет строки. При 797 импульсе в счетчике 88 код 1100011101, дешифратор 89 при этом коде выдает сигнал со второго выхода, который закрывает ключ 86 и открывает ключ 87. Импульс U_П с ключа 87 запускает блоки 82, 85, на вторые входы блоков 72, 77 элементов ИЛИ поступают соответственно 1-8 и 9-16 импульсы кодов звука. Ключ 87 открыт на время прохода трех кодов звука: 798, 799, 800 отсчетов строки. При поступлении в счетчик 800-го импульса строки с третьего выхода дешифратора 89 импульс закрывает ключ 87 и является вторым выходным сигналом с блока 41, который запускает U_П самоходный распределитель 43 импульсов, который в момент первого отсчета строки подает на третьи входы элементов 72, 77 код ССИ. Этот код является первым кодом в каждой строке. Далее процессы повторяются. В кодах звука единицы в разрядах 1-8 представляются положительными полусинусоидами, в разрядах 9-16 представляются отрицательными полусинусоидами. На первый вход формирователя 42 кодов /фиг.8/ поступают коды с АЦП 38 сигналов В_П/В_Л/ 7 на первые входы блока 90 элементов И, на вторые входы которого поступают 8 импульсов с блока 94. С выходов блока 90 импульсы последовательно через элементы ИЛИ 91, 92 открывают на время своей длительности /6,25 нс/ выходной ключ 93, на сигнальный вход которого поступают синусоидальные колебания 160 МГц. Ключ 93 в открытом состоянии пропускает одну положительную полусинусоиду. Единицы кодов В представляются положительными полусинусоидами. С приходом в дешифратор 106 кода 797-го отсчета строки сигнал со второго выхода дешифратора 106 закрывает ключ 103 и открывает ключ 104. С блоков 97, 102 на вторые входы блоков 95, 98 поступают по 8 импульсов, и с выходов этих блоков на второй элемента ИЛИ 92 и на первый вход элемента ИЛИ 100 поступают три кода сигнала звука. Единицы 1-8 разрядов в кодах звука представляются положительными полусинусоидами, единицы в разрядах 9-16 представляются отрицательными полусинусоидами. С приходом в счетчик 105 800-го импульса строки сигнал с третьего выхода дешифратора 106 закрывает ключ 104. Начинается период следующей строки, в котором с блока 43 первый код строки является кодом ССИ, поступающей на третий вход элемента ИЛИ 92, и код СИС с блока 45, поступающий на второй вход элемента ИЛИ 100. Коды ССИ и СИС являются первыми кодами первой строки только в правом кадре. Далее процессы повторяются. Спектр амплитудно-модулированного сигнала передатчика 48 /фиг.22/ состоит из несущей частоты и двух боковых частот. Сама несущая и одна из боковых частот в информационном смысле являются избыточными, поэтому в каждом амплитудном модуляторе 50, 52 подавляется несущая частота и отфильтровывается одна из боковых /ненужная/ частот. Амплитудный модулятор 50 выдает в выходной усилитель 51 верхнюю боковую частоту 2560 МГц /f_Н+160/, амплитудный модулятор 52 выдает в выходной усилитель 53 нижнюю боковую частоту 2240 МГц /f_Н-160 МГц/. Первый канал передатчика 48 излучает верхнюю боковую частоту с информацией кодов R_П, G_П, /R_П, G_Л / и при стабильности несущей 10^-7 занимает в эфире полосу ±256 Гц или 512 Гц. Второй канал излучает нижнюю боковую частоту с информацией кодов В_П/В_Л, и занимаемая полоса в эфире ±224 Гц или 448 Гц, что составляет всего 0,00002% от несущей частоты.The signal U _{from the} keys 5 and 35 comes from the output of the element And 21 / Fig.1/ at the moment of arrival at its inputs of a pulse of 25 Hz pulse of 25 kHz and line frequency. A frequency synthesizer 40 provides 20 MHz sampling pulses from the first output to the control inputs of the ADC 36-38, to the first control inputs of the shapers 41, 42 codes and to the first control inputs of the ADC 46, 47, from the second output - 160 MHz clock pulses to the second control the inputs of the shapers 41, 42 codes, from the third output - 75 kHz sound sampling pulses to the second control inputs of the ADC 46, 47, from the fourth - 50 Hz pulses to the key 5 input, from the fifth output - 25 kHz line frequency pulses to the third control block inputs 41, 42, to the third control inputs ADCs 46, 47 and to the first input of the frame scan unit 20, from the sixth output - 25 Hz stereo pulses to the second input of block 20 and to the control input / U ₀ / of block 44, from the seventh - 12.5 kHz pulses to the input of the block 17, from the eighth output, sinusoidal oscillations of a 2400 MHz carrier frequency to a transmitter 48 of radio signals. The master oscillator 39 generates sine waves with a stability of 10 ^-7 . The ADCs 46, 47 convert the sound signals into 16-bit codes, which are supplied in parallel from the ADC 46 to the third information input of the code generator 41, from the ADC 47 to the second information input of the block 42. Self-propelled pulse distributor 43 with the arrival of the start signal U _П with the second output of block 41 / at the time of the 800th sampling pulse of the line / gives a code of 8 units 11111111, which is the code of the horizontal sync pulse of the SSI, to the fourth information input of block 41 and to the third information input of block 42. Self-propelled distributor of 45 pulses with arrival on its input signal U _P start from the second output of the counter 44 pulses gives a code of 8 and one, which is the clock pulse of a stereo pair of SIS, to the fourth information input of block 42. The SIS code is the first code of the first line of the right frame / 4 /. The counter 44 pulses is two-bit, with the arrival of the second pulse at the counting input from the second output of block 41, it generates a signal U _P from the second output to block 45, after which it is reset to a signal U ₀ 25 Hz. The second pulse from block 41 means the end of the period of the left frame, i.e. end of a stereo pair. ASC 36-38 are identical (Fig. 5/), have one conversion principle, which consists in scanning the beam from the LED 58 by the reflector of the piezoelectric deflector 55 along the plane of the entrance pupils of the photodetector line 61. The light pulse is converted into an electrical signal that excites the corresponding encoder bus 62, which generates 8 -bit code of the instantaneous value of the input signal, sampling 20 MHz. A pulsed LED, for example, AL402A with a response time of 25 ns, is adopted as a radiation source. Line 61 includes 255 photodetectors for encoding signals with an 8-bit code. Photodetectors are avalanche photodiodes of the APD with a response time of 10 ns. An encoder from K155IV1 microcircuits with a response time of 20 ns. The encoder 62 generates codes from 00000000 to 11111111. The first photodetector corresponds to the code 00000001, the second to the code 00000010, the third to the code 00000011, etc. 255-у - code 11111111. The conversion time in the ADP 30 is not, which satisfies the sampling rate of 20 MHz / 50 ns /. The operation of the shapers 41, 42 codes / 7, 8 /. From the outputs of the ADC 36, 37, the codes are sent in parallel to the first and second information inputs of block 41, from the ADC 38 to the first information input of the generator 42 codes. Shaper 41 codes the first in the line generates the SSI code / Fig. 4/, from the code stream generates from the second to 797 signal codes R _P , G _P , / R _L , G _L / and then three sound codes 796, 799, 800 line samples . Shaper 42 codes the first in the line generates the SSI and SIS codes / in the first line of the right frame /, in the stream of codes forms the second and 797 signal codes V _P and V _L and then three sound codes 798, 799, 800. Units in codes R _P , R _{L are} represented by positive half-sinusoids of the monofrequency of 160 MHz with a stability of 10 ^-7 . Units in the codes G _P , G _{L are} represented by negative half-sine waves of the same monofrequency. Units in codes В _П , В _{Л are} represented by positive half-sine waves of the frequency of 160 MHz, units in the SIS code are represented by negative half-sine waves of the same frequency. Timing diagrams of the operation of blocks 41, 42 in Fig.23. Blocks 41, 42 convert parallel codes into sequential ones and replace the representation of unit symbols from pulses with half-sinusoids of the monofrequency 160 MHz in them. Codes from the ADC 36 are received (Fig. 7/) at the first inputs of the block of elements 70 And, to the second inputs of which are received eight consecutive pulses from the output of block 74, the starting signal U _P which comes from the first key 86. From the outputs of block 70, the pulses are sequentially through OR elements 71, 72 open for a duration of 6.25 ns

output key 73, to the signal input of which sine waves of a frequency of 160 MHz are received. The output switch 73 in the open state passes one positive half-sine wave to the output. A similar process passes the code received at the first inputs of the block of 75 AND elements, the pulses from which open for the duration of their duration / 6.25 ns / second output switch 78, which in the open state passes one negative half-sine wave. The key outputs 73, 78 are combined. At the output of block 41, the output signal appears to be full or incomplete sine waves of a frequency of 160 MHz with a stability of 10 ^-7 . Zeros are represented by the absence of sine waves. These signals modulate the carrier frequency of 2400 MHz in the modulator 50 of the transmitter 48. The sequence of generation of the SSI signals, code samples of the line and sound codes determines the signals from the decoder 89. In the initial state, the key 86 is closed. Counter 88 pulses 10-bit, counts 800 pulses of sampling line. With the code 00000001 in the decoder 89, from its first output, the pulse opens the key 86, which transmits 20 MHz signals as U _P signals to block 74, 79, and from the second sample of the line, video signal codes of 797 line samples are generated. With a 797 pulse in counter 88, code 1100011101, the decoder 89 in this code gives a signal from the second output, which closes key 86 and opens key 87. Pulse U _P from key 87 starts blocks 82, 85, to the second inputs of blocks 72, 77 of OR elements 1-8 and 9-16 pulses of sound codes respectively arrive. Key 87 is open for the passage of three sound codes: 798, 799, 800 line samples. When the line 800 from the third output of the decoder 89 enters the counter of the 800th pulse, the pulse closes the key 87 and is the second output signal from the block 41, which launches the U _П self-propelled pulse distributor 43, which at the moment of the first counting of the line supplies the third inputs of the elements 72, 77 SSI code. This code is the first code on each line. Next, the processes are repeated. In sound codes, units in bits 1–8 appear to be positive half-sine waves, in bits 9–16 appear to be negative half-sine waves. At the first input of the shaper 42 codes (Fig. 8/), codes are received from the ADC 38 signals V _P / V _L / 7 to the first inputs of the block of 90 I elements, to the second inputs of which 8 pulses from block 94 are received. From the outputs of the block 90 pulses are sequentially through OR elements 91, 92 open for the duration of their duration / 6.25 ns / output switch 93, at the signal input of which sine waves of 160 MHz are received. Key 93 in the open state passes one positive half-sine wave. Code B units are represented by positive half-sine waves. With the arrival of the code 797 of the line count to the decoder 106, the signal from the second output of the decoder 106 closes the key 103 and opens the key 104. From blocks 97, 102, 8 pulses are sent to the second inputs of blocks 95, 98, and from the outputs of these blocks to the second element OR 92 and the first input of the OR element 100 receives three codes of the sound signal. Units of 1–8 bits in sound codes are represented by positive half-sine waves, units in bits 9–16 are represented by negative half-sines. With the arrival of the 800th pulse of the line in the counter 105, the signal from the third output of the decoder 106 closes the key 104. The period of the next line begins, in which, with block 43, the first code of the line is the SSI code received at the third input of the OR element 92 and the SIS code from 45, arriving at the second input of the OR element 100. The SIS and SIS codes are the first codes of the first line only in the right frame. Next, the processes are repeated. The spectrum of the amplitude-modulated signal of the transmitter 48 / Fig.22/ consists of a carrier frequency and two side frequencies. The carrier itself and one of the side frequencies in the information sense are redundant, therefore, in each amplitude modulator 50, 52, the carrier frequency is suppressed and one of the side / unnecessary / frequencies is filtered out. The amplitude modulator 50 provides the upper side frequency 2560 MHz / f _H + 160 / to the output amplifier 51, the amplitude modulator 52 outputs the lower side frequency 2240 MHz / f _H -160 MHz / to the output amplifier 53. The first channel of the transmitter 48 emits an upper side frequency with information of the codes R _P , G _P , / R _P , G _L / and with a carrier stability of 10 ^{-7 it} takes on the air a band of ± 256 Hz or 512 Hz. The second channel emits a lower side frequency with information of codes V _P / V _L , and the occupied band on the air is ± 224 Hz or 448 Hz, which is only 0.00002% of the carrier frequency.

At the receiving side, two radio signals are received by blocks 106, 129 (Fig. 9/), which are channel selectors of the corresponding ranges with electronic tuning. Each unit includes an input circuit, a radio frequency amplifier, and a mixer [8 p.132]. The band-pass filter of the radio frequency amplifier is tuned in block 108/129 / bias voltage from block 107 control / channel selection /. The radio frequency signal through the communication loop is fed to the mixer, here from the synthesizer 147 frequencies / output 5 / the frequency equal to the carrier of the transmitter 48 / Fig. 1/, which is necessary for detecting a single-band signal [9 p.146], is supplied. The signal from the mixer, which is the output signal of the block 106/129 /, is input to the amplifier 109/130 / of the radio frequency, where it is amplified to the required value and fed to the input of the bipolar amplitude detector 110/131 /. The second inputs of the frequency synthesizer 147 are connected to the second group of outputs of the control unit 107, when the transmission channel is turned on, the signal from the corresponding output of the block 107 enters the block 147 and determines the output of the required carrier frequency to the third inputs of the blocks 108, 129. The bipolar amplitude detectors 110, 131 are made the circuit in figure 10. Diode D1 selects the positive envelope of the modulating signal / Fig.23/. The diode D2 from the modulating one selects the envelopes of the positive half sine / symbols of units of codes R /, the diode D3 from the modulating one selects the envelopes of the negative half sine / symbols of units of codes G /. Similarly, in block 131 for signal B. From the first output of the bipolar amplitude detector, the detected positive half-sine waves / frequencies of 160 MHz / go to the input of the driver 111/132 / pulses, from the second output, the detected negative half-waves go to the input of the second driver 112/133 / pulses. The pulse shapers are made according to the scheme of an asymmetric trigger with emitter coupling [10 p. 2091], which forms rectangular pulses from harmonically changing signals. The pulses have one polarity and a duration equal to the pulse duration in the codes on the transmitting side. Units in codes are now represented by the presence of an impulse, zeros by their absence. The operating procedure of the receiving side is determined by control signals from the channel for generating control signals. The decisive role belongs to block 146 allocation SSI. With the arrival of three SSI codes, block 146 generates a SSI horizontal sync pulse arriving at the first input of frequency synthesizer 147, and the frequency in block 147 is tuned to the frequency and phase of the master oscillator 39 on the transmitting side. Own frequency stability of the synthesizer 147 frequencies 10 ^-6 . Frequency synthesizer 146 produces: from the first output, 20 MHz sampling pulses to the first control inputs of the registers 113, 121, 134, to the control inputs of the code processing units 114, 122, 135 and to the signal input of the first key 148, from the second output - 160 MHz clock pulses to the second control inputs of the registers 113, 121, 134 and to the third control inputs of the sound reproduction channels, from the third output - pulses of 75 kHz sampling of sound codes to the fourth control inputs of the sound reproduction channels, from the fourth - pulses of 40 MHz double sampling frequency and to the first control inputs of adders 116; 124, 137 and to the third control inputs of the first and second drives of codes 118, 119, from the fifth — sinusoidal oscillations of the carrier frequency into blocks 106, 129, from the sixth output — pulses of 50 Hz frame frequencies through the second switch 151 ₂ to the first control inputs of the first and second drives codes 118, 119 and to the control inputs of blocks 120, 128, 141 control signals. Codes from blocks 111, 112, 132 in sequential form are respectively received at the information inputs of register 113 of signal R, register 121 of signal G and register 134 of signal B, from which 20 MHz pulses are transmitted to their code processing blocks 114, 122, 135, which perform doubling samples in each line from 800 to 1600 receiving intermediate / average / code samples between each passing code and the one following it. Blocks perform the addition of the previous code followed by the division of the sum code in half. Division is performed without time-consuming by discarding the least significant digit / as is done when dividing the decimal number by 10 /. To do this, the corresponding bitwise connection of the outputs of the adder 163 / Fig. 11/ and the outputs of the blocks 161, 162 delays:

, т.е. 40 МГц. Поэтому процесс сложения должен занимать 25 нс. В сумматоре 163 применяются микросхемы К555ИМ6 с временем сложения 25 нс [11 с.258]. После включения питания в регистрах 157-160 нули. Первый импульс 20 МГц, поступающий в триггер 154, обнуляет сумматор 163. Сигнал U_выд1 с первого выхода триггера 154 одновременно выдает: "код 0" с регистра 159 в блок 162 задержек, задерживающий код на 50 нс и через диоды в сумматор 163, из регистра 157 "код 0" в сумматор 163 открывает ключи в блоке 155 на время своей длительности, и регистры 157, 158 заполняются кодом "код 1". В сумматоре 163 идет сложение "код 0+код 0", по окончании которого /25 нс/ первый код суммы с сумматора 163 идет на выход, при котором делится на 2: код №1

Блоки 161, 162 задерживают коды на 50 нс, причем первая половина задержки 25 не приходится на процесс сложения в сумматоре 163. Поэтому через 25 нс вслед за кодом №1 идет с блока 162 код №2 "код 0".Bit 0 means transfer to the high bit when adding codes. Doubling samples in a row reduces the code repetition period by half, amounting to 25 ns

, i.e. 40 MHz. Therefore, the addition process should take 25 ns. The adder 163 uses K555IM6 microcircuits with an addition time of 25 ns [11 p. 258]. After power-up in the registers 157-160 zeros. The first 20 MHz pulse entering the trigger 154 resets the adder 163. The signal U _exp1 from the first output of the trigger 154 simultaneously outputs: “code 0” from register 159 to the delay block 162, which delays the code by 50 ns and through the diodes to the adder 163, from register 157 "code 0" in the adder 163 opens the keys in block 155 for the duration of its duration, and the registers 157, 158 are filled with the code "code 1". In the adder 163 is the addition of "code 0 + code 0", at the end of which / 25 ns / the first code of the sum from the adder 163 goes to the output, which is divided by 2: code No. 1

Blocks 161, 162 delay codes for 50 ns, and the first half of delay 25 does not occur during the addition process in adder 163. Therefore, after 25 ns, after code No. 1, code No. 2 "code 0" goes from block 162.

Через 25 нс за ним следует с блока 161 код №4 "код 1".The second pulse entering trigger 154 zeroes adder 163. The signal U _vy2 from the second trigger output simultaneously outputs: “code 1” from register 158 to delay block 161 and through diodes to adder 163 “code 0” from register 160 to adder 163 opens the keys in block 156, and the registers 159, 160 are filled with the code “code 2”, in the adder is the addition of “code 0 + code 1”, after which the sum code goes to the output, and this is divided into 2: code No. 3

After 25 ns, it follows from block 161 code No. 4 "code 1".

Через 25 нс за кодом №5 следует с блока 162 код №6 "код 2".The third pulse entering trigger 154 resets adder 163. Signal U _{vy3 of the} first output of the trigger simultaneously outputs: “code 2” from register 159 to block 162 and through diodes to adder 163, from register 157 “code 1” to the adder opens the keys to block 155, registers 157, 158 are filled with the following code "code 3". In the adder 163 is the addition of "code 1 + code 2", at the end of which the sum code goes to the output, in which it is divided by 2: code No. 5

After 25 ns, code No. 5 follows from block 162 code No. 6 "code 2".

Через 25 нс за ним с блока 162 следует код №8 "код 3".The fourth pulse entering the trigger 154, zeroes the adder 163, and the signal U _vy4 from the second output of the trigger simultaneously produces: code "code 3" from register 158 to block 161 delays and through diodes to the adder, "code 2" from register 160 to adder opens the keys in block 156, registers 159, 160 are filled with the code "code 4". In the adder 163 is the addition of "code 2 + code 3", after which the sum code goes to the output divided by 2: code number 7

After 25 ns, it follows from block 162 the code number 8 "code 3".

Через 25 нс за ним следует с блока 162 код №10 "код 4". С приходом шестого и следующих импульсов в триггер 154 процессы повторяются. С блока 114 коды в параллельном виде и с частотой 40 МГц поступают в первый блок задержек, во второй блок 117 задержек и на первые входы сумматора 116 /фиг.9/. Также и с блоков 123 и 136. Для удвоения строк в кадре необходимым условием является задержка кодов текущей строки относительно кодов следующей строки на ее длительность 40 мкс. В заявляемой системе направление разверток нечетных строк относительно четных встречное /фиг.2/. Первые блоки 115, 123, 136 задержек выполняют задержку кодов текущей строки на 40 мкс. С приходом импульса 50 Гц и импульса ССИ 25 кГц в элемент И 164 /фиг.12/ выходной сигнал U_от открывает ключ 165, пропускающий импульсы 40 МГц с блока 147 в распределитель 167 импульсов. Тактовые импульсы с распределителя 167 импульсов с первого по 1600 поступают на первые/тактовые/ входы с первого по 1600 разряды восьми регистров 169. На 1-8 информационные входы блока 115 /123, 136/ поступают сигналы кодов с первого по 1600 отсчеты первой строки /нечетной/ с блока 114. Сигналы первого разряда кода поступают на вторые входы разрядов первого регистра 169₁, сигналы второго разряда кода поступают на вторые входы разрядов второго регистра 169₂ и т.д., сигналы восьмого разряда кодов поступают на вторые входы разрядов восьмого регистра 169₈. По окончании периода первой строки 1600 разрядов регистров 169 заполнены сигналами кодов строки. В период второй строки идет последовательная выдача 1600 кодов из регистров 169 в сумматор 116 /124, 137/ при одновременном заполнении освобождающихся регистров сигналами кодов второй строки.The fifth pulse entering trigger 154 resets adder 163. Signal U _{out5 of the} first output of the trigger simultaneously outputs: “code 4” from register 159 to block 162 and through diodes to the adder, from register 157 “code 4” to adder 163 opens the keys to block 155, "code 5" fills the registers 157, 158. In the adder is the addition of "code 3 + code 4", at the end of which the sum code goes to the output, which is divided into two: code No. 9

After 25 ns, it follows from block 162 code No. 10 "code 4". With the arrival of the sixth and subsequent pulses in the trigger 154, the processes are repeated. From block 114, codes in parallel form and with a frequency of 40 MHz are received in the first delay block, in the second delay block 117, and at the first inputs of the adder 116 (Fig. 9/). Also from blocks 123 and 136. To double the lines in the frame, a necessary condition is the delay of the codes of the current line relative to the codes of the next line by its duration 40 μs. In the inventive system, the direction of the sweeps of odd lines relative to even the oncoming one / Fig.2/. The first delay blocks 115, 123, 136 perform a delay of the codes of the current row by 40 μs. With the arrival of a pulse of 50 Hz and 25 kHz pulse in the DIU AND gate 164 /fig.12/ U output _from the key opening 165, which transmits pulses of 40 MHz from the block 147 to the distributor 167 pulses. Clock pulses from the distributor of 167 pulses from the first to 1600 are supplied to the first / clock / inputs from the first to 1600 bits of eight registers 169. Codes 1 to 1600 of the information inputs of the first to 1600 samples of the first line / odd / s block 114. The signals of the first bit of the code are fed to the second inputs of the bits of the first register 169 ₁ , the signals of the second bit of the code are fed to the second inputs of the bits of the second register 169 ₂ , etc., the signals of the eighth bit of the codes are fed to the second inputs of the bits of the eighth register 169 ₈ . At the end of the period of the first line, 1600 bits of the registers 169 are filled with signals of the line codes. In the period of the second line, sequential issuance of 1600 codes from the registers 169 to the adder 116/124, 137 / is performed while filling out the free registers with the signals of the second line codes.

The signals are generated by the leading edge of the clock pulse; the signals of the incoming codes are entered by the same pulse. Due to the fact that the scan of the second line goes counterclockwise to the first line, the codes from the registers 169 are issued in the reverse order, starting with the 1600 bits of the registers 169 _1-8 . The filling of the freed-up bits of the registers with the codes of the second line also begins with the 1600s. It is executed by the second pulse distributor 168, the outputs of which are connected to the first / clock / inputs of the register bits in the reverse order: the first output is connected to the 1600th bits of the registers 169, and the 1600th output is connected to the first bits of the registers 169. When the third line is expanded, the codes are output from the registers is performed by pulses from the distributor 167 pulses, starting from the first bits of the registers 169. Thus, the addition of the same samples of the lines of the current and delayed is performed. Codes of the current line come to the first inputs of the adder 116/124, 137 /, codes from block 115 come to the second inputs of the adder, delayed codes of the same samples of the previous line. Adders 116, 124, 137 are identical, made of K555IM6 microcircuits with a response time of 25 ns. The division of the sum code by 2 is carried out by the corresponding connection of the outputs of the adder to the inputs of its code store so that the least significant bit in the sum code is discarded. The second delay blocks 117, 125, 138 delay the codes by 25 ns for the time the adders operate, so that the codes of the intermediate and current lines of the same name arrive at the inputs of the codes 118, 119 synchronously. Code stores work identically. The signals of the bits of the codes in each drive code are fed to the information 1-8 inputs from the 1st to the 500th blocks of 171 registers / Fig.13/, and in the block of registers 171 / Fig.14, 15 / the signals of the bits of the codes are fed to the third inputs bit registers.

The operation of the code storage, Fig.13.

All code drives work synchronously. From the sixth output of block 147, 50 Hz pulses through the open SIS pulse key 151 ₂ are fed to the first inputs / input of trigger 170 / drives 118, 119, 126, 127, 139, 140 codes. From the first output of the trigger 170, the signal is supplied to the first control input of the block 171 ₁ registers and includes it in the work of accumulating codes of the first line of the frame. Information inputs 500 of blocks 171 are bitwise combined, the registers of block 171 ₁ are filled with 1600 codes of the first line. With the arrival of the 1600th line code, the first output control signal from block 171 _{1 is} supplied to the first control input of the second block 171 ₂ and starts it in the process of accumulating codes of the second line. Upon filling in the registers of block 171 _{2, the} first output control signal from it starts the block 171 _{3 of} registers, etc., the process is repeated until the 500th row of registers is filled with codes in block 171 ₅₀₀ . The first output control signal from block 171 _{500 is} supplied through the diode to the fourth control inputs of all blocks 171 _1-500 and provides 500 line codes synchronously to its block / 120, 128, 141 / of control signals. With the arrival of a second 50 Hz pulse in trigger 170, the signal from its second output is fed to the fifth control input of block 171 ₅₀₀ and turns it on to accumulate codes of the first bottom line (Fig. 2/) of the left side of the stereo pair. The scan of the left frame goes from the bottom up, so the first line of the frame is the bottom line. After filling in the codes of the first line of registers in block 171 _{500, the} second output control signal from block 171 ₅₀₀ goes to the fifth control input of block 171 ₄₉₉ and includes it in the process of filling in the codes of the second line / from the bottom /, etc. After filling in the 500th line with codes in block 171 _1, its second output control signal is supplied through the diode to the fourth control inputs of all blocks 171 _1-500 registers and generates 500 line codes from them in the corresponding block of control signals. Then the signal from the first output of the trigger 170 goes to the first control input of the block 171 ₁ registers and the process is repeated.

The operation of the block 171 registers, Fig.14, 15.

The signal from the first output of the trigger 170 enters the first control input of the first key 172, opens it. The key 172 passes pulses U _d 40 MHz to the input of the distributor 175 pulses, from the outputs of which the pulses U _{t are} sequentially fed to the first inputs of the bits of eight registers 177, to the third inputs of the bits of which the signal codes R _П / R _Л / are received. Upon filling all the bits of the registers 177 _{1-8, the} pulse from the 1600th output of block 175 closes the key 172 and is the first output control signal that opens the key 172 in the next block 171 _{2 of the} registers, and it is filling the bits of the registers with codes of the second line. For a frame period of 20 ms, the registers 177 of all blocks 171 _1-500 are sequentially filled. The output control signal from block 171 ₅₀₀ passes through a diode to the fourth control inputs of all blocks 171 and opens the third keys 174 in them, which pass one pulse U _output 25 kHz, which is supplied in parallel to the second inputs of all bits of the registers 177 and provides all frame codes synchronously into the corresponding block of control signals. Key 174 closes with a transmitted pulse. With the left frame of the stereo pair, the signal from the second output of the trigger 170 goes to the fifth control input of block 171 ₅₀₀ and opens the second key 173, which passes pulses U _d to the input of the second pulse distributor 176, from the outputs of which the clock pulses go to the first inputs of the bits of the registers 177. use the existing connections of the outputs of the bits of blocks 171 to the inputs of the blocks 120, 128, 141 of the control signals; the sequence of connecting the outputs of the second distributor 176 pulses to the first inputs of the bits of the registers 177 changes to brother: the first output of block 176 is connected to the last / 1600th / bits of the registers 177, and the last / 1600th / output of block 176 is connected to the first inputs of the first bits of the registers 177. To prevent unnecessary signals 1600- from passing to the first and second control outputs The th output from block 175 is connected to the inputs of the last bits of the registers 177 through the diode, and 1600 the output from block 176 is connected to the inputs of the first bits of the registers through the diode. Each code drive has 6400000 outputs / 1600 × 8 × 500 /. Drives 118, 119 codes are connected to the block 120 of the control signals, drives 126, 127 are connected to the block 128 of the control signals, drives 139, 140 are connected to the block 141 of the control signals. Each of the control signal blocks includes 1600000/1600 × 500 × 2 / code-to-pulse converters, the outputs of which are connected to the corresponding inputs in the LED screen 142, of all the inputs in the LED screen 4800000/1600000 × 3 /. Due to the large number of connections between the code stores, control signal blocks and the LED screen, the best option for reliable and long-term operation is to execute these blocks on the back of the LED screen in a single, non-separable design.

System operation.

PEC 1 generates three analog signals of the right frame, then three analog signals of the left frame, which are converted by the ADCs 36, 37, 38 into 8-bit codes with a sampling rate of 20 MHz. The first and second code generators 41, 42 convert the parallel codes into sequential ones and replace the unit symbols in the codes from pulses to positive and negative half-sine waves of a frequency of 160 MHz.

In block 41, the sync pulse of the SSI lines is added to the codes in each line; in block 42, the SIS stereo pair code is added to the first line of each right frame. The last three samples in each line are sound codes, the code information is transmitted by the upper and lower side frequencies of one carrier frequency. At the receiving side, two radio signals are received by two paths for receiving and processing codes, detection is performed, clock pulses of the SSI lines and sterepair SIS are allocated. A frequency synthesizer 147 (Fig. 9) reproduces the carrier frequency. The representation of single characters returns to impulses. Color codes R, G, B are distributed on their channels. Blocks 114, 122, 135 double the number of samples in each line / 800 × 2 /, adders 116, 124, 137 double the number of lines / 500 × 2 / in the frame. During the frame period, the code storage units 118, 119, 126, 127, 139, 140 accumulate frame codes of three color signals, which in the next frame period are synchronously issued to control signal blocks 120, 128, 141. Converters "code-number of pulses" of blocks 120, 128, 141 energize the LEDs in the LED screen. Each LED during the frame period emits light pulses, the number of which is proportional to the value of the signal code. Video mode at the receiving side 1600 × 1000 × 50 Hz. The viewer perceives the volumetric image through the ZD glasses 144. Sound accompaniment is performed by two channels 152 of sound reproduction. On the receiving side, there is no need for line and frame scans. The synchronization of the operation of the blocks of code stores from the right frame of the stereo pair is performed by the entered second key 151 ₂ , which is opened by the SIS pulse from block 151 ₁ .

The inventive system manages one carrier frequency and a small band on the air, which determines high noise immunity, the receiving side has low-voltage power, "code-number of pulses" converters increase the brightness and reliability of color reproduction of the reproduced image on the SD screen.

Information sources

1. Patent No. 2296297 C1 class H04N 15/00, bull. 12 from 04/27/07, prototype.

2. B.N. Begugov, N.P. Zakaznov. Theory of optical systems. M., 1973, p. 225, 388.

3. Radio transmitting devices. M.S. Shumilin et al. M., 1981, p. 234, 235.

4. Fridland M.V., Soshnikov V.G. Automatic control systems in video recording devices. M., 1988, p.118 fig.5.5, p.122 fig.5.10.

5. Kolesnichenko O.V., Shishigin I.V. PC hardware. 5th ed., St. Petersburg, 2004, p. 588, 565.

6. "Radio" No. 9, 2004, p. 47.

7. The journal "Instruments and control systems" No. 1, 1990, p.40.

8. Brodsky M.A. TVs color image. Minsk, 1988, p.132 fig. 4.2.

9. Radio communications, broadcasting and television. Ed. A.D. Fortushenko, M., 1981, p. 146.

10. Barkan V.F., Zhdanov V.K. Amplification and impulse technology. M., 1984, p. 209.

11. Digital integrated circuits. Directory. 1991, p. 258.

Claims (1)

Stereo TV system, containing the transmitting side, including photoelectric converter / photomultiplier /, from first to third analog-to-digital converters / ADCU, the inputs of which are connected to the corresponding outputs of the solar cells, the first and second ADC signal sound to the information inputs of which sound signals are given, sine wave generator and frequency synthesizer, first and second code generators, first self-propelled pulse distributor, the input of which is connected to the second output of the first code generator, second self-propelled pulse distributor, pulse counter the output of which is connected to the input of the second self-propelled pulse distributor, the first information input of the first pulse shaper is connected to the output of the first ADC, the output of the first ADC audio signal is connected to the corresponding input of the first code generator, the output of the second ADC of the sound signal is connected to the second information input of the second code generator, the third and fourth information inputs of which are connected respectively to the outputs of the first and second self-propelled pulse distributors, and including a radio transmitter, containing two channels the first of which includes a serially connected carrier frequency amplifier, amplitude modulator the second input of which is connected to the first output of the first code generator, and an output amplifier, the second channel includes an amplitude modulator, the first input of which is connected to the output of the carrier frequency amplifier in the first channel, and an output amplifier, Frequency synthesizer outputs are connected: the first - to the first control inputs of the first and second code generators, the second - to the second control inputs of the code generators, the third is connected to the second control inputs of the first and second ADC sound signal, eighth - to the input of the radio transmitter, the photoelectric converter includes a lens, connected in series to the first amplifier and the first piezoelectric deflector with a reflector at the end, located in the focal plane of the lens, the first source of positive reference voltage the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector, a second source of negative reference voltage, the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector, connected in series to a second amplifier and a second piezoelectric deflector with a reflector at the end, optically connected to the reflector of the first piezoelectric deflector, a third source of positive reference voltage, the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector, a fourth source of negative reference voltage, the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector, line scan unit from the master oscillator, the input of which is the third control input of the photomultiplier and is connected to the seventh output of the frequency synthesizer, and output stage the output of which is connected to the input of the first amplifier, frame scan unit the first and second inputs of which are the first and second control inputs of the solar cells and are connected to the fifth and sixth outputs of the frequency synthesizer, includes a series-connected element And master oscillator and summing amplifier, the output of which is the output of the frame scan unit and is connected to the input of the second amplifier, the second input of the summing amplifier is connected to the first input of the And element, and its control input is connected to the output of the AND element, contains the first and second dichronic mirrors, located one after another and against the reflector of the second piezoelectric deflector, the first, second, third micro lenses first to third photodetectors and first to third pre-amplifiers, the input window of the first photodetector is optically connected through the first micro lens and the first dichroic mirror with a reflector of the second piezoelectric deflector, the input window of the third photodetector is optically connected through the third micro-lens and through the first and second dichroic mirrors with a reflector of the second piezoelectric deflector, the input window of the second photodetector is optically connected through a second micro lens, a second dichroic mirror and through the first dichroic mirror with a reflector of the second piezoelectric deflector, the outputs of the first to third photodetectors are connected respectively to the inputs of the first to third preamplifiers, the outputs of which are the first to third outputs of the solar cells, the first to third ADCs are identical, each includes a series-connected amplifier, whose input is the information input of the ADC, and a piezoelectric deflector with a reflector at the end, source of positive reference voltage the output of which is connected to the second inputs of the amplifier and piezoelectric deflector, a negative reference voltage source, the output of which is connected to the third inputs of the amplifier and piezoelectric deflector, emitter from a pulsed LED, slit diaphragm and micro lens, series-connected line of multi-element photodetector and encoder, the outputs of which are the outputs of the ADC, the control input is the pulse LED input, input windows of the multi-element photodetector line are optically connected through the reflector of the piezoelectric deflector to the radiating side of the emitter, the first code generator contains three channels, the first and second channels are identical, the outputs of the three channels are combined, the first channel includes a series-connected block of elements AND, the first and second elements of III and the output key, and a self-propelled pulse distributor, the second channel includes a series-connected block of elements AND, the third and fourth elements OR and the output key, and a second self-propelled pulse distributor, the second inputs of the blocks of elements AND are connected to the outputs of the self-propelled pulse distributor of their channel, the outputs of the output keys are combined and are the first output of the first code generator, the third channel includes two blocks of AND elements, the inputs of which are the information input of the code generator, fifth and sixth elements OR, the output of the fifth OR element is connected to the second input of the second OR element in the first channel, the output of the sixth OR element is connected to the second input of the fourth OR element in the second channel, and two self-propelled pulse distributors, the outputs of which are connected to the second inputs of the corresponding blocks of AND elements, includes the first and second keys, and series-connected pulse counter and decoder, two outputs of which are connected respectively to the first and second control inputs of the first and second keys, the output of the first key is connected to the inputs of the self-propelled pulse distributors in the first and second channels, the output of the second key is connected to the inputs of the self-propelled pulse distributors in the third channel, control inputs are: combined inputs of keys and counting input of a pulse counter, combined signal inputs of output keys, pulse counter control input, the second code generator includes two channels, whose outputs are combined the first channel contains a series-connected block of elements AND, the first and second elements OR and the output key, and a self-propelled pulse distributor, the outputs of which are connected to the second inputs of the block of elements AND, the first inputs of which are the first information input of the second code generator, the second channel includes a series-connected first block of elements AND, the third element OR and the first self-propelled pulse distributor, the outputs of which are connected to the second inputs of the first block of AND elements, includes a series-connected second block of elements AND, fourth, fifth elements OR and output key, and a second self-propelled pulse distributor, the outputs of which are connected to the second inputs of the second block of AND elements, and includes the first and second keys, pulse counter and decoder, whose outputs are connected: the first - to the first control input of the first key, the second to the second control input of the first key and the first control input of the second key, the first inputs of the elements of the second channel are the second information input of the second code generator, the third information input of which is the third input of the second OR element, and containing the receiving side, including antenna Control block, first and second paths for receiving and processing video signal codes, the inputs of which are connected to the antenna, a video information display device with an IR transmitter on its body, ZD glasses with an IR receiver on the frame, a channel for generating control signals and two sound reproduction channels, the first path for receiving and processing codes of video signals contains a series-connected unit for receiving a radio signal, whose first input is connected to the antenna, the second inputs are connected to the first group of outputs of the control unit, radio frequency amplifier and bipolar amplitude detector, first and second pulse shapers, connected respectively to the first and second outputs of the bipolar amplitude detector, and the signal channel R, containing a series-connected signal register R, the information input of which is connected to the output of the first pulse shaper, code processing unit, first delay block and adder, second delay block the inputs of which and the first inputs of the adder are bitwise combined and connected to the outputs of the code processing unit, the second path for receiving and processing codes of video signals contains a series-connected unit for receiving a radio signal, whose first input is connected to the antenna, the second inputs are connected to the first group of outputs of the control unit, radio frequency amplifier and bipolar amplitude detector, first and second pulse shapers, connected respectively to the first and second outputs of the bipolar amplitude detector, and signal channel B, containing a series-connected register of signal B, the information input of which is connected to the output of the first pulse shaper, code processing unit, first delay block and adder, second delay block the inputs of which and the first inputs of the adder are bitwise combined and connected to the first to eighth outputs of the code processing unit, the receiving side includes a signal channel G, comprising serially connected signal register G, code processing unit, first delay block and adder, the second block of delays the inputs of which and the first inputs of the adder are bitwise combined and connected to the first to eighth outputs of the code processing unit, the channel for generating control signals includes serially connected block selection horizontal sync pulses / SSI /, frequency synthesizer key, pulse counter and decoder, and a block for isolating clock pulses of stereo pairs / SIS /, the first and third inputs of the SSI isolation block are connected to the outputs of the first pulse shapers in the first and second paths for receiving and processing video signal codes, the output of the SSI allocation block is connected to the first input of the frequency synthesizer, to the first control input of the key, to the second control inputs of the first delay blocks in the signal channels R, G In and to the corresponding input of the block allocation of the SIS, the second input of which is connected to the output of the second pulse shaper in the second path of the reception and processing of video signal codes, and the output of the SIS allocation unit is connected to the input of the IR transmitter, the control input of the pulse counter and the second control input of the key are combined and connected to the second output of the decoder, the second inputs of the frequency synthesizer are connected to the second group of outputs of the control unit, Frequency synthesizer outputs are connected: the first is to the signal input of the key and to the first control inputs of the signal registers R, G AT, the second output is to the second control inputs of the signal registers R, G AT, the fifth output is connected to the third control inputs of the radio signal receiving units in the first and second paths of receiving and processing video signal codes, the first and second sound reproduction channels are identical, the first and second information inputs of the first channel are connected to the outputs of the first and second pulse shapers, respectively, in the first path of receiving and processing video signal codes, the first and second information inputs of the second channel are connected to the outputs of the first and second pulse shapers, respectively, in the second path for receiving and processing video signal codes, the corresponding first two control inputs of the first and second sound reproduction channels are connected to the first and second outputs of the decoder in the channel for generating control signals, the second two control inputs of the first and second sound reproduction channels are connected respectively to the second and third outputs of the frequency synthesizer, the first to third code processing units are identical, each includes a trigger, whose input is the control input of the block, first to fourth registers, first and second delay blocks, adder and sixteen diodes, the control input of the adder is connected to the input of the trigger, the information inputs of the first and second registers are bitwise combined, information inputs of the third and fourth registers are bitwise combined, the outputs of the first and second registers are connected via diodes to the first inputs of the adder, the outputs of the fourth register and the third register through the diodes are connected to the second inputs of the adder, the outputs of which are the outputs of the code processing unit, first to third first delay blocks are identical, each includes an AND element, first and second keys, first and second pulse distributors and eight registers, each of which contains the number of bits according to the number of samples in a row, the first and second inputs of the element And are the first and second control inputs of the first block of delays, the third control input of which is the combined signal inputs of the first and second keys, the output of the element And is connected to the first control input of the first key and to the second control input of the second key, the output of the first key is connected to the input of the first pulse distributor, whose outputs are sequential, starting from the first connected to the first inputs of bits from the first to eighth registers, the last output of the first pulse distributor is connected to the inputs of the bits of eight registers through a diode, the second / information / bit inputs of each of the registers are combined and are the first to eighth information inputs of the first delay block, the last output of the first pulse distributor is connected to the second control input of the first key and to the first control input of the second key, the output of which is connected to the input of the second pulse distributor, the outputs of which are connected sequentially from the last to the first bit to the first inputs of the bits of eight registers, the last output of the second pulse distributor through the diode is connected to the first control input of the first key and through the diode to the second control input of the second key, the outputs of the bits of each of the eight registers are combined and are the first to eighth outputs of the first block of delays, the block selection of horizontal sync pulses / SSI / includes the first or third pulse counters, the first and second elements And, the first to third elements are NOT, and diode, information inputs are the counting inputs of the pulse counters, the inputs of the elements are NOT connected respectively to the counting inputs of the pulse counters, the outputs of the elements are NOT combined and connected in parallel to the control inputs of the first to third pulse counters, the outputs of the first and second pulse counters are connected to the first and second inputs of the first element And, whose output and the output of the third pulse counter are connected to the inputs of the second AND element, the output of which is the output of the SSI isolation block and is connected through the diode to the control inputs of the pulse counters, the block allocation of stereo pulses of stereo pairs / SIS / includes the first and second pulse counters, the first and second elements And, the first and second elements are NOT and a diode, the first and second inputs of the block are the counting inputs of the pulse counters, the inputs of the elements are NOT connected respectively to the counting inputs of the pulse counters, the outputs of the elements are NOT combined and connected to the control inputs of the pulse counters, the outputs of which are connected to the inputs of the first AND element, the output of which is connected to the first input of the second AND element, characterized in that on the transmitting side the first and second reflective prisms are introduced into the photoelectric converter, movable flat mirror with mirror coatings on external planes and with a vertical axis of rotation, serially connected first key, the signal input of which is connected to the fourth output of the frequency synthesizer, its control input is connected to the output of the And element in the frame scanning unit of the photomultiplier, trigger and actuator mechanically connected to the axis of rotation of the movable flat mirror, the second reflective prism is located at an appropriate distance to the left of the first reflective prism, their optical axes are parallel and after reflection coincide with the geometric center of a flat mirror, located in the center of the distance between the input optical axes of the reflective prisms and having two fixed positions, the first at 45 ° to the line of sight of the first reflective prism, the second at 45 ° to the line of sight of the second reflective prism, at both positions, the axis of sight from the flat mirror coincides with the optical axis of the photomultiplier lens, the second key is entered, the signal input of which is connected to the first output of the frequency synthesizer, the control input is connected to the output of the AND element in the frame scan unit, the output of the second key is connected to the control inputs of the first to third ADCs of the video signal, the output of the second ADC video signal is connected to the second information input of the first code generator, whose fourth information input is the third control inputs of the second and fourth OR elements, the third output of the decoder of the first code generator is connected to the second control input of the second key and is the second output of the first code generator, to which the counting input of the pulse counter is connected, the control inputs of the first code generator are: the first is the combined key inputs and the counting input of the pulse counter, the second is the signal inputs of the output keys, the third is the control input of the pulse counter, in the second code generator, the fourth information input is the second input of the fifth OR element of the second channel, the third output of the decoder is connected to the second control input of the second key, control inputs are: the first is the combined key inputs and the counting input of the pulse counter, the second is the combined signal inputs of the output keys, the third is the control input of the pulse counter, the outputs of the output keys are combined and are the output of the second code generator, which is connected to the second input of the amplitude modulator in the second channel of the radio signal transmitter, the first control inputs of the first and second ADCs of the sound signal are connected to the first output of the frequency synthesizer, to the fifth output of which the third control inputs of the first and second ADCs of the sound signal are connected, the control input of the pulse counter is connected to the sixth output of the frequency synthesizer, on the receiving side, the information input of the signal register G of the channel of the signal G is connected to the output of the second pulse shaper in the first path for receiving and processing video signal codes, in each channel of the signal R, G Introduced the first and second drive codes, the inputs of the first drive code is connected to the outputs of the adder, the inputs of the second drive code is connected to the outputs of the second block of delays, and a control signal block is introduced, the inputs of which are connected to the outputs of the first and second codes stores, the second and third homonymous control inputs of the first and second codes stores are combined and connected respectively to the output of the horizontal sync pulse allocation unit / SSI / and to the fourth output of the frequency synthesizer, to which the first control inputs of the adders and the third control inputs of the first delay blocks are connected, the second control inputs of which are connected to the output of the SSI allocation block, the first control inputs of the first delay blocks are connected to the sixth output of the frequency synthesizer, the control inputs of the first to third code processing units are combined and connected to the first output of the frequency synthesizer, the second input of the SSI isolation block is connected to the output of the second pulse shaper in the first path for receiving and processing video signal codes, the first input of the SIS extraction unit is connected to the output of the first pulse shaper in the second path for receiving and processing video signal codes, the third input of the block allocation of the SIS is the second input of the second element And the output of which is the output of the unit and is connected through the diode to the control inputs of the pulse counters, the video information display device is represented by a flat-panel LED screen / SD screen /, the corresponding inputs of which are connected to the corresponding outputs of the three blocks of control signals, The SD screen contains screen glass and matrix elements according to the frame resolution number / 1600 × 1000 /, each matrix element includes three LED cells / LED cells /, each of which emits one of the primary colors / R, G AT/, The SD cell includes a white LED and the corresponding color filter / R, G AT/, the input of each LED is connected to the corresponding output of the corresponding block of control signals, the first and second key blocks are entered into each code processing unit, the inputs of which are bitwise combined and are the first to eighth inputs of the block, the outputs of the first block of keys are connected to the bitwise integrated inputs of the first and second registers, the outputs of the second block of keys are connected to the bitwise integrated inputs of the third and fourth registers, the control input of the first block of keys is connected to the first output of the trigger, the control input of the second block of keys is connected to the second output of the trigger, the outputs of the second register are connected to the inputs of the first block of delays, the outputs of the third register are connected to the inputs of the second block of delays, adder outputs the first and second delay blocks are appropriately bitwise combined and are outputs of the code processing unit, a second key is introduced into the channel for generating control signals, the signal input of which is connected to the sixth output of the frequency synthesizer, and the control input is connected to the output of the block allocation of the SIS, the output of the second key is connected in parallel to the first control inputs of the first and second codes stores and to the control inputs of the blocks of control signals, the first and second code drives are identical, each includes a trigger and register blocks according to the number of half lines of a frame

, the information inputs are the bitwise combined from the first to the eighth inputs of the register blocks, the outputs are the outputs of all the register blocks, the control inputs are: the first is the trigger input, the second is the combined second control inputs of the register blocks, the third is the combined third control inputs of the register blocks, the first control the output of each previous block of registers is connected to the first control input of each subsequent block of registers, the first control output of the last / 500 / block of registers through d One is connected to the fourth control inputs of all register blocks, the second control output of each subsequent register block is connected to the fifth control input of each previous register block, the second control output of the first register block through a diode is connected in parallel to the fourth control inputs of all register blocks, the first trigger output is connected to the first control input of the first block of registers, the second output of the trigger is connected to the fifth control input of the last / 500 / block of registers, register blocks id Identical, each includes the first, second, third keys, the first and second pulse distributors and eight registers, the information inputs are the bit-wise combined third inputs of the bits of the eight registers, the outputs are the parallel outputs of the bits of the eight registers, the control inputs are: the first is the first control input of the first key , the second is the signal input of the third key, the third is the combined signal inputs of the first and second keys, the fourth is the first control input of the third key, the fifth is the first control the input of the second key, the output of the first key is connected to the input of the first pulse distributor, the outputs of which are connected in series from the first to the 1600th to the first inputs of the bits in parallel to eight registers, the last output / 1600 / of the first pulse distributor is connected to the second control input of the first key, is the first the control output of the block of registers and through a diode is connected in parallel to the first inputs of the last / 1600s / bits of eight registers, the output of the second key is connected to the input of the second pulse distributor, the output which is connected to the first inputs of the bits of eight registers in sequence from the 1600th bit to the first, the last / 1600 / output is connected to the second control input of the second key, is the second control output of the block of registers and is connected through the diode in parallel to the first inputs of the first bits of eight registers , the output of the third key is connected in parallel to the second inputs of all bits of the eight registers and to the second control input of the third key, the blocks of control signals are identical, each contains a pulse shaper and according to the number of resolutions in the frame / 1600 × 1000 / code-to-pulse converters, which are identical and each includes a decryptor, a key block and an output key, a self-propelled pulse distributor and an LED power supply, the pulse shaper input is the control input of the block, and its output is connected in parallel to the inputs of the self-propelled pulse distributors of the converters, the information inputs of the block are the inputs from the first to eighth of all code-to-number pulses converters, the block outputs are the outputs of the output keys of all converters, the key blocks of which each contain 255 keys, the signal inputs of which are connected in series to the outputs from the first to the 255th self-propelled pulse distributor, the control inputs of these keys are connected to the corresponding outputs of the decoder, and their outputs are combined and connected to the control input / u _from / output key, the signal input of which is connected to the output of the LED power supply, the information inputs of each code-to-number of pulses converter are the first to eighth inputs of the decoder.

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