RU2316142C1 - Stereo television system - Google Patents

Abstract

FIELD: radio communications, possible use for television broadcasting in high definition HDTV format.

SUBSTANCE: system additionally features four keys at transmitting side, and at receiving side features additionally from first to sixth frame code accumulators, from first to sixth impulse generator blocks, light diode flat panel screen with 1920×1080 resolution, infrared transmitter and 3D-goggles with infrared receiver on the frame thereof.

EFFECT: production of HDTV format resolution, increased brightness of image and separate observation of stereo pair frames by viewer.

2 tbl, 23 dwg

Description

The invention relates to radio communications technology and can be used for television broadcasting in high definition HDTV.

Analogs are high-resolution television systems, claiming the HDTV format [1 p.26-28], containing the transmitting and receiving sides. The disadvantages of these systems are: insufficient resolution due to the scanning of lines and frames with the presence of reverse moves that reduce the number of active lines in the frame, the need for broadband channels for signal transmission, HDTV transmission exclusively in compressed form, leading to loss of compression [1 c. 27, 23], there are currently no 1920 × 1080 matrices for video cameras and it is still impossible to obtain a 16: 9 picture [1 p.32], the system is not able to realize the stereo effect at 1920 × 1080 resolution. Actually existing resolution of 1440 × 750 without stereo image. In addition, there are no televisions capable of displaying all 1920 columns of the picture at all [1 p. 33]. The digital stereo-television system [3] was adopted as a prototype. It contains a photoelectric converter on the transmitting side, which generates six analog color signals in a stereo pair of right and left frames, six ADC video signals, a frequency synthesizer, three code shapers, a trigger, two keys and a radio signal transmitter of three channels, on the receiving side containing a control unit, three paths for receiving and processing codes of video signals, a channel for generating control signals, six pulse amplifier units, a modulation unit and radiation, horizontal scanning unit, amplifier and the first piezoelectric deflector with a reflector at the end, a vertical scanning unit, a second amplifier and a second piezoelectric deflector with a reflector at the end, a projection lens, a matte screen, and a unit for separate observation of stereo frames. The frequency of stereo pairs is 25 Hz, the frame rate is 50 Hz. The information of the codes of the right and left frames is transmitted by three radio channels, two carrier frequencies. On the receiving side, three radio signals are received in parallel, amplified, detected, the video signal codes R, G, B are distributed over their channels, in which doubling of samples in rows and doubling of rows in a frame are performed. The modulation unit performs the conversion "code - the brightness of the radiation." The frame scan is performed by two piezoelectric deflectors, the projection lens projects an image with the corresponding magnification on a matte screen. The right and left frames are observed by the viewer separately with their right and left eyes, the alternate overlapping of the field of view of which is performed by the separate observation unit by mechanical rotation of the neutral filters. Disadvantages of the prototype: insufficient resolution in the frame / 1200 × 800 /, insufficient brightness of the image on the screen when the frame is scanned in two lines on the screen without afterglow, mechanically rotating filters in the unit for separate observation of frames pose a danger to the viewer's eyes.

The purpose of the invention is the resolution in the frame, respectively, of the HDTV format, increasing the brightness of the image and the complete security of observing frames of stereo pairs.

The technical result is: obtaining a resolution corresponding to the HDTV format, a significant increase in image brightness and security in obtaining a three-dimensional image perception by the viewer. The result is obtained by obtaining a picture of a frame with a resolution of 1020 × 1080, increasing the brightness of the image using an LED flat panel screen with the number of LED cells by the number of resolution pixels in the frame / 2073600 /, emitting the entire frame duration / 20 ms /, using 3D glasses for separate observation of frames made by the technology of LCD cells [4 p. 588-565]. On the transmitting side, a video mode of 960 × 540 × 50 Hz / 960 — the number of encoded samples in a line, 540 — the number of encoded lines in a frame, and 50 Hz — the frequency of right and left frames in total / is formed. The frequency of stereo pairs is 25 Hz. The stereopair includes the right and left frames following one after another. Stereopair information is transmitted by three radio channels / side frequencies of two carrier frequencies, as in the prototype /. On the transmitting side, 540 lines are encoded per frame with 960 samples each. Codes are 8-bit. The scanning of lines on the transmitting side is progressive without reverse moves both in rows and frames. The clock frequency on the transmitting side is:

where: 50 Hz - frame rate / 25 Hz + 25 Hz /,

540 - the number of lines in the frame,

960 is the number of encoded samples per line,

2 - coding of samples by a bipolar signal: positive and negative half-signals,

8 - the number of bits in the code.

Code Sampling Rate:

Line Frequency:

f _c = 540 × 50 Hz = 27 kHz.

Line Duration:

frame duration:

Piezo deflector oscillation frequency with horizontal scan on the transmitting side

parallel code period

the period of the sequence of bits in the serial code:

Video mode at the receiving side 1920 × 1080 × 50 Hz. The number of samples in a line is 1920, the lines in a frame are 1080, the frame rate is 50 Hz, the frequency of stereo pairs is 25 Hz. The receiving side provides the viewer with a perception of a volumetric image with a resolution of 2073600 pixels on the LED screen / LED screen / with the size of the SD cell 0.6 × 0.6 mm:

horizontal 1920 × 0.6 mm = 1152 mm,

vertical 1080 × 0.6 mm = 648 mm, diagonal 1321 mm,

or 52 inches and an aspect ratio of 16: 9.

The viewer receives volumetric perception through 3D glasses [4 p.558-565], in which, simultaneously with the frame change, the field of view is sequentially blocked from that of the eye, the frame of which is missing on the SD screen. The essence of the invention is that in a stereo television system comprising a transmitting side including a photoelectric converter, three ADCs of a video signal, three code shapers, a trigger and two keys, a pulse counter, two self-propelled pulse distributors, a frequency synthesizer and a radio signal transmitter, and a receiving side including a control unit, three paths for receiving and processing video signal codes, a channel for generating control signals and a video information display device, from the third to the third are entered on the transmitting side stand, the keys are entered on the receiving side from the first to the sixth, the first and sixth drives are entered on the receiving side of the frame codes, the first to sixth pulse shaper units, the video information display device is represented by a flat-panel LED screen / LED screen / with an IR transmitter the case of the screen and introduced 3D glasses with an IR receiver on their frame.

The transmitting side in Fig. 1, the raster of the frame in Fig. 2, the shape of the control voltages in Fig. 3, the structure of the digital streams in Fig. 4, the ADC of the video signal in Fig. 5, the construction of the piezoelectric deflector in Fig. 6, the ADC of the sound signal in Fig. 7, signal shapers R and G in FIG. 8, signal shaper B in FIG. 9, receiving side in FIG. 10, bipolar amplitude detector in FIG. 11, summing amplifier in FIG. 12, frame code storage in FIG. 13, the register block in FIGS. 14 and 15, the code processing block in FIG. 16, the first delay block in FIG. 17, the LED cell in FIG. 18, the light matrix diodes and their location on the color filters 19, the horizontal sync block allocation DIU 20, the sync block allocation stereopairs ASIC 21, the frequency spectra of the signals of the transmitter 22, the system operation time chart in Figure 23.

The transmitting side includes / Fig. 1 / a photoelectric converter 1, which is a sensor of video signals of two images of the same space, generates three video signals of the right frame R _p , G _p , V _p and three video signals of the left frame R _l , G _l , V _l and contains the first / right / lens 2, the first amplifier 3 and the first piezoelectric deflector 4 connected in series with a reflector at the end located on the rear focal plane of the lens 2, the first source 5 of positive reference voltage, the second source 6 of negative reference voltage, therefore, the connected second amplifier 7 and the second piezoelectric deflector 8, the front end of which has two faces located at an appropriate angle to each other and with a reflector on each face, the third source 9 of the positive reference voltage, the fourth source 10 of the negative reference voltage, the second lens 11 is left, the third amplifier 12 and the third piezoelectric deflector 13 connected in series with a reflector at the end located in the rear focal plane of the second lens 11, the fifth source 14 of the positive reference the sixth source of the negative reference voltage 15, the horizontal scanning unit 16 from the driving generator 17 and the output stage 18, the vertical scanning unit 19, including the And 20 element connected in series, the driving generator 21 and the summing amplifier 22, the first 23 and the second 24 dichroic mirrors, located one after the other and against the first reflector of the piezoelectric deflector 8, first 25, second 27, third 26 micro lenses, first 28, second 30, third 29 photodetectors, first 31, second 33, third 32 pre-amplifiers, third 34 and fourth 35 ihroichnye mirrors arranged one after the other and against the second reflector pezodeflektora 8, fourth 36, fifth 38, sixth 37 microobjectives, fourth 39, fifth 41, sixth photodetectors 40, fourth 42, fifth 44 and sixth 43 preamplifiers. The second lens 11 is located to the left of the lens 2, the optical axis of the lens 11 is parallel to the optical axis of the lens 2, the distance between the axes of the lenses corresponds to the optimal stereoscopic effect for human vision. The transmitting side includes a trigger 45, the first 46, the third 47, the fifth 48 keys, the second 49, the fourth 50, the sixth 51 keys, the first ADC 52 / video signals R _p and R _l /, the second ADC 53 / video signals G _p and G _l /, the third ADC 54 / video signals B _p and B _l /, the first shaper 55 codes, the second shaper 56 codes, the third shaper 57 codes, the first 58 and second 59 self-propelled pulse distributors, a counter 60 pulses, the oscillator 61 of the sinusoidal oscillations and the synthesizer 62 frequencies, the first 63 and second 64 ADCs of the sound signal, to the inputs of which sound signals Zv1, Zv2 and 65 signal transmitter of three channels. The first channel includes a series-connected first carrier frequency amplifier 66, an amplitude modulator 67 and an output amplifier 68, the second channel includes an amplitude modulator 72 and an output amplifier 73, the third channel includes a second carrier frequency amplifier 69, an amplitude modulator 70 and an output amplifier 71. Each of the amplitude modulators 67, 72, 70, includes a series-connected ring modulator and a band-pass filter [5 p.234], filtering out the unnecessary side frequency in the spectrum of the amplitude-modulated carrier, the ring module heator suppresses the carrier frequency. ADCs 52, 53, 54 are identical (Fig. 5/), each contains an amplifier 74 and a piezoelectric deflector 75 with a reflector at the end, a positive reference voltage source 76, a negative reference voltage source 77, an emitter from a pulsed LED 78, a slit diaphragm 79, and a micro lens 80, line 81 of multi-element photodetector and encoder 82. All piezoelectric deflectors 4, 8, 13, 75, 94 are end bimorph piezoelectric elements with a light reflector at the end, are structurally executed / Fig.6/ equally [6 p.118] from the first 83 and second 84 piezo-plates internal electro and 85, the first 86 and second 87 external electrodes. One end of the piezoelectric plates is fixed in the holder 88, a light reflector 89 is located on the free end. The free end of the piezoelectric deflector 8 is made of two faces at an appropriate angle to each other, each face has its own reflector, they separate the rays of the right and left lenses in separate directions. ADCs 63 and 64 are identical (Fig. 7/), each includes a serially connected voltage divider 90, a key block 91, a matching amplifier 92, an amplifier 93 and a piezo-deflector 94 with a reflector at the end, a source of positive reference voltage 95, source 96 of negative reference voltage, emitter from a pulsed LED 97, a slit aperture 98 and a micro lens 99, a multi-element photodetector line 100, a first decoder 101, an encoder 102 and a second decoder 103, a pulse counter 104 connected in series, a third decoder 105 and a block 106 p Trunk. The first 55 and second 56 code generators are executed the same way / Fig.8/, each includes a trigger 107 and a block 108 switching and three channels. The first and second channels are identical. The first includes a series-connected block of 109 AND elements, the first 110, the second 111 OR elements and an output switch 112, and a self-propelling pulse distributor 113, the second channel includes a second block 114 of AND elements, a third 115, a fourth 116 OR elements and an output key 117, and a self-propelled pulse distributor 118, the third channel includes two blocks of 119 and 122 AND elements, the fifth 120 and sixth 123 OR elements and two self-propelled pulse distributors 121, 124, includes the first 125 and second 126 keys, a pulse counter 127 and a decoder 128. In the first shaper 55 decryption codes torus 128 has first and second outputs connected to corresponding key inputs 125, 126. In the second code generator 56, the decoder 128 also has a third output, which is the second output of block 56, connected to the input of the first self-propelled pulse distributor 58 and to the counting input of the pulse counter 60 . The first and second information inputs of blocks 55, 56 are the inputs of the switching unit 108 and the inputs of the blocks 119, 122 of AND elements, the third and fourth information inputs are the third inputs of the second and fourth elements OR 111, 116. The control inputs are: the first is the trigger input 107 / 12.96 MHz /, the second - the combined inputs of the counter 127 and the keys 125, 126 / 6.48 MHz /, the third - the signal inputs of the output keys 112, 117 / 103.68 MHz /, the fourth - the control input of the counter 127 pulses / 27 kHz /. The output in block 55 is the combined outputs of the output keys 112, 117. In block 56 there are two outputs: the first is the output of the output keys 112, 117, the second is the third output of the decoder 128. The third code generator 57 contains / Fig. 9/ trigger 107, block 108 switching and two identical channels. The first includes an AND element block 109, a first 110, a second 111 OR element, and an output switch 112, and a self-propelled pulse distributor 113. The second channel includes an AND element block 114, a third 115, a fourth 116 OR element, and an output switch 117, and a self-propelled pulse distributor 118. The first information input is the inputs of the switching unit 108, the second and third information inputs are the second inputs of the blocks 111 and 116 of the OR elements. The first control input is the trigger input 107 / 12.96 MHz /, the second is the combined inputs of the blocks 113, 118 / 6.48 MHz /, the third is the signal inputs of the output keys 112.117 / 103.68 MHz /.

The receiving side includes / FIG. 10 / antenna, control unit / channel selection 129, first, second and third paths for receiving and processing video signal codes, a channel for generating control signals, a video information display device / LED screen / and two sound reproduction channels. The first path for the reception and processing of codes of video signals receives and processes the codes of signals R _p and R _l and includes serially connected radio signal receiving unit 130, a radio frequency amplifier 131 and a bipolar amplitude detector 132, first 133 and second 134 pulse shapers, and a signal channel R including the first 135 and second 136 signal registers R, block 137 code processing, the first block 138 delays, the adder 139 and the second block 140 delays. The second path for the reception and processing of codes of video signals receives and processes the codes of signals In _p and V _l and includes serially connected unit 141 for receiving a radio signal, an amplifier 142 of a radio frequency and a bipolar amplitude detector 143, a first 144 and a second 145 pulse shapers, and a signal channel B including the first 146 and second 147 signal registers B, a code processing unit 148, a first delay unit 149, an adder 150 and a second delay unit 151. The third path for the reception and processing of codes of video signals receives and processes the codes of signals G _p and G _l and includes serially connected radio signal receiving unit 152, a radio frequency amplifier 153 and a bipolar amplitude detector 154, first 155 and second 156 pulse shapers, and a signal channel G including first 157, second 158 G signal registers, code processing unit 159, first delay block 160, adder 161 and second delay block 162. The receiving side includes first to sixth 163-168 frame code drives, first to sixth 169-174 pulse shaper blocks, 175 LED flat panel screen / LED screen /, IR transmitter 176 on the LED screen housing, 3D glasses 177 s IR receiver 178 on the frame of 3D glasses. The operating side of the receiving side provides a channel for generating control signals, including a block 179 for extracting horizontal sync pulses / SSI /, a frequency synthesizer 180, serially connected key 181, a pulse counter 182 and a decoder 183, and a block 184 for separating sync pulses of stereo pairs / SIS /. Also, the receiving side includes identical first 185 and second 186 sound reproduction channels. The image from the screen 175 by the viewer is perceived as voluminous through 3D glasses 177. When playing the right and left frames on the screen, the glasses of 3D glasses alternately lose transparency, each eye sees only its own frame, which gives a stereo effect. Glasses of glasses are made by the technology of LCD cells of the translucent type, used as electronically controlled filters / shutters /. With the arrival of the clock pulse of the SIS 25 Hz stereopair to the IR transmitter 176, it studies the IR pulse received by the IR receiver 178 (Fig. 10/), which generates a control signal in the LCD cell of the left glass, dimming it for 20 ms, then gives a second control signal into the LCD cell of the right glass, dimming it for 20 ms. Each eye sees its frame. Accumulators of codes 163-168 of the frame are identical / Fig.13/, each includes blocks of 187 registers by the number of half lines in the frame: 187 _1-540 . The information input of the code store is the bitwise integrated 1-8 inputs of blocks 187 ₁ -187 ₅₄₀ registers. The information inputs of the code storage devices are connected: 163 and 164, respectively, to the outputs of the blocks 139 and 140, 165 and 166 to the outputs of the blocks 161 and 162, 167 and 168 to the outputs of the blocks 150 and 151. The control inputs of the frame code storage devices are: first - the first control input the first block 187 ₁ registers, the second - the combined second control inputs / 54 kHz / blocks 187 registers, the third - the combined third control inputs / U _d 25.92 MHz / blocks 187 _1-540 registers. Each control output of the previous block 187 registers is the first control input of the subsequent block 187 registers. The control output of the last block 187 ₅₄₀ registers connected in parallel to the fourth control inputs of all blocks 187 registers. Blocks 187 registers are identical / Fig.14 and 15 /, each includes the first 188 and second 189 keys, the distributor 190 pulses and eight registers 191 _1-8 . The information input of the register block is the bitwise combined third inputs of the bits of the eight registers 191. The outputs of the block 187 are the parallel outputs of all the bits of the eight registers 191, a total of 15 360 outputs / 1920 × 8 /. The outputs 540 of the blocks 187 registers are the outputs of each drive code codes, which 8294400 outputs / 1920 × 8 × 540 /. The control inputs are: the first is the first control input of the first key 188, the second is the signal input / U _output 54 kHz / second key 189, the third is the signal input of the first key 188 / U _d 25.92 MHz /, the fourth is the first control input of the key 189 connected to the control output of the last block 187 ₅₄₀ registers. The last / 1920 / output of the pulse distributor 190 is connected to the second control input of the first key 188 and is the control output of the block 187 registers connected to the first control input of the next block 187 ₂ registers. The output of the first key 188 is connected to the input of the pulse distributor 190, the outputs of which are connected in series from the first to the 1920th to the first control inputs of the bits in parallel with eight registers 191 _1-8 . The output of the second key 189 is connected in parallel to the second control inputs of the bits of the eight registers 191 and to the second control input of the key 189, closing the key 189 after passing one pulse U _vyd . The outputs of the drives 163-168 frame codes are connected to the inputs of the pulse shaper units 169-174, respectively, the purpose of which is to give control signals to power the LEDs in the LED cells of the screen 175. Each block of the pulse shapers includes pulse shapers by the number of lines / 540 /, the number of codes in line / 1920 / and bits in the code / 8 /, i.e. by the number of outputs from the block / 169-174 / pulse shapers: 8294400. An exception to the horizontal and vertical scanning imaging process obliges each LED to be provided with its own electronic control circuit; therefore, the total number of pulse shapers in blocks 169-174 corresponds to the number used in the LED screen LEDs: 8294400 × 6 = 49766400.

Modern technologies make it possible to manufacture microcircuits with tens of millions of transistors in a microcircuit [7 p.65, 8 p.26], therefore, each of the blocks 169-174 can be executed in one microcircuit. The amplitude of the control signal from each pulse shaper corresponds to the operating voltage of the LED, the duration of the control signal corresponds to the duration of / 20 ms / frame for LEDs to emit the entire period of the frame. The LED flat panel screen 175 represents a collection of LED cells by the number of pixels in the frame 2073600/1920 × 1080 /. Each LED cell forms one pixel of the image and consists of (Fig. 18) of an opaque body 225 in the form of a rectangular parallelepiped, a matrix of 226 LEDs of three primary colors / R, G, B / and a corresponding shape of a microlens 227 that collects the radiation flux from the matrix LEDs and forming from the bottom of the pixel the desired size and shape. The red LEDs of the radiation in the matrix are 8 / by the number of bits in the code /, green is 8, the blue is also 8, there are 24 LEDs in total, which are located in the focal plane of the microlens 227. The micro-miniature LEDs are located in the matrix in five rows of five columns / FIG. 19 /. The response of the LEDs to the control signal is tens of nanoseconds [9 p. 9], practically the response time is zero. The diameter of the emitting part of the LED is 0.1 mm, the shape of the matrix is square from the side l 0.5 mm, an area of 0.25 mm ² . The end sides of the housing of the SD cell are squares with a side of 0.6 mm. The depth of the cell body corresponds to the focal length of the microlenses / several millimeters /. The color streams emitted by the matrix LEDs are modulated in terms of brightness by the “code - radiation brightness” transformation. Modulation is performed by applying a damping neutral filter on each LED, the density of which corresponds to the weight of the bits in the code to which the LED belongs. The frequency of attenuation of the LED radiation is carried out according to the binary code coefficients of the code to which the LEDs belong. The LED of the first / senior / digit of the code does not have a light filter, i.e. its filter is 0 ^x , the LED of the second digit of the code has a filter of density 2 ^x , the LED of the third digit of the code has a filter of 4 ^x , etc., the LED of the eighth / least / digit of the code has a filter of density 128 ^x . A variant of the arrangement of the LEDs in three colors and their filters in Fig.19. The distribution of the binary code coefficients of the code, the corresponding density of neutral filters and the weight of the discharge in the code in table 1.

Table 1 Code digits 1 senior rank 2 3 four 5 6 7 8 young. Binary Odds one 0.5 0.25 0.125 0.0625 0,031 0.0156 0.0078 Neutral filters 0 ^x 2 ^x 4 ^x 8 ^x 16 ^x 32 ^x 64 ^x 128 ^x The weight of the discharge in the code, in% fifty 25 12.5 6.25 3,1 1,57 0.78 0.39

The radiation of 24 matrix LEDs is summed up by a microlens 227, at the output of which the brightness, saturation and color tone of the resulting radiation is determined by the mutual ratio of the three color components, respectively, of the signal codes R, G, B. In the LED screen 175, the number of cells 2073600 uses LEDs of the same color 16588800/2073600 × 8 /, and in three colors / R, G, B / 49766400. With the case size of the SD cell 0.6 mm × 0.6 mm, the screen dimensions are: horizontal 1929 × 0.6 mm = 1152 mm,

vertical 1080 × 0.6 mm = 648 mm,

diagonally 1321 or 52 inches.

The summing amplifier 22 / FIG. 12/ includes a 10-bit pulse counter 228, a decoder 229, a first 230 and a second 231 keys, a first 232 and a second 233 pulse shapers and an output amplifier 234. The first information input is the first input of the output amplifier 234, the second the counting input of the counter 228 pulses, the control input is the combined control inputs of the keys 230, 231 and the control input of the block 228. The output is the output of the output amplifier 234. The processing units 137, 148, 159 are identical (Fig. 16/, each includes a trigger 192, the first block 193 elemen Com. delays, from the first to the fourth 194-197 registers, the second block of elements 198 delays, the fifth register 199, the sixth register 200, the adder 201 and 16 diodes. Block 193 delays the codes by 77 ns to restore the even codes to the odd ones. Block 198 delays the codes by 14.5 ns. Registers 199, 200 operate storing codes 77 ns and outputting their signals U _vyd with latch 192. The first input information are combined bitwise input registers 194, 195, the second - the inputs of the first unit delay elements 193. The output is the bitwise combined outputs of the registers 199, 200 and block 198, the control input is the input of the trigger 192. The first delay blocks 138, 149, 160 are identical (Fig. 17/), each includes the And 202 element, the first 203, the second 204 keys, the first 205 , the second 206 pulse distributors and eight registers 207 _1-8 , each of which contains 1920 bits. Blocks 138, 149, 160 delay the codes of each line by a line duration of 37 μs.

Block 179 allocation of horizontal sync pulses SSI includes / FIG. 20/ first 208, second 209, third 210 pulse counters, first 211, second 212 AND elements, first 213, second 214, third 215 elements NOT and a diode. 1-3 information inputs are the counting water of the counters 208, 209, 210 pulses, the output is the output of the second element And 212. With the arrival of 1-3 codes at the same time, three codes from the same units 11111111 at the output of block 179, an SSI pulse appears, their frequency is 27 kHz . Block 184 allocation of clock pulses of stereopairs SIS includes / Fig.21/ from first to third 216-218 pulse counters, from first to third 219-221 elements NOT and a diode. With the arrival at the counting inputs of the counters of three codes from units 11111111 and at the fourth input of the SSI pulse from block 179, an SIS pulse appears at the output of block 184, their frequency is 25 Hz.

The photoelectric converter 1 generates six analog video signals of two images from the right 2 and left 11 lenses, which from the pre-amplifiers 31, 32, 33 are fed to the inputs of the keys 46, 48, 47 and from the pre-amplifiers 42, 43, 44 to the inputs of the keys 49, 51 , 50. From the outputs of the keys 46 and 49, the analog video signals are fed to the input of the first ADC 52, from the keys 47 and 50 to the input of the second ADC 53, from the keys 48 and 51 to the input of the third ADC 54. The alternate output of the stereo pair codes with the ADC is performed by trigger 45 and keys 46-48, 49-51. Pulses of 50 Hz from the tenth output of block 62 enter the trigger 45. The signal from the first output of the trigger opens the keys 46, 47, 48, which pass the analog video signals of the right frame during the 20 ms period of the first frame to the ADC 52-54 inputs. With the arrival of the second 50 Hz pulse to trigger 45, the signal from the second output closes the keys 46-48 and opens the keys 49, 50, 51, which pass the analog video signals of the left frame during the second period of 20 ms frame in the 52-54 ADC. The clock inputs of the ADC from the first output of block 62 receive clock pulses of 12.96 MHz sampling of video signals. The 52-54 ADCs convert analog video signals to 8-bit codes. Shapers 55, 56, 57 codes convert the parallel codes from the ADC to serial ones and replace the representation of units in the codes from pulses with positive and negative half-sinusoids of the single frequency 103.68 MHz from the 4th output of the synthesizer 62 frequencies. The master oscillator 61 generates sinusoidal oscillations with a stability of 10 ^-7 . A frequency synthesizer 62 generates and issues: from the first output, sampling pulses of 12.96 MHz to the ADC 52-54 clock inputs and to the first control inputs of the shapers 55, 56, 57 codes, from the second output 6.48 MHz sampling pulses of the line to the second shaper inputs 55-57 codes to the first control inputs of the ADC 63, 64, from the third - pulses of 81 kHz sound sampling to the second ADCs 63, 64, from the fourth - sinusoidal oscillations of 103.68 MHz to the third control inputs of the shapers 55-57 codes, from the fifth output - pulses of 27 kHz line frequency on the 4th control inputs fo of drivers 55, 56 codes, to the first input of block 19 and to the third control inputs of drivers 55-57 codes, from the fifth output - pulses of 27 kHz line frequencies to the 4th control inputs of drivers 55, 56 codes, to the first input of block 19 and the third control inputs of the ADC 63, 64, from the sixth - pulses of 25 Hz stereo frequency to the second input of block 19 and to the control input of the counter 60 pulses U _o , from the seventh - 13.5 kHz pulses to the input of block 16 horizontal scanning, from the eighth - sinusoidal oscillations of the first carrier frequency 1244.16 MHz / 103.68 MHz × 12 / for amplifier 66, from the ninth - si osoidal oscillations of the second carrier frequency 933.12 MHz for the amplifier 69 / 103.68 MHz × 9 /, from the tenth output - 50 Hz pulses of the frame frequency to the input of the trigger 45. The ADC 63, 64 convert the sound signals into 16-bit codes that are received to the second information inputs of blocks 55, 56. A self-propelled distributor of 58 pulses with the arrival of a signal U _p from the second output of block 56 / at the time of 479 line sampling pulses / gives a code of eight units 11111111, which is the code of the horizontal sync pulse SSI / 959 counting in each line / to the third information inputs of the shaper she has 55, 56 codes and the second information input of the shaper 57 codes. A self-propelled distributor of 59 pulses with a signal U _p coming to its input from the second output of block 60 generates a code of eight units 11111111, which is a clock pulse of the SIS stereo pair / 960th count in the last line of the left frame of the stereo pair, Fig. 4 /, to the fourth information inputs of the blocks 55, 56 and to the third information input of block 57. The counter 60 is two-bit, gives a signal U _p for the block 59 from the second bit with the arrival of a second pulse at its input from the second output of block 56, after which it is reset to a signal of 25 Hz / stereo pair frequency /. The second pulse from block 56 means the end of the period of the second / left / frame of the stereo pair. The SIS code represents the end of the stereo pair, followed by the first frame of the stereo pair, i.e. right frame of the next stereo pair. The spectrum of the amplitude-modulated signal of the transmitter 65 / Fig.22/ consists of a carrier frequency and two side frequencies. One of the side frequencies and the carrier itself in the information sense are redundant. Therefore, in each amplitude modulator 67, 72, 70, the carrier frequency is suppressed and one of the side / unnecessary / frequencies is filtered out. The amplitude modulator 67 provides the upper side frequency 1347.84 MHz / f ₁ + 103.68 MHz / from the first carrier to the output amplifier 68. The amplitude modulator 72 outputs to the input of the output amplifier 73 the lower side frequency of 1140.48 MHz / f ₁ -103.68 MHz / from the first carrier. The amplitude modulator 70 outputs to the output amplifier 71 an upper side frequency of 1036.8 MHz / f ₂ +103.68 MHz / from the second carrier. The first channel of the transmitter 65 emits an upper side frequency of 1347.84 MHz with information of codes R _p and R _l , and with carrier stability of 10 ^{-7 the} occupied band on the air is ± 135 Hz or 270 Hz, the second channel emits a lower side frequency of 1140.48 MHz with the information of codes V _p and V _l , the occupied band on the air ± 114 Hz or 228 Hz, the third channel emits an upper side frequency of 1036.8 MHz with the information on codes G _p and G _l , the occupied band on the air ± 104 Hz or 208 Hz. The total occupied bandwidth of 706 Hz on three channels, which is less than 0.01% compared to the frequency bands occupied by existing television systems. Lens 2 creates the right image in the focal plane in which the reflector of the piezoelectric deflector 4 is located. Its reflector has a width of 0.02 mm, a length of 10.8 mm / 540 × 0.02 /. The dimensions of the deploying element are 0.02 × 0.02 mm. According to the control voltages (Fig. 3/) from the amplifier 3, the piezoelectric deflector 4 vibrates the end face with the reflector relative to the first reflector of the piezoelectric deflector 8, scanning a row of the right image. The lens 11 creates a left image in the focal plane where the reflector of the piezoelectric deflector 13 is located. Its reflector has the same dimensions as the reflector of the piezoelectric deflector 4, and vibrates the end face relative to the second reflector of the piezoelectric deflector 8, scanning a row of the left image. Block 16 line scan produces a linearly varying voltage in the form of an isosceles triangle. The control voltage period is equal to the duration of two lines. For a raster of 540 lines at 50 Hz frames, piezo-deflectors 4 and 13 oscillate at a frequency of 13.5 kHz. During the period of one oscillation, two lines are scanned, the line frequency is 27 kHz.

Line scanning is progressive and without reverse moves. The piezoelectric deflector 8 performs a frame scan synchronously of two frames: when scanning down / Fig. 2/, there are odd / right / frames, when scanning up, even / left / frames go. The piezoelectric deflector 8 oscillates at a frequency of 25 Hz, which is 50 frames per second. Frame scan is also without reverse moves. The width of the piezoelectric reflector 8 reflectors of 0.02 mm, the length of each 19.2 mm / 960 × 0.02 /. From the output of the summing amplifier 22, the amplifier 7 receives a linearly varying and step voltage (Fig. 3/), amplified to the required value by the amplifier 7 [6 p. 122]. Summing amplifier 22/12 / performs the summation of the line voltage from the master oscillator 21 with pulses of 27 kHz line frequency. Each line impulse moves the line at the end of its move by one line step, 540 lines are obtained: all active. The purpose of the blocks 228-233 to submit to the second input of the output amplifier 234 at the right time, negative / when scanning down / and positive / when scanning up / pulses of the corresponding amplitude and duration. The signal U _o from the And element 20 resets the counter 228, which is 11-bit and counts the horizontal pulses 27 kHz, the counting cycle is 1080 pulses / 540 × 2 /. The signal U _o opens the key 230 and closes the key 231. The key 230 passes 540 line pulses to the input of the first pulse shaper 232, which generates negative pulses arriving at the second input of the output amplifier 234. The right frame is being scanned. With the arrival of the 540th pulse, the counter generates a code number 540, in which the decoder 229 generates a signal that closes the key 230 and opens the key 231, which transmits line pulses to the second pulse generator 233, which generates positive pulses to the second input of the amplifier 234, followed by a scan of the left frame of the stereo pair .

Counter 228 counts 1080 pulses. Then follows a pulse of 25 Hz U _o , the counter is reset, the process is repeated. Mixed color rays reflected from the first reflector of the piezoelectric deflector 8 are directed: red is reflected from the first dichroic mirror 23, collected by the lens 25 into the photodetector 28, blue is transmitted by the mirror 23, reflected from the second mirror 24, the lens 26 is collected into the photodetector 29, the green color passes through both mirrors 23, 24 and lens 27 are assembled into a photodetector 30. From the photodetectors, analog video signals are fed to preamplifiers 31, 32, 33. Rays from the second piezoelectric deflector go through a similar process 8 projector of analog video signals to preamplifiers 42, 43, 44. preamplifiers right frame signals via the public keys 46, 48, 47 enter the ADCs 52-54. In the next frame period (left), the signals from the preamplifiers 42, 43, 44 through the public keys 49, 50, 51 enter the ADC 52-54. The ADCs 52-54 have one conversion principle, which consists in scanning the beam (Fig. 5/) from the LED 78 with a piezoelectric deflector 75 reflector along the plane of the entrance pupils of the photodetector line 81 of the multi-element photodetector. The light pulse is converted into an electrical signal, exciting the corresponding bus of the encoder 82, which gives the code of the instantaneous value of the input signal. Discretization of the conversion of 12.96 MHz. The radiation source is a pulsed LED AL402A with a response time of 25 ns. Photodetectors in line 81 are avalanche photodiodes of the APD with a response time of 10 ns. Line 81 includes 255 photodetectors for encoding signals with 8-bit codes. An encoder from K155IV1 microcircuits with a response time of 20 ns. The encoder generates codes from 00000001 to 11111111. The first photodetector in line 81 corresponds to the code 00000001, the second to 00000010, the third to code 00000011, etc., the 255th to 11111111, the conversion time is 30 ns / 10 ns + 20 ns / with a margin satisfies the frequency of 12.96 MHz / 77 ns /. The ADCs 63, 64 convert sound signals into 16-bit codes. During one line, the ADC generates three codes, a sampling rate of 81 kHz. To obtain codes with 16 digits, the transfer coefficient of the voltage divider 90 / Fig. 7/ is changed. Block 91 of the keys has seven keys for connecting the corresponding stage of the divider 90 to the matching amplifier 92. The line 100 of the multi-element photodetector includes 1024 photodetectors and converts the sound signals into 10-bit codes. Resolution adopted 10 μV. The encoding range of one ruler is 0-0.01024 V. The conversion of signals exceeding 2 ¹⁰ into the code is performed by a decoder 101, an encoder 102, a second decoder 103, a divider 90, and a key block 91. With their application, the coding range of sound signals is 0-0.65536 V, i.e. 2 ¹⁶ . The transmission coefficient in the range from 0 to 2 ¹⁰ is 1.0. With a code above 2 ^{10, the} coefficient becomes 0.5, with a code above 2 ¹¹ - 0.25, with a code from 2 ¹² - 0.125, with a code from 2 ¹³ - 0.0625, with a code from 2 ¹⁴ - 0.03125, with code from 2 ¹⁵ - 0,015625, which remains to 2 ¹⁶ . With a decrease in the signal amplitude, the process is the reverse of increasing transmission coefficient. Over the course of one line, the encoder 102 provides three codes arriving at block 106 containing three 16-bit registers. In the process of receipt, the codes are shifted from register to register by signals U _sd shift. In block 106, three codes are accumulated, which at times 477, 478, 479 of the sampling pulses in the line / Fig. 4/ are issued in the first 55 and second 56 blocks. The output signals come from the decoder 105. The output signals form a pulse counter 104 and a decoder 105. The 9-bit counter keeps a pulse count of 6.48 MHz, the count cycle is 480 line pulses. The counter 104 is reset to zero by a line frequency pulse U _o 27 kHz at the moment of a 480 line sampling pulse. The first shaper 55 codes gives from the 1st to 952 signal codes R _p / R _l /, three sound codes, the SSI code and the SIS code in the last line of the left frame. Units in codes of odd samples of a line are represented by positive half-sinusoids of a single frequency of 103.68 MHz with a stability of oscillations of 10 ^-7 , units in codes of even samples of a line are represented by negative half-sines of the same frequency. The second shaper 56 codes gives from the 1st to 952 signal codes G _p / G _l /, three sound codes, SSI code and SIS code. The third generator 57 codes gives from the 1st to 952 signal codes In _p / V _l /, the SSI code and the SIS code.

The operation of the formers 56, 55 / Fig. 8/.

Codes with ADCs 52, 53 arrive in parallel with a frequency of 12.96 MHz at the inputs of a switching unit 108 that branches a stream of codes 12.96 MHz into two at 6.48 MHz: the first stream is the codes of odd samples of the line, the second is the codes of even samples lines / Fig. 4/. Block 108 of four K176KT1 microcircuits, which are 4-channel switches with a response time of 25 ns [10 p. 222]. The connection of the channels to the outputs of block 108 in turn is performed by a trigger 107, 12.96 MHz pulses are received at its input. At the second inputs of the AND elements of blocks 109, 114, 8 pulses are sequentially received from the self-propelled distributor 113, 118 pulses having 8 bits each. Starting U _p pulses for them are 6.48 MHz pulses. From the outputs of the AND elements of blocks 109, 114, the code pulses sequentially through the OR elements 110, 111 and 115, 116 open the output keys 112, 117 for a duration of 10 ns. The sinusoids of the mono frequency 103.68 MHz arrive at the signal inputs of the output keys. The output key 112 in the open state passes one positive sine wave, the second output key 117 in the open state passes one negative sine wave. At the output of the code generator, the units in the codes of odd samples are represented by positive half-sine waves, in the codes of even samples by a line, they are represented by negative half-sines. Zeros appear to be the absence of both. The output signals from blocks 55, 56 appear to be full or incomplete sinusoids of a frequency of 103.68 MHz with a stability of 10 ^-7 . These signals modulate carrier frequencies. Timing diagrams of the operation of blocks 55, 56 in Fig.23. Each sound code consists of two parcels of 8 bits. The first package / the first half of the code / 1-8 bits goes to the first inputs of the AND elements of block 119 and through the OR elements 120, 111 goes to the input of the output key 112, the second package 9-16 bits goes to the first inputs of the AND elements of block 122 and through the elements OR 123, 116 is fed to the input of the output key 117. The keys 125, 126 are designed to separate the codes of the video signals from the sound codes. The key 125 is opened by the signal from the first output of the decoder 128 at the moment of the 480 line sampling pulse / Fig. 4/ and the line sampling pulse remains open from the 1st to 476. At the moment 476 of the pulse from the second output of the decoder 128, the signal closes the key 125 and opens the key 126. At the moments 477, 478, 479 pulses of the line, three sound codes arrive at the inputs of the output keys 112, 117. At the moment of the 480 pulse / 959 counting / to the third element OR 111, the SSI code comes from block 58, triggered by a signal U _p / 479 pulse-s / s from the third output of the decoder 128. At the last 540th line of each left frame of the stereo pair, block 59 gives out a line pulse / 960th sample / SIS code to the third input of the OR element 116. The signal U _p for block 59 generates a counter 60 pulses. The process of operation of the generator 57 codes is similar to the operation of block 55 and simpler, it does not participate in the formation of sound codes.

Three radio signals are received at the receiving side by blocks 130, 141, 152 (Fig. 10/), which are channel selectors of the corresponding ranges with electronic tuning. Each unit includes an input circuit, a radio frequency amplifier, and a VT2 / mixer / transistor [11 p.132]. The band-pass filter of the radio frequency amplifier in each range is tuned by the bias voltage from the control unit 129. The radio frequency signal through a communication loop is fed to the emitter of the VT2 mixer, here, with a frequency synthesizer of 180 frequencies / outputs 5, 6 /, two frequencies equal to the first and second carrier frequencies of the transmitter, necessary for the detection of a single-band signal [12 p.146], are supplied. The signal from the VT2 collector, which is the output signal of the block 130/141, 152 /, is input to the amplifier of the radio frequency amplifier 131/142, 153 /, where it is amplified and fed to the input of the bipolar amplitude detector 132/143, 154 /. The second inputs of block 180 are connected to the second group of outputs of block 129. When the transmission channel is turned on, the signal from the corresponding output of block 129 enters block 180 and determines the output of two frequencies from it to the third inputs of blocks 130, 141, 152. Bipolar amplitude detectors 132, 143, 154 are made according to the scheme in Fig.11. Diode D1 emits a positive envelope of the modulating signal. The diode D2 from the modulating one selects the envelopes of the positive half sine / unit symbols in the codes of odd samples /, the diode D3 from the modulating one selects the envelopes of the negative half sine / unit symbols in codes of even samples /. From the first output of the bipolar amplitude detector, the detected positive half-sine waves with a frequency of 103.68 MHz are fed to the input of the first shaper 133 pulses / 144, 145 /, from the second output, the detected negative half-sine waves are fed to the input of the second shaper 134 pulses / 145, 156 /.

The pulse shapers are made according to the scheme of an asymmetric trigger with emitter coupling [13 p.209], which forms rectangular pulses from harmonically changing signals. The pulses have the same polarity and duration equal to the pulse duration in the codes on the transmitting side. Units in codes are represented by the presence of an impulse, zeros by their absence. After turning on the power of the receiving side, all keys are in the closed state. The operating procedure is determined by control signals from the channel for generating control signals. The decisive role belongs to block 179 allocation of sync pulses. The condition for the appearance of the SIS from block 179 is the simultaneous arrival at the counting inputs of the block 179 of pulses of codes of eight units 11111111. In all codes except the SSS, one or more zeros will always be present, especially in three codes at the same time. For each zero in the code, the elements of the NOT block 179 / Fig. 20/ reset the block counters. With the arrival of three codes 11111111, block 179 will output an SSI pulse at the output, their frequency is 27 kHz. The SSI pulse from block 179 enters block 180, 184, 138, 149, 160. The SSI pulse adjusts the frequency in the frequency synthesizer 180 to the frequency and phase of the master oscillator on the transmitting side, the natural frequency stability of the synthesizer 180 frequencies 10 ^-6 . Block 180 outputs the output pulses from the first 6.48 MHz sampling line, from the second - 103.68 MHz clock, the third - the pulses 81 kHz sampling frequency sound _vyd U, fourth - 12.96 MHz sampling pulses of video signals codes from the fifth and sixth — sinusoidal oscillations of two corresponding carrier frequencies to the third inputs of blocks 130, 141, 152, from the seventh — pulses of 25.92 MHz of the double sampling frequency of the codes, from the eighth — pulses of the frame frequency of 50 Hz, from the ninth — pulses of 54 kHz of double horizontal frequency . Codes R _{p of} odd samples of the line from the output of the pulse shaper 133 and codes R _{p of} even samples of the line from the shaper 134 of the pulses are transmitted in sequential form to the registers 135, 136, filling in the bits of which take a parallel form. Codes G _p and B _p go through similar processes, filling in the registers 146, 147 and 157, 158. The codes are sent from the registers to blocks 137, 148, 159 and they are executed by 6.48 MHz pulses from the first output of block 180, they also reset the registers. The processing units 137, 148, 159 of the codes are identical and double the samples in each row from 960 to 1920 to obtain the middle / intermediate / samples between each passing code and the next one. Blocks add up the previous and next codes and divide the sum code into two. The operation of the block in Fig.16. The code of the first sample of the line from register 135 is fed in parallel to the inputs of the registers 194, 195, the code of the second sample of the line is sent to the inputs of the first block 193 of delay elements, which delays the even code by 77 ns, restoring the second sample after the first. From block 193, the code is sent in parallel to the inputs of the registers 196, 197. Each code is used twice: the first time as the next, the second time as the previous one. Therefore, four registers are applied. After turning on the power in the bits of the registers zeros. With the arrival of the first 12.96 MHz pulse to the input of flip-flop 192 from its first output, the signal U _vyd1 simultaneously outputs from register 195 “code 0” / from one zeros / to the first inputs of adder 201, from register 196 “code 0” to sixth register 200 for storing in it the code "code 0" 77 ns and through diodes to the second inputs of the adder 201. The output signals and reset the registers. And in the registers 194, 195 at the same time the first code “code 1” arrives. The adder performs the addition of "code 0 + code 0". The adder from K555IM6 microcircuits [14 p. 258] with an addition time of 24 ns. With the arrival of the second pulse in the trigger 192, it receives a signal U _vt into the adder 201, gives out the sum code from it and resets the adder bits. When the sum code is transferred to the second block of delay elements 198, the code is divided into two. The division is performed without time expenditure by shifting the sum code so that the least significant bit of the sum code / is discarded, as when dividing the decimal number by ten /. The shift is performed by connecting the outputs of the adder 201 to the inputs of the second block 198 of delay elements:

Bit 0 means transfer to the high bit when the sum of codes. Doubling the number of samples per line from 960 to 1920 reduces the code period by half and amounts to 38.5 ns / Fig. 16/. The addition process takes 24 ns, so block 198 must still delay the code by 14.5 ns / 38.5-24 /. After the code arrives at adder 201, the code follows 38.5 ns to exit block 198, which is required. The first code from block 198 is code number 1

.

.

With the arrival of the second pulse in the trigger 192 from its second output, the signal U _vyd2 simultaneously outputs from the register 200 code No. 2 “code 0” to the output, from register 197 “code 0” to the adder and from register 194 “code 1” to register 199 and through diodes to the addition adder. At the same time, registers 196, 197 are filled with the code "code 2". Registers 199, 200 store 77 ns codes, but the first half of the storage time / 38.5 ns / falls on the addition time in the adder and the delay time by block 198, so the codes from blocks 199 and 200 will follow the code from block 198 through 38 , 5 ns. Issued by the signal U _vyd2 from register 197 “code 0” and register 194 “code 1” are summed in the adder 201, the sum code is divided into two, code No. 3 follows from the output of block 198

.

.

With the arrival of the third pulse to the input of trigger 192, the signal U _vyd3 from its first output simultaneously outputs from register 199 code No. 4 “code 1”, from register 195 “code 1” to adder 201, from register 196 “code 2” to register 200 and through the diodes into the adder, the registers 194, 195 are filled with the following code “code 3”, the adder 201 adds “code 1 + code 2”, then division by two, and code No. 5

goes to the exit. With the arrival of the 4th pulse in trigger 192 from its second output, the signal U _vy4 simultaneously generates code 6 “code 2” from register 200, from code 197 “register 2” to the adder, from code 194 “code 3” to register 199, and through diodes to the adder 201. Registers 196, 197 are filled in with the following code “code 4”, addition in the adder “code 2 + code 3”, division by two, and code No. 7

goes to the exit. With the arrival of the fifth pulse to the input of trigger 192, the signal from its first output U _vyd5 simultaneously outputs code 8 “code 3” from register 199, issues code 3 from register 195 to the adder, code 196 from register 196, and 200 to register through diodes to the adder. Registers 194, 195 are filled with the new code "code 5". There is an addition “code 3 + code 4”, division by two, and code No. 9

goes to the exit. With the arrival of the 6th pulse in the trigger and subsequent processes are repeated. The outputs of blocks 199, 198, 200 are bitwise combined and are the outputs of block 137. From the outputs of blocks 137, 148, 159, line codes with a doubled frequency of 25.92 MHz already arrive at the inputs 138, 149, 160 of the delays, respectively, at the first inputs of the adders 139, 150, 161 and second delay blocks 140, 151, 162. Then there is the process of doubling the lines in the frame, for which it is necessary to delay the codes of the current line relative to the codes of the next line for the line duration / 37 μm /. The delay is performed by the first block 138/149, 160 / delays / FIG. 17/. When scanning a frame on the transmitting side, the direction of the development of odd lines relative to even lines is opposite. With the arrival of a pulse of 50 Hz to the first input of the And element 202 and the second pulse input of the line of 27 kHz / SSI / from the output of the And element, the signal opens the key 203, which transmits 25.92 MHz pulses to the 205 pulse distributor. Clock pulses from block 205 sequentially from the first to 1920 outputs arrive at the first / clock / inputs of the bits of eight registers 207 _1-8 . At 1-8, the information inputs of block 138 receive code signals. The signals of the first bits of the codes are fed to the second inputs of the bits of the first register 207 ₁ , the signals of the second bits of codes are fed to the second inputs of the bits of the second register 207 ₂ , etc., the signals of the eighth bits of the codes are fed to the second inputs of the bits of the eighth register 207 ₈ . Starting from the period of the second line, the 1920 codes are sequentially issued from the registers 207 to the adder 139 and at the same time the released bits of the registers are filled with the signals of the codes of the next line. The issuance of codes is performed by the leading edge of the clock pulses; the input of the signal signals is entered by the same clock pulse. Since the scan of the second line goes counter to the first, the issuance of codes from registers 207 is in the reverse order, i.e. starts from the 1920th rank. This is accomplished by a second pulse distributor 206, the outputs of which are connected to the first inputs of the bits of the registers 207 in the reverse order from the 1920s to the first. When scanning the third line, the codes are output again in pulses from the distributor 205, starting from the first bits of the registers 207. The adder 139/150, 161 / performs the addition of codes of the same samples of the current and delayed lines. Codes of the current line from block 137 come to the first inputs of the adder, codes from block 139, delayed by 37 μs, come to the second inputs.

Adders 139, 150, 161 are identical, made of K555IM6 microcircuits with an addition time of 24 ns. The division of the sum code into two is performed by the corresponding connection of the outputs of the adder 139 to the inputs of its drive 163/167, 165 / frame codes / as well as in blocks 137 /. The second delay blocks 140, 151, 162 delay the codes by 24 ns for the duration of the addition by the adders, so that the codes of the current and intermediate lines arrive at the frame code stores synchronously. Codes 540 of the current lines of signal R from block 140 go to the drive 164 frame codes, codes 540 of intermediate / doubled / lines of signal R from block 139 go to the drive 163 codes, codes 540 of the current lines of signal G from block 162 go to the drive 166 frame codes, Codes 540 of the intermediate lines of signal G are received from adder 161 to drive 165 of codes, similarly for signal B.

The work of blocks 187 registers / Fig.14, 15 /.

The signals of the bits of the codes are fed to the third inputs of the bits of the registers 191 _1-8 . Filling the registers with line codes begins with the opening of a pulse of 50 Hz of the first key 188, which passes pulses U _d 25.92 MHz to the input of the distributor 190 pulses. The clock pulses from the outputs of block 190 are sequentially fed in parallel to the first control inputs of the bits of eight registers 191. The signals of the first bits of codes go to the bits of the first register 191 ₁ , second bits of codes to the bits of the second register 191 ₂ , etc. By filling the registers 191, the signal from the last / 1920th / output of block 190 closes the first key 188 and, as a control output signal, opens the key 188 in the second block 187 of ₂ registers, the registers of which are similarly filled with codes of the second line. Thus, consecutively for 20 ms, the registers 191 of all blocks 187 of _1-540 registers are _filled . By filling the registers 191 in all blocks 187, the control signal from block 187 ₅₄₀ opens the second keys 189 in all 540 blocks 187 of the registers. The keys 189 pass one U _output / 54 kHz / pulse, which simultaneously outputs all frame codes from all blocks 187 of the frame code storage to the pulse shaper blocks 169-174 and resets the bits of the registers 191 to receive the codes of the next frame. Each drive code frame 163-168 has 8294400 outputs, which are connected to the same inputs respectively of the blocks 169-174 pulse shapers, each of which includes 8294400 pulse shapers. The outputs of the six blocks 169-174 49766400 are connected to the same inputs of the LED screen 175/1920 × 1080 × 24 /.

The operation of the stereo system.

The photoelectric converter 1 generates analog video signals of the right and left frames of the stereo pair, which are converted by the 52-54 ADC into 8-bit codes with a sampling rate of 12.96 MHz. Shapers 55, 56, 57 codes form consecutive codes from parallel codes, replacing the representation of units in the codes from pulses in them with positive and negative half-sinusoids of the single frequency 103.68 MHz. On the transmitting side, 540 lines are encoded with 960 samples each. Line scan line by line without reverse moves. Frame rate 50 Hz, stereo pair frequency 25 Hz. A stereo pair of right and left frames. The information of codes R, G, B is transmitted by three channels of the transmitter 65. The receiving side receives three radio signals by three paths of receiving and processing codes of video signals, amplifies, detects, extracts horizontal sync pulses of SSI and sync pulses of stereo pairs of SIS, and a frequency synthesizer 180 reproduces two carrier frequencies. Representation of units in codes returns to impulses. The signal codes R, G, B are distributed over their channels, in which doubling of samples in each row and doubling of rows in the frame / 190 × 1080 / are performed. The reproduced mode on the screen corresponds to the HDTV / 1920 × 1080 / format, while the viewer perceives the image through 3D glasses. The control signals for the infrared transmitter 176 (Fig. 10/) are the pulses of the SIS stereopairs from block 184. The technical characteristics of the inventive system are in table 2. The first 185 and second 186 channels reproduce stereo sound. The clock from block 179 opens the key 181, which transmits 6.48 MHz pulses to the counter 182 pulses. With the arrival of pulse 476, the decoder 183 generates a signal from the first output, opening corresponding channels in channels 185, 186, passing three sound codes each, which are converted into analog signals and reproduced by loudspeakers. Upon receipt of a line pulse in the counter 182 479, the decoder 183 by the signal from the second output closes the keys in the channels 185, 186 and resets the counter 182. Each of the sound reproduction channels contains corresponding blocks that convert the sound codes into analog signals, power amplifiers, and loudspeakers. The execution of the receiving side is proposed to be performed in two parts: in the first part, include paths for receiving and processing codes with R, G, B signal channels, a channel for generating control signals and sound channels, in the second part, include six frame code stores, six pulse shaper blocks and LEDs -screen, and the second part is performed in a single monolithic and non-separable design.

table 2 Specifications Values Transmission side Transmission of signal codes R _p , R _l 1347.84 MHz upper side. f ₁ B _p , B _l 1140.48 MHz lower side. f ₁ G _p , G _l 1036.8 MHz upper side. f ₂ Occupied bands on the air 270 Hz, 228 Hz, 208 Hz Clock frequency 103.68 MHz The number of encoded lines / samples per line 540/960 Video Sampling 12.96 MHz Frame rate / stereo pair frequency 50 Hz / 25 Hz Line frequency 27 kHz Line Length / Frame Duration 37 μs / 20 ms Video coding 255 levels., 8 bits. Transmit Side Video Mode 960 × 540 × 50 Hz Receiving side Playable format HDTV 1920 × 1080 × 50 Number of lines / samples per line 1080/1920 Line Rate / Frame Rate -/50 Hz Frame duration 20 ms Video Sampling 25.92 MHz Frame Resolution / CD Cells per Frame 2073600/2073600 Number of LEDs in one color 16588800 pieces LEDs in three colors R, G, B 49766400 pieces Diagonal screen size / inches 1321/52 " Frame format 16: 9 Stereo pair image playback LED screen and 3D glasses

Used sources.

1. “Home computer” No. 12, 2005, p.26-28, 23, 32, 33.

2. “Home computer” No. 4, 2006, p.23-34.

3. Patent No. 2246801, cl. H04N 15, bull. No. 5 of 02.20.05, prototype.

4. Kolesnikov OV, Shishigin I.V. Hardware R. S. 5th ed., St. Petersburg, 2004, p. 588-565.

5. Radio transmitting devices. M.S. Shumilin et al., M., 1981, p. 234, 235.

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Claims (1)

Stereo TV system,  containing the transmitting side,  including photoelectric converter,  the first,  second,  third analog-to-digital converters (ADC),  the first and second ADCs of the sound signal,  to the information inputs of which sound signals are given,  serially connected sine oscillation generator and frequency synthesizer,  the first,  second and third code generators,  first and second self-propelled pulse distributors,  pulse counter  trigger,  first and second keys,  and a radio transmitter,  containing three channels  the first channel includes a series-connected amplifier of the first carrier frequency,  the input of which is connected to the eighth output of the frequency synthesizer,  amplitude modulator and output amplifier,  the second channel includes a series-connected amplitude modulator,  the first input of which is connected to the output of the amplifier of the first carrier frequency,  and an output amplifier,  the third channel includes a series-connected amplifier of the second carrier frequency,  the inputs of which are connected to the ninth output of the frequency synthesizer,  amplitude modulator and output amplifier,  the first trigger output is connected to the first control input of the first key and to the second control input of the second key,  the second trigger output is connected to the second control input of the first key and the first control input of the second key,  the first and second information inputs of the first code generator are connected to the outputs of the first ADC and the first ADC of the sound signal,  the first and second information inputs of the second code generator are connected to the outputs of the second ADC and the second ADC of the sound signal,  the first information input of the third code generator is connected to the output of the third ADC,  third information inputs of the first,  the second shaper codes and the second information input of the third shaper codes are connected to the output of the first self-propelled pulse distributor,  the fourth information inputs of the first and second code shapers and the third information input of the third code shaper are connected to the output of the second self-propelled pulse distributor,  the control input of which is connected to the output of the second discharge of the pulse counter,  the counting input of which and the control input of the first self-propelled pulse distributor are combined and connected to the second output of the second code generator,  the first output of which is connected to the second input of the amplitude modulator of the third channel of the radio signal transmitter,  the output of the first code generator is connected to the second input of the amplitude modulator in the first channel of the radio signal transmitter,  the output of the third code generator is connected to the second input of the amplitude modulator in the second channel of the radio signal transmitter,  the first output of the frequency synthesizer is connected to the first control inputs of the first,  second and third code generators,  the second output of the frequency synthesizer is connected to the second control inputs from the first to third code generators and to the first control inputs of the first and second ADCs of the sound signal,  the third output of the frequency synthesizer is connected to the second control inputs of the first and second ADCs of the sound signal,  the fourth output of the frequency synthesizer is connected to the third control inputs from the first to third code generators,  the fifth output of the frequency synthesizer is connected to the fourth control inputs of the first and second code generators,  to the third control inputs of the first and second ADCs of the sound signal and to the first control input of the frame scan unit,  the second control input of which is connected to the sixth output of the frequency synthesizer,  the control input of the pulse counter is also connected to it,  the seventh output of the frequency synthesizer is connected to the input of the horizontal scanning unit of the photoelectric converter,  which contains the first lens,  connected in series to the first amplifier and the first piezoelectric deflector with a reflector at the end,  located in the focal plane of the first lens,  the first source of positive reference voltage  the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector,  a second source of negative reference voltage,  the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector,  connected in series to a second amplifier and a second piezoelectric deflector,  the free end of which consists of two faces at an appropriate angle to each other,  each face has its own reflector,  the first reflector of the second piezoelectric deflector is optically connected to the reflector of the first piezoelectric deflector,  a third source of positive reference voltage,  the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector,  a fourth source of negative reference voltage,  the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector,  contains a second lens,  located to the left of the first lens at an appropriate distance and whose optical axis is parallel to the optical axis of the first lens,  connected in series to a third amplifier,  the first input of which is connected to the first input of the first amplifier,  and a third piezoelectric deflector with a reflector at the end,  located in the focal plane of the second lens and optically connected to the second reflector of the second piezoelectric deflector,  fifth source of positive reference voltage  the output of which is connected to the second inputs of the third amplifier and the third piezoelectric deflector,  sixth source of negative reference voltage,  the output of which is connected to the inputs of the third amplifier and the third piezoelectric deflector,  contains the first and second dichroic mirrors,  located one after another and against the first reflector of the second piezoelectric deflector,  the first,  second and third micro lenses,  the first,  second and third photodetectors,  the first,  second and third preamplifiers,  the input window of the first photodetector is optically connected through the first micro lens and the first dichroic mirror with the first reflector of the second piezoelectric deflector,  the input window of the second photodetector is optically connected through the second micro lens and through both dichroic mirrors to the first reflector of the second piezoelectric deflector,  the input window of the third photodetector through the third micro lens,  the second dichroic mirror and through the first dichroic mirror is optically connected to the first reflector of the second piezoelectric deflector,  the outputs from the first to third photodetectors are connected respectively to the inputs of the first,  second and third preamplifiers,  whose outputs are the first,  second and third outputs of the photovoltaic converter,  which contains the third and fourth dichroic mirrors,  located one after another and against the second reflector of the second piezoelectric deflector,  fourth,  fifth,  sixth micro lens,  fourth,  fifth,  sixth photodetectors,  fourth,  fifth,  sixth preamplifiers,  the input window of the fourth photodetector is optically connected through the fourth micro-lens and the third dichroic mirror to the second reflector of the second piezoelectric deflector,  the input window of the fifth photodetector is optically connected through the fifth micro-lens and through both dichroic mirrors to the second reflector of the second piezoelectric deflector,  the input window of the sixth photodetector is optically connected through the sixth micro lens,  a fourth dichroic mirror and through a third dichroic mirror with a second reflector of the second piezoelectric deflector,  the outputs from the fourth to the sixth photodetectors are connected respectively to the inputs of the fourth,  fifth and sixth preamplifiers,  whose outputs are fourth,  fifth  sixth outputs of the photoelectric converter,  the frame scanning unit of the photoelectric Converter contains a series-connected element And,  master oscillator and summing amplifier,  the second input of which is connected to the first input of the AND element,  the control input of the summing amplifier is connected to the output of the element And,  the output of the summing amplifier is the output of the frame scan unit and is connected to the first input of the second amplifier,  the first and second inputs of the element And are the inputs of the frame scan unit,  the summing amplifier includes a series-connected pulse counter and a decoder,  first and second keys,  first and second pulse shapers and an output amplifier,  the signal inputs of the keys and the counting input of the pulse counter are combined and are the second input of the summing amplifier,  the first input of which is the first input of the output amplifier,  first control input of the first key,  the second control input of the second key and the control input of the pulse counter are combined and are the control input of the summing amplifier,  the second control input of the first key and the first control input of the second key are combined and connected to the output of the decoder,  the output of the first key is connected to the input of the first pulse shaper,  the output of the second thorn is connected to the input of the second pulse shaper,  the outputs of the pulse shapers are combined and connected to the second input of the output amplifier,  the output of which is the output of the summing amplifier,  the first,  second,  the third ADCs are identical,  each contains a series-connected amplifier and a piezoelectric deflector with a reflector at the end,  source of positive reference voltage  the output of which is connected to the second inputs of the amplifier and piezoelectric deflector,  negative reference voltage source  the output of which is connected to the third inputs of the amplifier and piezoelectric deflector,  emitter from a pulsed LED,  slit diaphragm and micro lens,  series-connected line of multi-element photodetector and encoder,  the outputs of which are the outputs of the ADC,  the control input is the pulse LED input,  the first and second ADCs of the sound signal are identical,  each contains a series-connected voltage divider,  key block  matching amplifier  amplifier and piezoelectric deflector with a reflector at the end,  source of positive reference voltage  the output of which is connected to the second inputs of the amplifier and piezoelectric deflector,  negative reference voltage source  the output of which is connected to the third inputs of the amplifier and piezoelectric deflector,  emitter from a pulsed LED,  slit diaphragm and micro lens,  series-connected line of multi-element photodetector,  first decoder,  encoder  and a second decoder,  the outputs of which are connected to the corresponding inputs of the first decoder and to the inputs of the key block,  includes a series-connected pulse counter,  third decoder and register block,  the information inputs of which are connected to the outputs of the encoder,  and the first three control inputs are connected to the outputs of the third decoder,  ADC input is voltage divider input,  the first control input is the counting input of the pulse counter,  the second is the combined inputs of the pulsed LED and the fourth control input of the register block,  the third is the control input of the pulse counter,  the output is the outputs of the register block,  the first and second code generators are identical,  each contains a serially connected trigger and a switching unit,  the inputs of which are the first information input of the code generator,  and three channels  the first and second channels are identical,  their inputs are connected to the corresponding outputs of the switching unit,  and the outputs of the three channels are combined,  the first channel includes a series-connected block of elements AND,  the first and second elements OR and the output key,  and a self-propelled pulse distributor,  the second channel includes a series-connected block of elements AND,  the third and fourth elements OR and the output key,  and a self-propelled pulse distributor,  the first inputs of the block of elements AND are connected to the corresponding outputs of the switching block,  the second inputs of the block of elements And are connected to the outputs of the self-propelled pulse distributor of its channel,  the outputs of the output keys are combined and are the first output in the first and second code generators,  the third channel includes two blocks of AND elements,  the inputs of which are the second information input,  fifth and sixth elements OR,  the output of the fifth OR element is connected to the second input of the second OR element in the first channel,  the output of the sixth OR element is connected to the second input of the fourth OR element in the second channel,  and two self-propelled pulse distributors,  the outputs of which are connected to the second inputs of the corresponding blocks of AND elements,  includes the first and second keys,  and series-connected pulse counter and decoder,  two outputs of which are connected respectively to the first and second control inputs of the first and second keys,  in the second code generator, the decoder also has a third output,  arising from the second output of the second code generator,  connected to the counting input of the pulse counter and to the input of the first self-propelled pulse distributor of the transmitting side,  the output of the first key is connected to the inputs of the self-propelled pulse distributors in the first and second channels,  the output of the second key is connected to the inputs of the self-propelled pulse distributors in the third channel,  the third and fourth information inputs of the code generators are the third inputs of the second and fourth OR elements, respectively,  the first control input is the trigger input,  the second is the combined inputs of the keys and the counting input of the pulse counter,  the third is the combined signal inputs of the output keys,  the fourth is the control input of the pulse counter,  the third code generator contains a serially connected trigger and a switching unit,  and two identical channels,  the channel inputs are connected to the outputs of the switching unit,  and their outputs are combined and are the output of the third code generator,  the first channel includes a series-connected block of elements AND,  the first and second elements OR and the output key,  and a self-propelled pulse distributor,  the second channel includes a series-connected block of elements AND,  the third and fourth elements OR and the output key,  and a self-propelled pulse distributor,  the first inputs of the blocks of elements AND are connected to the corresponding outputs of the switching unit,  the second inputs of the blocks of elements AND are connected to the outputs of the self-propelled pulse distributor of their channel,  the first information input is the inputs of the switching unit,  the second and third information inputs are the second inputs of the second and fourth elements OR,  the first control input is the trigger input,  the second is the combined inputs of self-propelled pulse distributors,  the third is the combined signal inputs of the output keys,  the combined output of which is the output of the third code generator,  containing the receiving side  including antenna  Control block,  the first,  second and third paths for receiving and processing video signal codes,  the inputs of which are connected to the antenna,  video display device,  two channels of sound reproduction and a channel for generating control signals,  the first path for receiving and processing codes of video signals contains a series-connected unit for receiving a radio signal,  whose first input is connected to the antenna,  the second group of inputs is connected to the first group of outputs of the control unit,  radio frequency amplifier and bipolar amplitude detector,  first and second pulse shapers,  connected respectively to the first and second outputs of the bipolar amplitude detector,  and the signal channel R,  containing the first and second registers of the signal R,  connected respectively to the outputs of the first and second pulse shapers of its path,  series-connected code processing unit,  the first and second information inputs of which are connected to the outputs of the first and second registers of the signal R,  first delay block and adder,  and the second block of delays,  the inputs of which and the first inputs of the adder are connected to the outputs of the code processing unit,  the second inputs of the adder are connected to the outputs of the first block of delays,  the second path for receiving and processing codes of video signals contains a series-connected unit for receiving a radio signal,  whose first input is connected to the antenna,  the second group of inputs is connected to the first group of outputs of the control unit,  radio frequency amplifier and bipolar amplitude detector,  first and second pulse shapers,  connected to the first and second outputs of a bipolar amplitude detector,  and signal channel B,  including the first and second registers of signal B,  connected respectively to the outputs of the first and second pulse shapers,  series-connected code processing unit,  the first and second information inputs of which are connected to the outputs of the first and second registers of signal B,  first delay block and adder,  and the second block of delays,  the inputs of which and the first inputs of the adder are connected to the outputs of the code processing unit,  the second inputs of the adder are connected to the outputs of the first block of delays,  the third path for receiving and processing codes of video signals contains a series-connected unit for receiving a radio signal,  whose first input is connected to the antenna,  the second group of inputs is connected to the first group of outputs of the control unit,  radio frequency amplifier and bipolar amplitude detector,  first and second pulse shapers,  connected to the first and second outputs of a bipolar amplitude detector,  and signal channel G,  including the first and second registers of the signal G,  connected to the outputs of the first and second pulse shaper of its path,  series-connected code processing unit,  the first and second information inputs of which are connected to the outputs of the first and second registers of the signal G,  first delay block and adder,  and the second block of delays,  the inputs of which and the first inputs of the adder are connected to the outputs of the code processing unit,  the second inputs of the adder are connected to the outputs of the first block of delays,  the channel for generating control signals includes serially connected block selection horizontal sync pulses (SSI),  frequency synthesizer  key,  pulse counter and decoder,  and a block allocation of stereo clock pulses (SIS),  three block inputs,  SSI allocations are connected to the outputs of the first pulse shapers in the first,  second  the third path of receiving and processing codes of video signals,  the output of the block is connected to the first control input of the frequency synthesizer,  to the first control input of the key,  to the fourth input of the block allocation of the SIS and the second control inputs of the first blocks of delays in the signal channels R,  G  AT,  the first,  second,  the third inputs of the block allocation SIS connected to the outputs of the second pulse shapers in the first,  the second and third paths for receiving and processing codes of video signals,  the second group of inputs of the frequency synthesizer is connected,  to the second group of block outputs,  management  the first output of the frequency synthesizer is connected to the signal input of the key,  and to the first control inputs of the signal registers R,  G  AT,  the second output is connected to the second (clock) control inputs of the signal registers R,  G  In and to the corresponding control inputs in the first and second channels of sound reproduction,  to the corresponding control inputs of which the third output of the frequency synthesizer is connected,  the fourth output of which is connected to the control inputs of the code processing units in the signal channels R,  G  AT,  the fifth output of the frequency synthesizer is connected to the third inputs of the blocks of the reception of the radio signal in the first and second paths of the reception and processing of codes of video signals,  the sixth output is connected to the third input of the radio signal receiving unit in the third path of receiving and processing video signal codes,  the seventh output of the frequency synthesizer is connected to the third control inputs of the first delay blocks and to the first control inputs of the adders in the signal channels R,  G  AT,  the eighth output is connected to the first control inputs of the first delay blocks in the signal channels R,  G  AT,  the first output of the decoder is connected to the corresponding inputs in the first and second channels of sound reproduction,  its second output is connected to the control input of the pulse counter,  to the second control input of the key and to the corresponding control inputs in the first and second channels of sound reproduction,  the first and second information inputs of which are connected respectively to the outputs of the first and second pulse shapers in the first and second paths of the reception and processing of video signal codes,  code processing units are identical,  each includes a trigger,  whose input is the control input of the block,  first to sixth registers,  the first and second blocks of delay elements,  adder and sixteen diodes,  the control input of the adder is connected to the input of the trigger,  information inputs of the first and second registers are bitwise combined and are the first information input of the block,  the second information input of which is the inputs of the first block of delay elements,  the outputs of which are connected bitwise combined inputs of the third and fourth registers,  the first trigger output is connected to the control inputs of the fifth,  second  third registers,  the second trigger output is connected to the control inputs of the sixth,  the first  fourth registers,  the outputs of the first register are connected to the inputs of the fifth register and through diodes to the first inputs of the adder,  to which the outputs of the second register are connected,  the outputs of the third register are connected to the inputs of the sixth register and through diodes to the second inputs of the adder,  to which the outputs of the fourth register are connected,  the corresponding outputs of the adder are connected to the inputs of the second block of delay elements,  the outputs of which are combined bitwise with the outputs of the fifth and sixth registers and are outputs of the code processing unit,  the first delay blocks are identical,  each includes a series-connected element And,  first and second keys,  first and second pulse distributors,  eight registers  each of which contains the corresponding number of digits,  information inputs are bitwise combined second inputs of bits of eight registers,  outputs are bitwise combined outputs of bits from the first to eighth registers,  the first and second control inputs are the first and second inputs of the And element,  the third control input is the combined signal inputs of the first and second keys,  the output of the AND element is connected to the first control input of the first key and to the second control input of the second key,  exit the first key is connected to the input of the first pulse distributor, the outputs of which are connected in series to the first (clock) inputs from the first to the last digits from the first to eighth registers, the last output (1920th) the first pulse distributor is connected through a diode to the first inputs of the last bits of eight registers and is directly connected to the second control input of the first key and to the first control input of the second key, the output of which is connected to the input of the second pulse distributor, the outputs of which are connected in series from the first to the last to the first inputs bits of eight registers in sequence from the last bit of registers to the first, the last output of the second pulse distributor is connected through a diode to the first input At the first bits of eight registers and through a diode it is connected to the first control input of the first key and to the second control input of the second key, the horizontal sync pulse allocation unit (SSI) includes the first, second, third pulse counters, the first and second elements and, the first, second, third NOT elements and a diode, information inputs are the counting inputs of the first, second, third pulse counters, the output is the output of the second AND element, the outputs of the first and second pulse counters are connected to the inputs of the first AND element, output for which the output of the third pulse counter is connected to the inputs of the second AND element, the output of which through the diode and the outputs of the elements are NOT combined and connected in parallel to the control inputs of the pulse counters, the inputs of the first, second, third elements are NOT connected respectively to the counting inputs of the first, second, third pulse counters, the block of separation of clock pulses of stereo pairs (SIS) includes the first, second, third pulse counters, the counting inputs of which are the first, second, third information inputs of the block, the first , the second, third elements are NOT, the inputs of which are connected to the inputs of the first, second, third pulse counters, respectively, the first, second, third elements And, the inputs of the first element And are connected to the outputs of the first and second pulse counters, the inputs of the second element And are connected to the outputs of the first of the element And and the third pulse counter, the inputs of the third element And are connected to the output of the second element And to the fourth information input of the block, the output of the third element And is the output of the block, connected through the diode to the combined output there are NOT elements that are connected in parallel to the control inputs of the pulse counters, characterized in that on the transmitting side the frequency synthesizer has a tenth output of frame frequency pulses connected to the trigger input and the third through sixth keys are entered, the first control inputs of the third and fifth keys and the second control inputs of the fourth and sixth keys are connected to the first output of the trigger, the second control inputs of the third and fifth keys and the first control inputs of the fourth and sixth keys are connected to the second output to the trigger, from the first to sixth drives of the frame codes, from the first to sixth pulse shaper units are entered on the receiving side, the video information display device is represented by a LED flat panel screen (SD screen), on the upper part of the housing, which has an IR transmitter, the control input of which it is connected to the output of the stereo pair clock extraction unit (SIS), and 3D glasses with an IR receiver on the frame of 3D glasses are introduced, the input windows of which are in use opposite the output window of the IR transmitter, store if the frame codes are identical, each includes register blocks by the number of half lines in the frame, the information input of each frame code drive is 1–8 inputs of register blocks, the information inputs of the first, third, fifth frame code drives are connected to 1-8 adders outputs, respectively in the signal channels R, G, B, the information inputs of the second, fourth and sixth akoopitel frame codes are connected to 1-8 outputs of the second delay blocks, respectively, in the signal channels R, G, B, the first control input n frame code driver is the first control input of the first block of registers, the second control input is the combined second control inputs of the register blocks, the third is the combined third control inputs of the register blocks, the first is the control inputs of the drive code blocks are combined and connected to the eighth output of the synthesizer, frequencies, the second control the inputs of the drive codes of the frame are combined and connected to the ninth output of the frequency synthesizer, the third control inputs of the drives of the code codes are combined and connected to the seventh output of the frequency synthesizer, each control output of the previous block of registers is the first control input of the next block of registers, the control output of the last block of registers is connected in parallel to the fourth control inputs of all blocks of registers, the outputs of each drive of frame codes are the parallel outputs of all blocks of registers connected to the inputs of its block of pulse shapers, each of which includes pulse shapers according to the number of outputs from the frame code storage, register blocks They are identical, each includes the first and second keys, a pulse distributor and eight registers, 1-8 information inputs of the register block are the bitwise combined third inputs of the bits of the eight registers, the outputs of all the bits of the eight registers are parallel outputs of the register block, the first control input is the first control input the first key, the second is the signal input of the second key, the third is the signal input of the first key, the fourth is the first control input of the second key connected to the control output at the last block of registers, the output of the first key is connected to the input of the pulse distributor, the outputs of which are sequentially from the first to the last connected to the first control inputs of the bits in parallel to eight registers, the last output is connected to the second control input of the first key and is the control output of the block of registers, the output of the second key connected in parallel to the second control inputs of all bits of eight registers and to the second control input of the second key, the LED flat-panel screen consists of LED cells (LED cells) by the number of resolving elements (pixels) in the frame (1920 × 1080), each LED cell contains an opaque housing, a matrix of the corresponding number of LEDs of the three primary colors R, G, VF and a microlens in the output end of the LED housing -cells, the matrix of LEDs is located in the focal plane of the microlens and contains the number of LEDs of each color according to the number of bits in the code, and each LED has a neutral filter, the density of which is determined by the LED belonging to the binary category of the code, the LED inputs odov LED cells connected to respective outputs of pulse shaping units.

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