RU2304361C1 - Video camera - Google Patents

Abstract

FIELD: domestic video-engineering appliances for recording and reproducing video images.

SUBSTANCE: newly introduced in video camera are second lens, dual-channel photoelectric converter, five video-signal analog-to-digital converters, six coders, and reproducing device that has R, G, and B video signal channels, each incorporating decoder, code processing unit, and pulse amplifier unit, and also IR transmitter, 3D spectacles, and IR receiver on spectacle frame.

EFFECT: ability of obtaining stereo pairs in taking right- and left-hand pictures and of perceiving three-dimensional image in reproduction.

14 cl, 1 tbl

Description

The invention relates to household digital video equipment, can be used for recording and playback of video images. The prototype adopted a digital video camera [1, p. 546], which contains a lens, a photoelectric converter from the light-sensitive matrices of three CCDs, an ADC of a video signal and a codec, a video detector, a device for recording to a digital information storage device, control components, and an external interface. The disadvantage of the prototype is the lack of formation and reproduction for the viewer to perceive the volumetric image.

The purpose of the invention to introduce into the process of the video camera the formation and reproduction for the viewer to perceive a three-dimensional image. The technical result is to obtain when shooting the right and left frames of stereo pairs and the perception of the viewer when playing a three-dimensional image. The technical result is achieved by introducing into the video camera a two-channel photoelectric converter, forming sterepairs from the right and left frames, sequentially reproduced on the screen of a digital monitor and observed by the viewer separately through ZD glasses, obtaining the effect of a three-dimensional image. An image of one space is formed in the camcorder in two successive right and left frames making up a stereo pair. The frequency of stereo pairs is 25 Hz, the frame rate is 50 Hz / 25 + 25 /. Video mode in the camcorder: 600 _lines × 400 _samples × 50 _frames . The received digital information is compressed in the encoders of the camera with coefficients from 2 to 255 and is recorded in the digital information storage device. For playback, the digital information storage device is connected to a playback device in which the compressed code streams are restored, the number of samples in each line is doubled, and the video signal codes R, G, B sterepairs are fed to the digital inputs of the digital monitor used. The viewer perceives the volumetric image through the ZD glasses using an IR transmitter mounted on the monitor body and an IR receiver located on the frame of the ZD glasses.

The essence of the claimed invention is that a second lens, a frequency synthesizer, a trigger, three keys, a second through sixth ADC video signal, two ADC audio signals are introduced into a video camera containing one lens, a photoelectric converter, an ADC of a video signal, a digital information storage device and a video detector, first through sixth encoders, first through fifth blocks of AND elements and a playback device, the photoelectric converter comprises a first amplifier and a first piezoelectric deflector with a reflector at the end, a second amplifier and a second a baffle with a reflector at the end, a third amplifier and a third piezoelectric baffle with two reflectors at the end, six voltage sources, four dichroic mirrors, six micro lenses, six photodetectors, six pre-amplifiers, horizontal and vertical scan units, the playback device contains a frequency synthesizer, AND element and a key, three channels of video signals, each of which includes a key, a decoder, a code processing unit and a block of pulse amplifiers, two sound channels, each of a key, a decoder, a signal register and the sound, the unit for generating the sound analog signal and loudspeaker, and introduced an IR transmitter, ZD glasses and an IR receiver on the frame of ZD glasses.

Functional diagram of the video camera in figure 1, the playback device in figure 2, the scan frame in figure 3, the shape of the control voltage in figure 4, the ADC of the video signal in figure 5. The ADC of the sound signal in FIG. 6, the construction of the piezoelectric deflector in FIG. 7, the summing amplifier in FIG. 8, the block of elements AND in FIG. 9, the encoder in FIG. 10, the decoder in FIG. 11, the code processing unit in FIG. 12, scan frame on the screen of Fig.13.

The video camera includes / Fig. 1/ first lens 1 / right /, second lens 2 / left /, photoelectric converter 3, which is a sensor of video signals of two images of the same space: right R _P , G _P , V _P and left R _L , G _L , In _L , the first piezoelectric deflector 4 with a reflector at the end, located in the focal plane of the first lens 1, the first amplifier 5, the first source 6 of the positive reference voltage, the second source 7 of the negative reference voltage, the horizontal scanning unit 8 from the master oscillator 9 and the output stage 10, after before the second amplifier 11 and the second piezoelectric deflector 12 are properly connected, the front end of which has two faces located at a corresponding angle to each other and with a reflector on each face, a third source of positive reference voltage, a fourth source of negative reference voltage 14, and a third amplifier 15 connected in series and a third piezoelectric deflector 16 with a reflector at the end located in the focal plane of the second / left / lens 2, the fifth source 17 of the positive reference voltage, the sixth source 18 from negative reference voltage, the second lens 2 is located to the left of the first lens 1, its optical axis is parallel to the optical axis of the lens 1, the distance between them corresponds to the optimal stereoscopic effect for human vision, the first 19 and second 20 dichroic mirrors are arranged one after another, the first 21 , the second 22, the third 23 micro-lenses, the first 24, the second 25, the third 26 photodetectors, the first 27, the second 28, the third 29 pre-amplifiers arranged sequentially one after another t e 30, fourth 31 dichroic mirrors, fourth 32, fifth 33, sixth 34 micro lenses, fourth 35, fifth 36, sixth 37 photodetectors, fourth 38, fifth 39, sixth 40 preamplifiers, block 41 frame scan, including a series-connected element And 42 the master oscillator 43 and the summing amplifier 44. The video camera includes a first ADC 45 / signal R _P /, a second ADC 46 / signal G _P /, a third ADC 47 / signal V _P /, a fourth ADC 48 / signal R _L /, a fifth ADC 49 / signal G _L /, sixth ADC 50 / signal V _L /, first ADC 51 sound signals Sv 1 and second ADC 52 sound signals Sv 2, a frequency synthesizer 53, the first key 54 and the trigger 55 connected in series, the second key 56, the third key 57, the first through sixth 58-63 encoders, the first 64, the second 65, the third 66 element blocks And, the first 67, the second 68 encoders sound signal, the first 69 and second 70 blocks of elements And the sound signal, the video detector 71, the drive 72 digital information and the device 73 playback.

The playback device 73 / FIG. 2/ comprises a frequency synthesizer 74, a video signal channel R including a first key 78 and serially connected a first decoder 75, a first code processing unit 76 and a first pulse amplifier unit 77, a video signal channel G including a second key 82 and sequentially connected to a second decoder 79, a second code processing unit 80 and a second pulse amplifier unit 81, a video signal channel B including a third key 86 and serially connected a third decoder 83, a third code processing unit 84 and a third pulse processing unit 85 amplifiers, contains a first sound channel including a fourth key 91 and a first sound code decoder 87, a sound signal register 88, an analog audio signal generating unit 89 from a DAC, a low-pass filter and a power amplifier, and a loudspeaker 90, a second sound channel including the fifth key 96 and the second audio code decoder 92, the audio signal register 93, the analog audio signal generating unit 94 from the DAC, the low-pass filter and the power amplifier, and the loudspeaker 95, and include the last sequences coupled AND gate 97 and the sixth switch 98, IR transmitter 99, disposed on the housing of the digital monitor, ZD-points 100 and IR receiver 101, located on the rim ZD-points. To reproduce the image, a digital monitor with a digital input is used for the signal codes R, G, B separately. As a digital monitor, digital flat panel LCD monitors of TFT technology can be used [5, p. 476, 487 of Table 14.5], monitors using plasma / RDR / or LED / LED / technology and electroluminescent digital monitors [5, p. 489] having digital inputs for receiving R, G, B codes, receiving codes of right and left frames of stereo pairs and control signals of a line frequency of 30 kHz, frame frequency of 50 Hz and stereo frequency of 25 Hz, the digital monitor performs alternating sweeps of the right and left frames, raster scan and frames should scan the raster and frames by the photoelectric converter 3, Fig. 13.

Playable video mode: 600 _lines × 800 _samples × 50 Hz. Six ADCs 45-50 are identical (Fig. 5/), each includes a series-connected video amplifier 102 and a piezo-deflector 103 with a reflector at the end, a source of positive reference voltage 104, a source of negative reference voltage 105, an emitter from a pulsed LED 106, aperture diaphragm 107, and a micro lens 108, line 109 of a multi-element photodetector, the input windows of which are located against the reflector of the piezoelectric deflector 103 and are optically connected to the emitter, and the encoder 110. The input of the ADC is the input of the video amplifier 102, the output is the outputs of the encoder 110. The control input is the input of a pulsed LED 106. The ADCs 51 and 52 are identical (Fig. 6/), each includes a series-connected voltage divider 111, a key block 112, a matching amplifier 113, an audio frequency amplifier 114 and a piezo-reflector 115 with a reflector at the end , a source of a positive reference voltage 116, a source of a negative reference voltage 117, an emitter of a pulsed LED 118, a slit aperture 119 and a micro lens 120, an array of multi-element photodetector 121, the input windows of which are located rotiv pezodeflektora reflector 115 and optically coupled to the transmitter and sequentially connected a first decoder 122, encoder 123 and the second decoder 124 and the register 125, the outputs of which are the outputs of the ADC 51/52 /. The input is the input of the voltage divider 111, the control input is the input of the pulsed LED 118. The piezoelectric deflectors 3, 11, 16, 103, 115 are made in the same way / Fig. 7/, each includes [3, p.118] the first 126, the second 127 piezoelectric elements, internal the electrode 128, the first 129, the second 130 are the external electrodes, one end of the piezoelectric plates is fixed in the holder 131, a light reflector 132 is fixed at their free end. The summing amplifier 44 includes / Fig. 8/ connected in series 10-bit pulse counter 133 and a decoder 134, the first 135 and second 136 keys, first 137 and second 138 forms pulse watchers and output amplifier 139. The inputs are the first input of the output amplifier 139 and the counting input of the pulse counter 133, the control input is the combined inputs of the control input of the pulse counter 133, the first control input of the key 135 and the second control input of the key 136, the output is the output of the output amplifier 139 The first to sixth encoders 58-63 (Fig. 10/) are identical, each includes a series-connected register 140, a comparison circuit 141 / comparator /, a pulse counter 142 and a decoder 143, and is connected in series block 144 of the delay elements, block 145 of the keys and the output register 146. 1-8 information inputs are bitwise combined inputs of the register 140, the first inputs of the comparison circuit 141 and the inputs of the block 144 of the delay elements. The outputs are outputs 1-9 bits of the output register 146.

The first and second sound signal encoders 67, 68 are made similarly to encoders 58-63, and respectively, 16-bit sound signal codes are register 140, comparison circuit 141, pulse counter 142, and decoder 143 are 16-bit, block 144 has 16 delay elements, block 145 has 16 keys / by the number of bits in the code /, and the output register 146 is 17-bit.

The first to third decoders 75, 79, 83 (Fig. 2/ are identical, each includes / Fig. 11/ connected in series 9-bit first register 147, the first block 148 keys / 8 keys for the number of bits in the code / and 8-bit the second register 149, connected in series to the second block of keys 150 / of eight keys /, an 8-bit subtracting counter 151 pulses and a decoder 152, the first 153 and second 154 keys. The information input of the decoder is the information input of the first register 147, the first control input is the first control input of the first register 147, the second control input is the combined inputs of the second control input of the first register 147 and the signal inputs of the keys 153, 154, the first control output of the decoder is the output of the 9th the discharge of the first register 147, the second control output of the decoder is the output of the decoder 152. The output of the decoder is the outputs of 1-8 bits of the second register 149. The decoders 87, 92 sound codes are similar to decoder 75, and since the audio codes are 16-bit, the first register 147 has 17 bits, the first 148 and second 150 key blocks each have 16 keys, the subtracting pulse counter 151 and the decoder 152 are 16-bit, the second register 149 is also 16-bit.

Blocks 76, 80, 84 are identical, each includes / Fig. 12/ trigger 155, first 156, second 157 key blocks / 8 pieces each /, first 158, second 159, third 160, fourth 161 registers, fifth 162 and sixth 163 registers, block 164 delays, adder 165 and 16 diodes. 1-8 information inputs are bitwise combined inputs of 156, 157 key blocks, they are received at a frequency of 12 MHz / 12 MB / s / color signal codes R. The control input is trigger input 155. The outputs are bitwise combined 1-8 outputs of registers 162 , 163 and a block of 144 delays. From the output of block 76/80, 84 /, codes in parallel form follow with a frequency of 24 MHz / 24 MB / s /, the repetition period is 41.5 ns, into block 77 of pulse amplifiers, of which there are 8 pieces in the block.

The digital information storage device 72 is represented by five solid state carriers, for example, of the PC Card type [p. 328], combined in one case for the convenience of placing them in a video camera. 1-3 solid-state carriers synchronously accumulate 9-bit color codes R, G, B / 9th service, appears when digital information is compressed /, fourth and fifth solid-state carriers synchronously accumulate 17-bit codes of the first and second audio signals / 17th category service, appears when compressing information /. The maximum speed of arrival of codes of video signals at 1, 2, 3 inputs of a drive 72 of digital information is 108 Mbps / 12 Mb / s /, the maximum speed of arrival of codes of sound signals at 4 and 5 inputs of block 72 / Fig. 1/ is 1.53 Mbps During the hour of operation of the camera in the absence of information compression, the amount of information of each color signal will be 43.2 GB / 12 MB / s × 3600 s /. The volume of audio information of one channel will be 5.5 Gb / h. In the inventive camcorder, digital streams of each are compressed with a floating coefficient from 2 to 255, so the recorded amount of digital information will be 50-100 times less. Video detector 71 is represented by an LCD display based on a liquid crystal TFT matrix of size 4 × 5 cm. Video detector 71 uses ADC codes 45, 46, 47 / Fig. 1/, a reproduced frame of 600 lines with 400 samples in each, a frame rate of 25 Hz, which control signals impulses of a frequency of a lad of 30 kHz and pulses of a frame frequency of 50 Hz.

The sampling frequency of the video signals in the camcorder:

f _D = 600 _lines × 50 Hz × 400 _counts = 12 MHz,

where: 400 is the number of samples encoded in a string.

f _pp = 600 × 50 Hz = 30 kHz

where: 50 Hz - frame rate: 25 right + 25 left.

The clock frequency of the bits of the codes of the video signals in the drive 72 digital information:

f _T = 12 MHz × 9 bits = 108 MHz

9 - the number of bits in the code, the 9th bit is service.

ft _3V = 90 kHz × 17 _p = 1.53 MHz

90 kHz is the sampling frequency of audio signals.

17 - the number of bits in the sound code after compression of information.

Photoelectric converter 3 / Fig. 1/ is a sensor of the right and left images of the same space, generates three analog video signals of the right image R _P , G _P , V _P , which from the pre-amplifiers 27, 28, 29 enter the ADC 45, 46 , 47, and three analog video signals of the left image R _L , G _L , B _L , which come from the preamplifiers 38, 39, 40 in the ADC 48, 49, 50. The ADC 45-50 convert the analog video signals into 8-bit codes. The sequential issuance of codes of video signals first with an ADC 45-47 and then with an ADC 48-50 is performed by a trigger 55 and keys 56, 57. Pulses of a frame frequency of 50 Hz from the eighth output of the frequency synthesizer 53 through the open first key 54 are fed to the input of the trigger 55. The signal from the first output of trigger 55 opens the key 56, which transmits U _T during the 20 ms period of the first / odd / frame 12 MHz sampling pulses to the ADC 45-47 clock inputs, the codes from which are sent in parallel at a frequency of 12 MHz / MB / s / to the encoders 58, 59, 60. At this time, the ADCs 48-50 do not issue codes, they do not receive U _T imp pulses. With the arrival of the second 50 Hz pulse to trigger 55, the key 56 closes, the key 57 opens, which transmits clock pulses to the control inputs of the ADC 48-50, the codes from which during 20 ms are sent in parallel to the inputs of the encoders 61, 62, 63. The input trigger 55 pulses of 50 Hz come from the output of the first key 54, which opens with a stereo frequency pulse of 25 Hz from the output of the element And 42 in the block 41 frame scan This determines the formation of video signal codes always from the first frame of a stereo pair. With an odd frame, the piezoelectric deflector 12 scans the frame down (Fig. 3/): the first frames in the stereo pair are the first, the left frames are the second. The ADCs 45-47 encode the video signals of the right frames only, the ADCs 48-50 encode the video signals of the left / even / frames. A frequency synthesizer 53 produces: from the first output, 12 MHz pulses of the sampling frequency of the video signals to the inputs of the keys 56, 57 and to the inputs of the blocks of 64-66 elements And, from the second output, the frequency pulses of 50 Hz frames to the input of the first key 54, from the third output pulses of 90 kHz the sampling frequency of the sound signal to the control inputs of the ADC 51, 52, from the fourth output pulses of 1.53 MHz to the control inputs of blocks 69, 70 of the And elements and to the first control input of the drive 72 of digital information, from the fifth output pulses of 108 MHz to the second control input of the drive 72 digital and information, from the sixth - 15 kHz pulses to the horizontal block 8, from the seventh - 30 kHz horizontal pulses to the first input of the I 42 element and to the second input / control / video detector 71, from the eighth output the 25 Hz pulses to the second input of the I 42 element The ADC 51, 52 convert the sound signals into 16-bit codes, which are supplied in parallel to the inputs of the encoders 67, 68. The horizontal scanning unit 8 consists of a master oscillator 9 and an output stage 10. From the block 10, the control voltage is triangular isosceles .4 / amplified by amplifiers 5 and 15 and at drives piezoelectric deflectors 4 and 16 into oscillatory motion with a frequency of 15 kHz. The scan of the lad at the same time comes with a frequency of 30 kHz and without reverse moves / Fig.3/. The signal from the amplifier 5/15 / is supplied to the internal electrode 128 / Fig. 7/, the voltage from the source 6/17 / is applied to the external electrode 129, and the voltage from the source 7/18 / is applied to the external electrode 130. With the supply of the control voltage to the internal electrode 128, the piezoelectric deflectors 4 and 16 come into synchronous and in-phase oscillations and scan the lines of the right and left frames, respectively, on the first and second reflectors of the piezoelectric deflector 12, which performs vertical scanning of the image. The process of operation of the piezoelectric deflector 11 is the same as the piezoelectric deflector 4, but it oscillates with a frequency of 25 Hz and forms 50 frames per second, the frame scan also without reverse moves / 3 /. From the output of the summing amplifier 44, a linearly varying and stepwise control voltage is amplified by the amplifier 11. When scanning the right / odd / frames, the first reflector of the piezoelectric deflector 12 deflects the line scan down, while scanning the left / even / frames the second reflector deflects the line scan up. The summing amplifier 44 sums the triangular control voltage from the master oscillator 43 with pulses of 30 kHz line frequency, which gives a linear and step voltage (Fig. 4/ for amplifier 11. Each pulse of the line moves the next line one step apart / at the time of call lines beyond the edge of the frame. 600 lines are expanded in the frame; progressive / line-by-line scanning of lines. The purpose of the blocks 133-138 / FIG. 8/ is to apply negative / positive / pulses of the corresponding amplitude and duration to the second input of the output amplifier 139 at the right time. Before scanning the stereo pair, the signal U _О 25 Hz from the element And 42/1 / zero resets the counter 133 pulses. Counter 133 is 10-bit and counts pulses of line frequency 30 kHz, the cycle counts 600 pulses. At the end of the odd / right / frame scan with the arrival of 600 pulses, the pulse counter 133 generates a binary code of the number 600/1001011000 /, which is decoded by the decoder 134, the output pulse closes the first key 135, opens the second key 136, which passes the next 600 pulses to the second shaper 138 pulses, issuing positive pulses to the second input of the output amplifier 139. There is a scan of the left frame of the stereo pair. Then the second pulse of 25 Hz arrives at the first control input of the summing amplifier 44, the counter 133 is reset, the process of scanning the right and left frames of the stereo pair is repeated. The width of the reflectors of the piezoelectric deflectors 4 and 16 is the same, adopted 0.02 mm, length 12 mm / 0.02 mi × 600 /. The width of the piezoelectric reflector 12 reflectors is 0.02 mm, the length is 8 mm / 0.02 mm × 400 _counts . The reflected rays from the right reflector of the piezoelectric deflector 12 arrive: red rays are reflected from the first dichroic mirror 19 and are collected by a micro lens 21 into a photodetector 24, blue rays are transmitted from a second dichroic mirror 19, reflected from a second 20 and a micro lens are collected into a photodetector 26, green rays pass through both dichroic mirrors 19, 20 and a micro-lens 22 are collected in a photodetector 25. From the photodetectors, the analog video signals are fed to their pre-amplifiers 27, 28, 29. The rays reflected from the left of the piezoelectric deflector 12, analog video signals are fed to preamplifiers 38, 39, 40. Six analog video signals are fed to the ADC inputs 45-50, which have one conversion principle, consisting of (Fig. 5/) the scanning of the beam from the LED 106 by the reflector of the piezoelectric deflector 103 along the plane the input windows of the line 109 multi-element photodetector. The light pulse is converted by the photodetector of the line into an electrical signal that excites the corresponding bus of the encoder 110, which generates a code for the instantaneous value of the input video signal. The sampling frequency of 12 MHz is supplied to the input of the LED 106. The slit aperture 107 and the micro-lens 108 form a beam with an aperture equal to the size of the input window of one photodetector of the line 109. The radiation source is an AL402A LED with a response time of 25 ns, with a margin satisfying 12 MHz / 83 ns / line 109 includes 255 photodetectors for encoding video signals with an 8-bit code, ^2-8 . Photodetectors are avalanche photodiodes of the APD with a response time of 10 ns. The output of each photodetector is connected to the corresponding input of the encoder 110, which is represented by the K155IV1 chip [4, p.231] with a response time of 20 ns. The conversion time is 30 ns / 10 + 20 /, which is 33 · 10 ⁶ prev / s. The encoder 110 generates codes from 00000001 to 11111111. The first photodetector corresponds to the code 00000001, the second to the code 00000010, the third to 00000011, etc., the 255th to the code 11111111. The information creation rate by each ADC is: 12 MHz × 8 times = 96 Mbps or 12 MB / s.

The ADCs 51 and 52 convert two audio signals into 16-bit codes. Sampling rate 90 kHz. The line 121 (Fig. 6/) of a multi-element photodetector includes 1024 photodetectors and converts the audio signal into 10-bit codes, 2 ¹⁰ . The resolution is 10 μV. The conversion of signals exceeding 2 ¹⁰ is performed jointly by decoder 122, second decoder 124, voltage divider 111 and key block 112. With their use, the encoding range becomes 0-0.65536 V, i.e. 2 ¹⁶ . From the encoder 123, 16-bit codes are sent to the register 125, from which they are issued in parallel form by 90 kHz signals to the encoder 67/68 /. Codes of video signals from ADC 45-47 go to encoders 58-60, codes from ADC 48-50 go to encoders 61-63, codes from ADC 51, 52, respectively, to encoders 67, 68. All encoders work the same and compress the digital information stream performance of operations: comparing the values of the stream codes in magnitude to determine codes of equal magnitude and successive ones, counting the number of codes of equal magnitude, and generating a binary code of this number, introducing a code of the number of equal in magnitude codes into the stream after the first code its sequence and an introduction to this a token code for its identification.

The number of equal in size codes following one after another will change, therefore, the compression coefficient will also change from 2 to 255. The more consecutive equal in size codes, the higher the degree of information compression. When restoring the flow of information, the code of the number of codes of equal magnitude must reveal itself; for this, an identification signal is entered into the 9th bit of the code in the 8-bit code of the video signal in the encoder. Eight digits are informative, the 9th digit signal is a service marker for identifying the code of the number of equal codes in the stream when restoring compressed information.

The operation of the encoder 58 / 59-63 /, Fig.10.

The 8-bit code with the ADC 45 arrives simultaneously at 1-8 inputs of the register 140, at the first inputs of the comparison circuit 141 and at the inputs of the delay element block 144. The initial state of the keys in block 145 is open. The code in block 144 is delayed for a duration of 18 ns / response time comparison circuit 141 / and enters through the public keys of block 145 into 1-8 bits of the output register 146. The comparison circuit 141 performs a comparison of the values of each previous and subsequent codes to determine their equality or inequality . The comparison circuit 141 is represented by two 530SP1 microcircuits with a response time of 18 ns [4, p. 279]. With the inequality of codes A> B, a signal appears at output 2 / in output 5 [], [2, p.272 Fig. 2.190] /, with equal codes A = B, output 6 / appears in output 6 /, with A <B the signal at the output 3 / in the chip output 7 /. In case of equality codes A = B signal from the output of unit 1 closes the keys 141 in the block 145 receives a countable pulse U _MF to the count input of the counter 142 and to the first control input of register 140 as the signal U _vyd. The counter 142 pulses counts the pulses while in the stream are codes equal in magnitude.

In the case of inequality codes from circuit 141 compares with the signal from output 2, or 3, which are integrated, and their signals are used as control register 140 to reset / input 2 / U _vyd and outputting a code of the output register 146. When the code counter 142 equality / from K531IE17P microcircuits with a response time of 12 ns [4, p. 156] / counts the number U _{cc of} equal codes. The counter 142 pulses 8-bit, the maximum code in it is 11111111/255 /. When comparing unequal codes in scheme 141, a signal appears from output 2 or 3, which first outputs the code contained in it from output register 146, then outputs a code generated by counter 142 to 1-8 bits of output register 146 and simultaneously to the 9th bit of register 146 enters a signal, which is a sign of code from the counter 142 pulses, opens the keys in block 145 and resets U _О register 140 / input 2 /. The code / previously contained in the output register 146 / before the first pulse to the counter 142 / is the first code in a sequence of equal codes. The codes following this code are equal in size codes, counted by the counter 142 pulses, are excluded from the stream. Thus, at their expense and there is a compression of the flow of information. The first code of the sequence of equal codes is followed by the code from the counter 142 pulses, and in the 1-8 bits of the output register 146 receives informative signals, the 9th digit of the output register 146 receives an identification signal. When successive equal codes of more than 255 pieces are followed, the decoder 143 with the code 11111111 generates a signal that opens the keys in block 145, resets the register 140 and gives out from the counter 142 pulses in 1-8 bits of the output register 146 the counted code, and in the 9th bit of the output register 146 signal recognition. The bandwidth of the encoder is determined by the response time of the comparison circuit 141/18 ns / plus the response time of the pulse counter 142/12 ns / and is 30 ns, i.e. 30 MB / s Codes of signals R, G, In stereopair in sequential form from blocks 64-66 are received at 1, 2, 3 inputs of a digital information storage device 72, at 4 and 5 inputs of which codes of the first and second sound signals are received. The first and second control inputs of the drive 72 from the 4th and 5th outputs of the synthesizer 53 frequencies receive respectively 1.63 MHz and 108 MHz pulses. The device 73 playback is designed to view the captured material. To reproduce information from the drive 72 of digital information / Fig.2/ to its 3, 4, 5, 6, 7 control inputs are connected, respectively, 1, 2, 3, 4, 5, the control outputs of the device 73 playback. A frequency synthesizer 74 outputs: from the first output, 30 kHz line frequency pulses to the first input of the And 97 element and the first control input of the monitor, from the second - sterepair frequency pulses of 25 Hz to the second input of the And 97 element, to the control input of the IR transmitter 99 and to the third control input of a digital monitor, from the third - 108 MHz clock pulses to the first control inputs of decoders 75, 79, 83 and to the signal input of the sixth key 98, from the fourth - 12 MHz sampling pulses to the second control inputs of decoders 75, 79, 83 and to the first control inputs of blocks 76, 80, 84 r codes, from the fifth - pulses of 1.53 MHz to the signal inputs of the keys 91, 96 and to the first control inputs of the decoders 87, 92, from the sixth pulses of 90 kHz to the second control inputs of the decoders 87, 92 and the first control inputs of blocks 88, 93, from the seventh - pulses of 50 Hz frame rate to the second control input of a digital monitor. After turning on the power from 1 and 2 outputs of block 74, 30 kHz pulse and 25 Hz pulse / which means the scan of the first frame of the stereo pair / are received at the inputs of the And 97 element. The signal from the And 97 element opens the sixth key 98, which passes the 108 MHz clock pulses to the signal inputs of the keys 78, 82, 86. The 108 MHz clock pulses from the keys 78, 82, 86 go respectively to the 3, 4, 5 control inputs of the 72 digital drive information and synchronously issue codes of video signals R, G, B to the information inputs of decoders 75, 79, 83, which perform compressed data recovery by performing operations: determining the number of codes equal in magnitude in the compressed code stream, decrypting it to generate the number of first output signals ode on the number of withdrawn codes under compression, issuing a first code sequence by the number of seized under compression codes.

The operation of the decoder 75/79, 83 /, Fig.11.

Codes of compressed data are received at the information input of the first register 147. The initial state of the keys in block 148 is open, in block 150 is closed, key 153 is open, key 154 is closed. Informative signals are received in 1–8 bits of the first register 147; if there is an identification signal code in the 9th bit, it enters the ninth bit of the register 147. To fill the bits of the first register 147, 108 MHz / 12 MHz clock pulses are sent to its first control input × 9 / synthesizer 74 with the frequency register output 147 3. code outputs the control signal U _vyd 12 MHz with sprinkle the block 74 to the second control input of register 147. When issuing signals from the register 147 with bits 1-8 arrive on input blocks 1-8 148 and 150 keys. Since the keys in block 148 are open, the code passes them and arrives at 1-8 bits of the second register 149, and from it the 8-bit code is issued by the signal U _iss1 from the key 153, which resets the bits of the register 149. So far, 8- bit codes such a process is repeated. With the arrival in the first register of 147 9-bit code, i.e. code number equals the code signal from the ninth register 147 issuing at the discharge of code keys simultaneously closes at block 148, opens the keys at block 150, closes switch 153 and opens switch 154 and closes switch 78 /fig.2/ which interrupts the signal U _vyd / 108 MHz / to the third control input of the information storage device 72, the following codes from the first output of the digital information storage device 72 will not be issued to the decoder register 147. The code of the number of equal codes through the public keys of block 150 enters the subtracting counter 151 pulses. The signal from the key 154 enters the counting input of the subtracting counter 151 / chip 100IE137 with a response time of 10.5 ns [4, p. 428] / and simultaneously enters as a signal U _vy2 to the second control input of the second register 149. The signal U _vy2 generates from the register 149 the code that entered it before this does not reset the register bits when issuing it. 149. Therefore, while the counter 151 is working to subtract / until the code 00000000 / appears in the second register 149, the same code is issued. This code represents the codes seized during data compression at a given point in the stream. Recorded data streams go from the output of decoders. The decoder 152, when the code 00000000 enters it, gives a signal that simultaneously closes the key 154, opens the key 153, closes the keys in block 150, opens the keys in block 148, it also comes from the second control output of the decoder to the first control input of the key 78 and U _from opens the key 78, from the digital information storage 72 the R codes are received again in the decoder 75. Next, the processes, respectively, with the presence or absence of the identification signal in the 9th digit of the code, are repeated, alternating. The bandwidth of the decoder is determined by the response time of the subtraction counter 151 / 10.5 ns / plus the response time of the decoder / 18 ns /. The maximum possible speed of stream restoration is 35 MB / s, which with a margin satisfies the work of the encoder. The recovered code streams enter the code processing units 76, 80, 84, which double the number of samples in a row. Doubling of samples is performed by obtaining intermediate / middle / codes between each passing code and the following one: the previous code and the subsequent code are added and the sum code is divided in half. Each code is used twice: the first time as the next, the second time as the previous, so four registers are used in blocks 76, 80, 84.

The operation of the block 76/80, 84 /, Fig. 12.

With the arrival of the first 12 MHz pulse to trigger 155 from its first output, the signal U _vyd1 simultaneously outputs: from register 159 "code 0" / from one zeros / to adder 165, from register 160 "code 0" to sixth register 163 and through diodes to the second inputs of the adder 165, opens U _{from 1} keys in block 156 / keys in the block by the number of bits 8 / and the registers 158, 159 are filled with the code "code 1". The adder 165 adds the "code 0 + code 0". Registers at issue are reset to zero. Division of the sum code by 2 is performed by shifting the sum code by the least significant bit so that the least significant bit is discarded / as in the division of the decimal number by 10 /. The shift is performed by the corresponding connection of the outputs of the adder 165 to the inputs of the block 164 delay elements:

adder outputs 165 0 one 2 3 four 5 6 7 8 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ adder inputs 164 one 2 3 four 5 6 7 8

/. Процесс сложения занимает 24 нс, следовательно, блок 164 должен задерживать коды с сумматора еще на 17,5 нс /41,5-24/. Первый код №1

идет на выход с блока 164 через 41,5 нс после прихода сигнала U_выд1 в регистра 159, 160. С приходом второго импульса в триггер 155 с его второго выхода сигнал U_выд2 одновременно выдает: с регистра 163 код №2 "код 0", с регистра 158 "код 1" в пятый регистр 162 для задержки кода на 83 нс и через диода в сумматор 165, из регистра 161 "код 0" на вторые входы сумматора 165, открывает ключи в блоке 157 /U_от2/ и регистры 160, 161 заполняются кодом /"код 2". Регистры 162 и 163 предназначены для задержки кодов на 83 нс, в них первая половина времени задержки /41,5 нс/ приходится на время процесса суммирования в сумматоре 165 и время задержки кодов в блоке 164 /24+17,5/, поэтому коды с регистров 162, 163 следуют за кодами с блока 164 через 41,5 нс /24 МГц/. С приходом в сумматор "код 1" и "код 0" идет сложение "код 0 + код 1", при выдаче кода суммы в блок 164 деление на 2, и код №3

идет на выход. С приходом третьего импульса 12 МГц на вход триггера 155 с его первого выхода сигнал U_выд3 одновременно выдает: из регистра 162 код №4 "код 1", из регистра 159 "код 1" в сумматор 165, из регистра 160 "код 2" в регистр 163 и через диоды в сумматор, открывает U_от1 ключи в блоке 156, и регистры 158, 159 заполняются кодом "код 3". Идет сложение в сумматоре "код 1 + код 2", деление на 2, и с выхода блока 164 на выход идет код №5

.Bit 0 means transfer to it when adding codes. As an adder 165, K555IM6 microcircuits were used [4, p. 258] with an addition time of 24 ns. If the samples are doubled from 400 to 800, the code repetition period is 41.5 ns /

/. The addition process takes 24 ns, therefore, block 164 must delay the codes from the adder for another 17.5 ns / 41.5-24 /. The first code number 1

goes to the output from block 164 after 41.5 ns after the signal U _{ext1 arrives} at register 159, 160. With the second pulse _arriving at trigger 155 from its second output, the signal U _exp2 simultaneously outputs: from register 163 code No. 2 "code 0", from register 158 "code 1" to the fifth register 162 for delaying the code for 83 ns and through the diode to the adder 165, from register 161 "code 0" to the second inputs of the adder 165, opens the keys in block 157 / U from ₂ / and the registers 160, 161 are filled with code / "code 2". Registers 162 and 163 are designed to delay codes at 83 ns, in them the first half of the delay time / 41.5 ns / falls on the summation process in the adder 165 and the code delay time in block 164/24 + 17.5 /, therefore, codes with registers 162, 163 follow the codes from block 164 through 41.5 ns / 24 MHz /. With the arrival in the adder "code 1" and "code 0" is the addition of "code 0 + code 1", when issuing the code of the sum in block 164 division by 2, and code No. 3

goes to the exit. With the arrival of the third 12 MHz pulse to the input of the trigger 155 from its first output, the signal U _vyd3 simultaneously outputs: from register 162 code No. 4 "code 1", from register 159 "code 1" to adder 165, from register 160 "code 2" to register 163 and through diodes to the adder, opens U _{from 1} keys in block 156, and registers 158, 159 are filled with code "code 3". There is an addition in the adder "code 1 + code 2", division by 2, and from the output of block 164 to the output is the code number 5

.

идет на выход с блока 164. С приходом пятого и последующих импульсов в триггер 155 процессы повторяются. Выходы блоков 162, 163, 164 поразрядно объединены. С блоков 76, 80, 84 коды с частотой 24 МГц поступают в блоки 77, 81, 85 импульсных усилителей, где сигналы разрядов кода усиливаются, и коды в параллельном виде поступают на соответствующие цифровые входы ДV1 цифрового монитора. В качестве блоков 77, 81, 85 импульсных усилителей применены микросхемы 533АП6 с временем срабатывания 18 нс [4, с.128], каждый блок из 8 импульсных усилителей. На первый, второй и третий управляющие входы цифрового монитора с блока 74 поступают соответственно импульсы частоты строк 30 кГц, импульсы частоты кадров 50 Гц и импульсы стерепар 25 Гц. Разрешение в кадре 480000 элементов /800×600/. Изображение с экрана цифрового монитора /фиг.2/ зрителем воспринимается объемным через ЗД-очки 100. При воспроизведении правого и левого кадров стерепары стекла ЗД-очков поочередно [5, с.558] теряют прозрачность, каждый глаз видит свой кадр: правый глаз - правый, левый глаз - левый кадр, что и дает стереоэффект. Стекла ЗД-очков выполнены по технологии ЖК-ячеек просветного типа, используемые как электронно-управляемые фильтры /затворы/, с приходом импульса 25 Гц на вход ИК-передатчика 99 он излучает ИК-импульс, принимаемый ИК-приемником 101 /фиг.2/, расположенным на оправе ЗД-очков. ИК-приемник выдает управляющий сигнал в ЖК-ячейку левого стекла, затемняя его на 20 мс /длительность кадра/, затем выдает второй управляющий сигнал в ЖК-ячейку правого стекла, затемняя его на 20 мс. Поэтому каждый глаз видит свой кадр.With the arrival of the fourth pulse in trigger 155, the signal U _vy4 from its second output simultaneously outputs: from register 163 code No. 6 "code 2", from register 158 "code 3" to register 162 and through diodes to the adder, from register 161 "code 2 "into the adder 165, opens the keys U from ₂ in block 157, and the registers 160, 161 are filled with the code" code 4 ". Follows the addition of "code 2 + code 3", then division by 2, and code number 7

goes to the exit from block 164. With the arrival of the fifth and subsequent pulses in trigger 155, the processes are repeated. The outputs of blocks 162, 163, 164 are bitwise integrated. From blocks 76, 80, 84, codes with a frequency of 24 MHz are supplied to blocks 77, 81, 85 of pulse amplifiers, where the signals of the bits of the code are amplified, and the codes are sent in parallel to the corresponding digital inputs DV1 of the digital monitor. As blocks 77, 81, 85 of pulse amplifiers, 533AP6 chips were used with a response time of 18 ns [4, p.128], each block of 8 pulse amplifiers. The first, second and third control inputs of the digital monitor from block 74 respectively receive pulses of a frequency of lines of 30 kHz, pulses of a frame frequency of 50 Hz and pulses of a stereo pair of 25 Hz. The resolution in the frame is 480,000 elements / 800 × 600 /. The image from the screen of the digital monitor / Fig.2/ is perceived by the viewer as voluminous through the ZD glasses 100. When playing the right and left frames, the stereo pairs of the glasses of the ZD glasses alternately [5, p.558] lose their transparency, each eye sees its own frame: the right eye - right, left eye - the left frame, which gives a stereo effect. The glasses of the ZD glasses are made using the technology of LCD cells of the translucent type, used as electronically controlled filters / shutters /, with the arrival of a 25 Hz pulse to the input of the IR transmitter 99, it emits an IR pulse received by the IR receiver 101 (Fig. 2/ located on the frame of the ZD glasses. The IR receiver provides a control signal to the LCD cell of the left glass, dimming it for 20 ms / frame duration /, then it outputs a second control signal to the LCD cell of the right glass, dimming it for 20 ms. Therefore, each eye sees its frame.

Pulses of a clock frequency of 1.53 MHz of sound from the keys 91, 96 are fed to the 6 and 7 control inputs of the digital information storage device 72 and give sound codes to the information inputs of decoders 87, 92 from its 4 and 5 outputs. The operation of decoders 87, 92 is similar to that of the decoder 75. 16-bit codes in parallel form from decoders 87, 92 are received in sound signal registers 88, 93, from which they are output by 90 kHz output signals to blocks 89, 94 for generating analog audio signals. Stereo sound is played by speakers 90 and 95.

The operation of the camcorder.

When the power is turned on, a 25 Hz pulse from block 42 / Fig. 1/ opens the key 54. Pulses of a frame frequency of 50 Hz go to the input of trigger 66, the signal from the first output of which opens the key 56, sampling pulses of 12 MHz arrive during the first / right / frame stereo pairs to the clock inputs of the ADC 45-47. Codes R _P , G _P , B _P from the outputs of the ADC 45-47 enter the encoders 58-60, performing digital data compression, and to the inputs of the video detector 71, which forms an image on the LCD display. With the arrival of the second 50 Hz pulse to the input of the trigger 55, the signal from its second output closes the key 56, opens the key 57, which transmits 12 MHz pulses during the second / left / frame to the control inputs of the ADC 48-50. Codes R _L , G _L , V _L from the outputs of the ADC 48-50 enter the encoders 61-63. Codes of the right and left frames sequentially one after another from encoders 58-60, 61-63 through blocks 64-66, converting parallel codes to serial, are fed to 1-3 information inputs of the digital information storage 72. Photoelectric converter 3, the ADC 45-50 form a video mode of 600 _pp × 400 _count × 50 Hz. The audio codes from the ADC 51, 52 enter their encoders 67, 68, which compress the audio information stream, and through blocks 70, 69 enter the information inputs of the digital information storage device 72 at 4 and 5. To reproduce the shot material, 1-5 inputs of the playback device 73 are connected to 1-5 outputs of the drive 72, 3-7 control inputs of the digital information storage 72 are connected to 1-5 control outputs of which, respectively. The signal from the And 97 element opens the key 98 / Fig. 2/, which transmits 108 MHz pulses to the signal inputs of the keys 78, 82, 86 and to the second control inputs of the decoders 75, 79, 83. 108 MHz pulses come from the outputs of the keys 78, 82, 66 to 3, 4, 5 control inputs of the digital information storage device 72 and provide the video signal codes of the right and left frames to decoders 75, 79, 83, which restore the compressed video information streams. Codes from decoders 75, 79, 83 enter the code processing units 76, 80, 84, doubling the number of samples in the lines from 400 to 800. The codes of the right and left frames, alternating, are fed to the digital inputs of a digital monitor reproducing a video mode of 800 × 600 _pages × 50 Hz. The viewer perceives the image through ZD glasses. When playing the right and left frames on the screen of a digital monitor, the glasses of the ZD glasses alternately lose their transparency, and the viewer perceives the image on the screen in bulk. Pulses of 1.53 MHz from the keys 91, 96 are fed to the 6 and 7 control inputs of the digital information storage device 72 and provide sound signal codes to the inputs of the decoders 87, 92. The decoders restore the sound information streams coming into their sound signal registers 88, 93 from which are issued by pulses of 90 kHz to blocks 89, 94 and from them to loudspeakers 90, 95.

The inventive video camera generates, registers and reproduces a stereo image and stereo sound, can be widely demanded by users in a domestic environment.

Information sources

1. Murakhovsky V.I. Computer device. M .: "AST-PRESS book", 2003, p. 546, 328, prototype.

2. On.N. Partala. Video cameras, M.: Science and technology, 2000, p. 179.

3. Fridland M.V., Soshnikov V.G. Automatic control systems in video recording devices, M., 1988, p.118, fig.5.5, p.122, fig.5.10.

4. Digital integrated circuits. Handbook, Minsk, 1991.p.128, 156, 258, 272, fig. 2.190, 279, 428.

5. Kolesnichenko OV, Shishigin I.V. PC hardware. 5th ed., St. Petersburg, 2004, p. 476, 487, 558-566, 489.

Table Specifications Values 3D imaging Stereo Frequency / Frame Rate 25 Hz / 50 Hz Frame / stereo pair duration. 0.02 s / 0.04 s Camera Video Mode: number of rows × number of samples in the lad 600 × 400 line scan / line frequency 15 kHz / 30 kHz scanning lines in a frame progressive without reverse gears video sampling 12 MHz / 600 × 400 × 50 / video coding method linear PCM video coding 255 levels, 8 bits, 2 ⁸ sound sampling 90 kHz sound coding 65536 level, 16 bits, 2 ¹⁶ video bit rate 108 MHz / 12 MHz × 9p / Play stereo pair frequency / frame rate 25 Hz / 50 Hz number of lines per frame / number of samples per line 600/800 frame resolution 480000/800 × 600 / frame format 1.33: 1/800: 600 / image playback digital flat panel monitor.

Claims (1)

Video camera,  containing the first lens  photoelectric converter  first ADC video signal,  digital information storage device and video detector,  characterized in  that a second lens is inserted into it,  located to the left of the first lens and whose optical axis is parallel to the optical axis of the first lens,  series-connected frequency synthesizer,  first key and trigger,  second and third keys,  the signal inputs of which are combined and connected to the first output of the frequency synthesizer,  to the second output of which the signal input of the first key is connected,  the first control input of the second key and the second control input of the third key are combined and connected to the first output of the trigger,  the second control input of the second key and the first control input of the third key are combined and connected to the second output of the trigger,  introduced from the second to sixth ADC video signal,  the first and second ADCs of the sound signal,  the inputs of which are given sound signals,  first to sixth encoders,  from first to third blocks of elements And,  information inputs from the first to the sixth ADC of the video signal are connected respectively to the first to sixth outputs of the photoelectric converter,  the control inputs of the first to third ADCs of the video signal are combined and connected to the output of the second key,  the outputs of the first to third ADCs of the video signal are connected to the inputs of the first to third encoders, respectively, and to the first and third information inputs of the viewfinder,  the first control input of which is connected to the output of the first key,  the second control input is connected to the seventh output of the frequency synthesizer,  the control inputs of the fourth to sixth ADCs of the video signal are combined and connected to the output of the third key,  the outputs of the fourth to sixth ADCs of the video signal are connected to the inputs of the fourth to sixth encoders, respectively  outputs of the first and fourth encoders,  second and fifth encoders,  the third and sixth encoders are bitwise combined and connected to the inputs of the first, respectively  the second and third blocks of elements And,  the control inputs of which are combined and connected to the first output of the frequency synthesizer,  and their outputs are connected to the first,  to the second  the third information inputs of the digital information storage device,  introduced in series connected the first encoder of the sound signal and the first block of elements AND sound signal,  connected in series to the second encoder of the sound signal and the second block of elements AND sound signal,  the inputs of the first and second sound signal encoders are connected to the outputs of the first and second ADCs of the sound signal, respectively  the control inputs of which are combined and connected to the third output of the frequency synthesizer,  control inputs of the first,  the second blocks of elements And the sound signal are combined and connected to the fourth output of the frequency synthesizer,  and the outputs of the first and second blocks of elements And the sound signal are connected respectively to the fourth and fifth information inputs of the digital information storage device,  the first and second control inputs of which are connected respectively to the fourth and fifth outputs of the frequency synthesizer,  a playback device is inserted,  from the first to fifth information inputs of which are connected respectively to the first to fifth outputs of the digital information storage device,  the third to seventh control inputs of which the first to fifth control outputs of the playback device are connected, respectively  the photoelectric transducer contains a series-connected first amplifier and a first piezoelectric deflector with a reflector at the end,  located in the rear focal plane of the first lens,  the first source of positive reference voltage  the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector,  a second source of negative reference voltage,  the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector,  connected in series to a second amplifier and a second piezoelectric deflector,  the free end of which is made of two faces,  located at an appropriate angle to each other,  and each face has a reflector,  the first reflector of the second piezoelectric deflector is optically connected to the reflector of the first piezoelectric deflector,  a third source of positive reference voltage,  the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector,  a fourth source of negative reference voltage,  the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector,  connected in series with a third amplifier and a third piezoelectric deflector with a reflector at the end,  located in the rear focal plane of the second lens and optically connected to the second reflector of the second piezoelectric deflector,  fifth source of positive reference voltage  the output of which is connected to the second inputs of the third amplifier and the third piezoelectric deflector,  sixth source of negative reference voltage,  the output of which is connected to the third inputs of the third amplifier and the third piezoelectric deflector,  contains the first and second dichroic mirrors,  located one after another and against the first reflector of the second piezoelectric deflector,  third and fourth dichroic mirrors,  located one after another and against the second reflector of the second piezoelectric deflector,  first to sixth micro lenses,  first to sixth photodetectors,  first through sixth preamplifiers,  the input window of the first photodetector is optically connected through the first micro lens and the first dichroic mirror with the first reflector of the second piezoelectric deflector,  the input window of the second photodetector is optically connected through the second micro lens and through the first and second dichroic mirrors to the first reflector of the second piezoelectric deflector,  the input window of the third photodetector is optically connected through a third micro lens,  the second dichroic mirror and through the first dichroic mirror with the first reflector of the second piezoelectric deflector,  the input window of the fourth photodetector is optically connected through the fourth micro-lens and the third dichroic mirror to the second reflector of the second piezoelectric deflector,  the input window of the fifth photodetector is optically connected through the fifth micro-lens and through the third and fourth dichroic mirrors to the second reflector of the second piezoelectric deflector,  the input window of the sixth photodetector is optically connected through the sixth micro lens,  a fourth dichroic mirror and through a third dichroic mirror with a second reflector of the second piezoelectric deflector,  the outputs from the first to sixth photodetectors are connected respectively to the inputs from the first to sixth pre-amplifiers,  the outputs of which are respectively the first to sixth outputs of the photovoltaic converter,  line scan unit from series-connected master oscillator,  the input of which is connected to the sixth output of the frequency synthesizer,  and output stage  the output of which is the output of the horizontal scanning unit and is connected in parallel to the first inputs of the first and third amplifiers,  the frame scanning unit of the photoelectric converter includes a series-connected element And,  the inputs of which are the first and second control inputs of the frame scanning unit and are connected respectively to the seventh and eighth outputs of the frequency synthesizer,  master oscillator and summing amplifier,  the second input of which is connected to the corresponding input of the AND element,  the control input of the summing amplifier is connected to the output of the element And,  the output of the summing amplifier is the output of the frame scan unit and is connected to the first input of the second amplifier,  the summing amplifier includes a series-connected pulse counter and a decoder,  first and second keys,  first and second pulse shapers and output amplifier,  the signal inputs of the keys and the counting input of the pulse counter are combined and are the second input of the summing amplifier,  the first input of which is the first input of the output amplifier,  first control input of the first key,  the second control input of the second key and the control input of the pulse counter are combined and are the control input of the summing amplifier,  the second control input of the first key and the first control input of the second key are combined and connected to the output of the decoder,  the output of the first key is connected to the input of the first pulse shaper,  the output of the second key is connected to the input of the second pulse shaper,  the outputs of the pulse shapers are combined and connected to the second input of the output amplifier,  the output of which is the output of the summing amplifier and is connected to the first input of the second amplifier,  the first to sixth ADCs are identical,  each includes a series-connected video amplifier,  whose input is the information input of the ADC,  and a piezoelectric deflector with a reflector at the end,  source of positive reference voltage  negative reference voltage source  the outputs of which are connected respectively to the second and third inputs of the video amplifier and piezoelectric deflector,  emitter from a pulsed LED,  slit diaphragm and micro lens,  series-connected line of multi-element photodetector and encoder,  the outputs of which are the outputs of the ADC,  the control input is the pulse LED input,  input windows of the multi-element photodetector line are optically connected to the emitter through the piezoelectric reflector,  the first and second ADCs of the sound signal are identical,  each includes a series-connected voltage divider,  key block  matching amplifier  sound frequency amplifier and piezoelectric deflector with a reflector at the end,  source of positive reference voltage  negative reference voltage source  the outputs of which are respectively connected to the second and third inputs of the audio frequency amplifier and piezoelectric deflector,  emitter from a pulsed LED,  slit diaphragm and micro lens,  series-connected line of multi-element photodetector,  first decoder,  cipher and register,  the outputs of which are the ADC outputs of the sound signal,  contains a second decoder,  the inputs of which are connected to the outputs of the encoder,  and the outputs are connected to the corresponding inputs of the first decoder and the inputs of the key block,  input windows of the multi-element photodetector line are optically connected to the emitter through the piezoelectric reflector,  ADC input is voltage divider input,  the control input is the pulse LED input,  combined with the control input of the register,  first to sixth encoders are identical,  each includes a series-connected register,  comparison chart  pulse counter and decoder,  and series-connected block of delay elements,  key block and output register,  information input of the encoder are bitwise integrated register inputs,  the first inputs of the comparison circuit and the inputs of the block of delay elements,  the outputs are the outputs of the bits of the output register,  the first output of the comparison circuit is connected to the first control input of the register,  to the counting input of the pulse counter and to the second control input of the key block,  the second and third outputs of the comparison circuit are combined,  the combined output is connected to the second control input of the register,  to the first control input of the key block,  to the first control input of the pulse counter,  to the control input of the output register and to the input of its last (9th) category,  the outputs of the bits of the pulse counter are connected to the inputs of the decoder and through the diodes are connected to the inputs from the first to eighth bits of the output register,  the decoder output is connected to the second control input of the pulse counter and through the diode to the first control input of the key block,  to the first control input of the pulse counter,  to the control input of the output register,  to the input of its last (9th) rank and to the second control input of the register,  the first and second encoders of the sound signal are identical to the first to sixth encoders,  and register  comparison chart  pulse counter  decoder,  delay element block,  the block of keys and the output register in the encoders of the sound signal are made in accordance with the bit depth of the code of the sound signal  the first,  the second and third blocks of AND elements are identical,  each includes the first to ninth elements AND,  the first inputs of which are the inputs of the block,  self-propelled pulse distributor,  from the first to the ninth outputs of which are connected to the second inputs, respectively, from the first to the ninth elements of And,  and the first to ninth OR element of which inputs are connected to the first to ninth AND outputs,  and the output of the OR element is the output of the block,  the control input of which is the input of a self-propelled pulse distributor,  connected to the first output of the frequency synthesizer,  the first and second blocks of elements And the sound signal are identical,  each includes the first through seventeenth AND elements,  the first inputs of which are the inputs of the block and are connected to the outputs of their encoder sound signal,  self-propelled pulse distributor,  the first to seventeenth outputs of which are connected to the second inputs of the first to seventeenth AND elements,  and the OR element,  the inputs of which are connected to the outputs of the elements AND,  and the output is the output of the block,  the control input of which is the input of a self-propelled pulse distributor,  connected to the fourth output of the frequency synthesizer,  the playback device contains a frequency synthesizer,  series-connected element And,  the first and second inputs of which are connected respectively to the first and second outputs of the frequency synthesizer,  and the sixth key,  the signal input of which is connected to the third output of the frequency synthesizer,  contains the video channel R,  including the first key and the first decoder connected in series,  a first code processing unit and a first pulse amplifier unit,  video signal channel G,  including a second key,  and connected in series to a second decoder,  a second code processing unit and a second pulse amplifier unit,  video signal channel B,  including a third key and a third decoder connected in series,  a third block of code processing and a third block of pulse amplifiers,  the information inputs of the first or third decoders are connected respectively to the first,  to the second  the third outputs of the digital information storage device,  the first control inputs of the first to third decoders are combined and connected to the third output of the frequency synthesizer,  the second control inputs of the first to third decoders and the first control inputs of the first to third code processing units are combined and connected to the fourth output of the frequency synthesizer,  the signal inputs from the first to third keys are combined and connected to the output of the sixth key,  the first and second control inputs of the first,  the second and third keys are connected respectively to the second and first control outputs in the first,  second and third decoders,  the output of the first  the second and third keys are connected respectively to the third,  the fourth and fifth control inputs of the digital information storage device,  contains the first channel of sound,  comprising a fourth key and serially connected a first decoder of audio codes,  sound register,  an analog audio signal generating unit and a speaker,  second channel of sound  comprising a fifth key and a second sound code decoder connected in series,  sound register,  an analog audio signal generating unit and a speaker,  information inputs of the first and second sound code decoders are connected respectively to the fourth and fifth outputs of the digital information storage device,  the signal inputs of the fourth and fifth keys and the first control inputs of the first and second decoders of sound codes are combined and connected to the fifth output of the frequency synthesizer,  the second control inputs of the first and second sound code decoders and the first control inputs of the sound signal registers are combined and connected to the sixth output of the frequency synthesizer,  the first and second control inputs of the fourth and fifth keys are connected respectively to the second and first control outputs of the first and second sound code decoders,  the outputs of the fourth and fifth keys are connected respectively to the sixth and seventh control inputs of the digital information storage device,  the outputs of the first  the second and third blocks of pulse amplifiers are connected respectively to the first,  to the second  the third inputs of a digital monitor,  the first,  the second and third control inputs of which are connected respectively to the first,  the seventh and second outputs of the frequency synthesizer,  to the second output of which the input of the IR transmitter is connected,  located on the body of a digital monitor,  against the output window of the IR transmitter when playing the image is the input window of the IR receiver,  fixed on the frame of the ZD glasses,  first to third decoders are identical,  each includes a series-connected first register,  first block of keys and second register,  serially connected second block of keys,  subtracting pulse counter and decoder,  first and second keys,  the information input of the decoder is the information input of the first register,  the first control input is the first control input of the first register,  the second control input is the combined inputs of the second control input of the first register and the signal inputs of the first and second keys,  the outputs of the decoder are the outputs of the bits of the second register,  the first control output is the output of the last bit (9th) of the first register,  the second control output is the decoder output,  the inputs of the second block of keys are connected to the inputs of the first block of keys,  the output of the last (9th) category of the first register is connected to the first control input of the second block of keys and to the second control input of the first block of keys,  to the first control input of the second key and to the second control input of the first key,  the output of the first key is connected to the first control input of the second register,  the output of the second key is connected to the second control input of the second register and to the counting input of the subtracting pulse counter,  the decoder output is connected in parallel to the first control input of the first block of keys,  to the second control input of the second block of keys,  to the first control input of the first key and to the second control input of the second key,  the first and second decoders of sound codes are identical to the first to third decoders,  with the first register,  first and second key blocks,  second register  the subtracting pulse counter and decoder in the decoders of the sound codes are made with bit depth in accordance with the bit depth of the sound signal code,  the first,  the second and third code processing units are identical,  each includes a trigger,  first and second key blocks,  first to fourth registers,  fifth and sixth registers,  delay block  adder and sixteen diodes,  information inputs of the block are bitwise combined inputs of the first and second blocks of keys,  the control input is the trigger input,  the outputs are the bitwise combined outputs of the fifth,  sixth registers and outputs of the delay block,  the information inputs of the first and second registers are bitwise combined and connected to the outputs of the first block of keys,  the outputs of the first register are connected to the inputs of the fifth register and through diodes are connected to the first inputs of the adder,  to which the outputs of the second register are connected,  the information inputs of the third and fourth registers are bitwise combined and connected to the outputs of the second block of keys,  the outputs of the third register are connected to the inputs of the sixth register and through the diodes are connected to the second inputs of the adder,  to which the outputs of the fourth register are connected,  the corresponding outputs of the adder are connected to the corresponding inputs of the delay unit,  the control input of the adder is connected to the input of the trigger,  the first output of which is connected in parallel to the control inputs of the first block of keys,  second  third and fifth registers,  the second trigger output is connected to the control inputs of the second block of keys,  the first  fourth and sixth registers.

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