RU2292664C1 - Digital monitor - Google Patents

Abstract

FIELD: personal computer hardware engineering.

SUBSTANCE: digital monitor contains frequencies synthesizer, three channels, in each of which code processing block, code accumulator and block of impulsive amplifiers are contained, block for modulating radiations, horizontal deflection block, two piezo-deflectors, four sources of supporting voltage, projection objective and lusterless screen. Monitor additionally contains in accordance to invention: infrared transmitter, three-dimensional goggles with infrared receiver in goggles frame, analog-digital converter and row doubling block are introduced to each channel.

EFFECT: creation in digital monitor of conditions for reproduction of stereo effect, increased resolution of frame and increased averaged brightness of image.

12 dwg, 2 tbl

Description

The invention relates to the hardware of a personal computer / PC / and can be used as a monitor in a PC.

The prototype adopted a television receiver from a digital television system [1, p.5], containing a frequency synthesizer, three channels, each of which includes a series-connected code processing unit, a code storage unit and a pulse amplifier unit, a radiation modulation unit, a frequency divider and a unit connected in series horizontal scan from the master oscillator and the output stage, the first amplifier and the first piezoelectric deflector with a reflector at the end, the second amplifier and the second piezoelectric deflector with a reflector at the end, four sources voltage, projection optical system and matte screen. The code processing unit doubles the samples in a row. Code accumulators concentrate frame codes separately for each color signal. The radiation modulation unit performs luminance modulation of the radiation of the emitters at the same time 300 lines, converting digital codes into a change in the brightness of the radiation of 300 emitters according to the code values. One piezoelectric deflector performs horizontal scanning in parallel with 300 lines with repeating them 300 times for the first field of the frame; the second piezoelectric deflector performs an offset by a line step when scanning 300 even lines in the second field of the frame with repeating them 300 times. The image is projected onto the screen by the optical system, enlarging it several times. The disadvantages of the prototype: can not be used as a monitor in a computer, does not create a stereo effect for the viewer to perceive a three-dimensional image.

The purpose of the invention is to reproduce in the monitor the conditions for obtaining a stereo effect for a PC user.

The technical result is to obtain in the inventive monitor the conditions for reproducing a stereo effect and increasing the resolution of the frame. The result is achieved by using a 640 × 480 video mode with a RS video adapter at a frequency of 160 Hz, doubling the number of samples per line to 1280/640 × 2 /, doubling the lines to 960/480 × 2 /, scanning the frame simultaneously with 480 odd and 480 even lines with repeating each their groups for the frame period 48 times. This method gives an increase in the average image brightness by 46080 times / 960 _pages × 48 /. The technical result of the perception of the volumetric image is achieved using ZD glasses with an IR receiver on the rim of the glasses and an IR transmitter on the monitor screen.

From the separate outputs of the computer, the analog video signals R, G, B are fed to 1-3 information inputs of a digital monitor, the operating frequency and the clock pulses of 80 Hz stereo pairs are sent to the first and second control inputs of the monitor from the corresponding outputs of the PC video adapter. Following the sync pulse of the stereo pair, the left frame of the stereo pair follows. The frequency synthesizer, synchronizing along the leading edge of the stereo pair clock and using the operating frequency from the PC, outputs from its outputs a sampling frequency of codes f _d , a double sampling frequency, a line frequency of 76.8 kHz, a frame frequency of 160 Hz and the corresponding frequency of issuing codes f _out 19, 6608 MHz. The analog color signals R, G, B are converted by 1-3 ADCs into 8-bit binary codes of line samples, which, after doubling the samples in a line and doubling the number of lines, go to the code stores, from which they are fed to the code bits in the pulse amplifiers emitters of the radiation modulation unit, where they are converted into three-color radiation modulated by brightness for each line. Radiation of 480 emitters is simultaneously transmitted to the reflector of the piezoelectric deflector, from it to the reflector of the next piezoelectric deflector, which performs horizontal scanning parallel to 480 odd lines, the projection lens projects the image of the odd lines onto the screen. When reverse / right to left / sweep, there is a scan of 480 even lines, an image of even lines is projected on the screen. During the frame period, the scan of odd and even lines is repeated 48 times.

. Частота дискретизации кодов АЦП 49,152 МГц /640_отсч×480_строк×160 Гц/. Длительность строки с АЦП 13,02 мкс

, частота строк 76,8 кГц. Длительность строки на экране 65,1 мкс

. 96 - частота повторов строк в кадре /48×2/, частота строк 15,36 кГц

. Между глазами и экраном размещаются электронно-управляемые ЗД-очки [2, с.558-565], в которых синхронно и синфазно со сменой кадров перекрывается поле зрения тому из глаз, кадр которого отсутствует.6.25 ms frame duration

. The sampling frequency of the ADC codes is 49.152 MHz / 640 _count × 480 _lines × 160 Hz /. ADC Line Length 13.02 μs

, line frequency 76.8 kHz. 65.1 μs line length on screen

. 96 - line repeat frequency per frame / 48 × 2 /, line frequency 15.36 kHz

. Between the eyes and the screen are placed electronically controlled ZD glasses [2, p. 588-565], in which the field of view of that eye, the frame of which is absent, is synchronously and in phase with the change of frames.

The essence of the invention is that in a digital monitor containing a frequency synthesizer, three channels, each of which includes a code processing unit and serially connected code storage unit and a pulse amplifier unit, a radiation modulation unit, a frequency divider and a horizontal scanning unit, a first amplifier and a first piezoelectric deflector with a reflector at the end, a second amplifier and a second piezoelectric deflector with a reflector at the end, four sources of reference voltages, a projection lens and a matte screen, a second frequency divider is introduced, the output of which о connected to the input of the second amplifier, an IR transmitter located above the matte screen, ZD glasses with an IR receiver on the frame of glasses, an ADC and a line doubling unit are introduced into each channel, the inputs of which are connected to the outputs of the code processing unit, and the outputs are connected to code drive inputs.

Functional diagram of the digital monitor in figure 1, the raster and the shape of the control voltage of the scan lines in figure 2, the ADC of the video signal in figure 3, the code processing unit in figure 4, the line doubling unit in figure 5, the first delay block in figure 5. 6, the code store in FIG. 7, the odd / even / frame code store in FIG. 8, the register unit in FIGS. 9 and 10, the radiation modulation unit in FIG. 11, the piezoelectric deflector design in FIG. 12. The digital monitor / Fig. 1/ includes a frequency synthesizer 1, three channels, the first channel contains the first ADC 2, the first code processing unit 5, the first line doubling unit 8, the first code storage unit 11 and the first pulse amplifier unit 14, the second channel contains a second ADC 3, a second code processing unit 6, a second line doubling unit 9, a second code storage unit 12 and a second pulse amplifier unit 15 connected in series, the third channel contains a third ADC 4 connected in series, a third code processing unit 7, a third block to 10 double the lines, the third drive 13 codes and the third block 16 of the pulse amplifiers, includes a block 17 of the modulation of radiation, connected in series with the first frequency divider 18/10: 1 /, the block 19 line scan from a series-connected master oscillator 20 and the output stage 21, the first an amplifier 22 and a first piezoelectric deflector 23 with a reflector at the end, a first source of positive reference voltage 24, a second source of negative reference voltage 25, a second frequency divider 26/10: 1 / connected in series, a second amplifier 27 and a second piezoelectric deflector 28 with a reflector at the end, a third source of positive reference voltage 29, a fourth source of negative reference voltage 30, a projection lens 31, a matte screen 32, an IR transmitter 33 located above the screen 32, an IR receiver 34 on the frame of the ZD glasses 35 .

ADCs 2, 3, 4 are identical, each contains / Fig. 3/ series-connected video amplifier 36 and piezoelectric deflector 37 about a reflector at the end, a source of positive reference voltage 38, a source of negative reference voltage 39, an emitter from a pulsed LED 40, aperture diaphragm 41 and a micro lens 42, the line 43 of the multi-element photodetector and encoder 44, which is the output of the ADC.

Blocks 5, 6, 7 of the code processing are identical, each includes / Fig. 4/ trigger 45, first 46, second 47 key blocks, first 48, second 49, third 50, fourth 51 registers, adder 52, first 53 and second 54 blocks delays and 14 diodes. Blocks 53, 54 perform a code delay of 20 ns.

/. Накопители 11, 12, 13 кодов идентичны /фиг.7/, каждый включает ключ 64, триггер 65, накопитель 66 кодов нечетного кадра /левого/, накопитель 67 кодов четного кадра /правого/. Первым и вторым информационными выходами блоков 11, 12, 13 являются поразрядно объединенные первые 1-7 и вторые 1-7 входы накопителя 66 и 67, подключенные к первому и второму выходам соответственно блоков 8, 9, 10 удвоения строк. Управляющими входами являются: первым - сигнальный вход ключа 64, подключенный к выходу 4 синтезатора 1 частот, вторым - управляющий вход ключа 64, подключенный к второму входу синтезатора 1 частот, третьим - объединенные вторые управляющие входы накопителей 66 и 67, четвертым - объединенные третьи управляющие входы накопителя 66 кодов нечетного кадра и накопителя кодов 67 четного кадра. Третий управляющий вход подключен к выходу 1 синтезатора 1 частот, четвертый подключен к выходу 3 синтезатора 1 частот. Первый управляющий вход накопителя 66 кодов подключен к первому выходу триггера 65, первый управляющий вход накопителя 67 кодов подключен к второму выходу триггера 65. Выходы блоков 66, 67 поразрядно объединены и являются 1-3360 выходами накопителя 11 /12, 13/ кодов, подключены к входам блока 14 /15, 16/ импульсных усилителей. Накопитель 66 кодов нечетного кадра и накопитель 67 кодов четного кадра идентичны /фиг.8/. Каждый включает по числу строк /480/ блоки 68_1-480 регистров. Первым и вторым информационными входами блока 66 /67/ являются первые 1-7 и вторые 1-7 входы, подключенные к выходам 1 и 2 блока 8 /9, 10/ удвоения отрок. Блок 66 производит накопление кодов нечетных /левых/ кадров, блок 67 производит накопление кодов четных /правых/ кадров. Блоки 68_1-480 регистров идентичны /фиг.9 и 10/, каждый включает первый 69, второй 70, третий 71, четвертый 72 ключи, первый 73, второй 74, третий 75, четвертый 76 распределители импульсов, первые семь регистров 77_1-7, первый счетчик 78 импульсов и первый дешифратор 79, вторые семь регистров 80_1-7, второй счетчик 81 импульсов и второй дешифратор 82 и триггер 83. Первым и вторым информационными входами блока 68 регистров являются объединенные поразрядно первые /информационные/ входы разрядов первых семи регистров 77_1-7 и объединенные поразрядно первые /информационные/ входы разрядов вторых семи регистров 80_1-7. Выходы разрядов в каждом регистре объединены и являются 1-7 выходами блока 68 регистров. Управляющих входов четыре: первым являются объединенные первые управляющие входы первого 69 и третьего 71 ключей, подключенные к первому выходу триггера 65 в блоке 11 /фиг.7/, вторым - объединенные сигнальные входы второго 70 и четвертого 72 ключей, подключенные к третьему выходу блока 1, третьим - объединенные сигнальные входы ключей 69 и 71, подключенные к первому выходу блока 1, четвертым - объединенные первый управляющий вход ключа 70, второй управляющий вход ключа 72 и второй выход триггера 83, подключенные через диод к первому управляющему выходу блока 68 ₄₈₀ регистров.Blocks 8, 9, 10 of line doubling / FIG. 5/ are identical, each including a first delay unit 55 and an adder 56 and a second delay unit 57 connected in series. The first delay blocks 55 are identical (Fig. 6/), each includes a series-connected And element 58 and a first key 59, a second key 60, a first 61, a second 62 pulse distributors and seven registers 63 _1-7 , each of 1280 bits. Block 55 delays the codes for a line duration of 13.02 μs /

/. The drives 11, 12, 13 of the codes are identical (Fig. 7/), each includes a key 64, a trigger 65, a drive 66 of codes of an odd frame / left /, a drive 67 of codes of an even frame / right /. The first and second information outputs of blocks 11, 12, 13 are the bitwise combined first 1-7 and second 1-7 inputs of the drive 66 and 67 connected to the first and second outputs, respectively, of line doubling units 8, 9, 10. The control inputs are: the first is the signal input of the key 64 connected to the output 4 of the frequency synthesizer 1, the second is the control input of the key 64 connected to the second input of the frequency synthesizer 1, the third are the combined second control inputs of the drives 66 and 67, the fourth are the combined third control the inputs of the drive 66 codes of the odd frame and the drive codes 67 of the even frame. The third control input is connected to the output 1 of the frequency synthesizer 1, the fourth is connected to the output 3 of the frequency synthesizer 1. The first control input of the drive 66 codes is connected to the first output of the trigger 65, the first control input of the drive 67 codes is connected to the second output of the trigger 65. The outputs of the blocks 66, 67 are bitwise integrated and are 1-3360 outputs of the drive 11/12, 13 / codes connected to the inputs of the block 14/15, 16 / pulse amplifiers. The accumulator 66 codes of the odd frame and the accumulator 67 codes of the even frame are identical (Fig. 8/). Each includes the number of lines / 480 / blocks 68 _1-480 registers. The first and second information inputs of the block 66/67 / are the first 1-7 and second 1-7 inputs connected to the outputs 1 and 2 of the block 8/9, 10 / doubling the lad. Block 66 produces the accumulation of codes of odd / left / frames, block 67 produces the accumulation of codes of even / right / frames. Blocks 68 _1-480 registers are identical / 9 and 10 /, each includes the first 69, second 70, third 71, fourth 72 keys, the first 73, second 74, third 75, fourth 76 pulse distributors, the first seven registers 77 _{1- 7} , the first pulse counter 78 and the first decoder 79, the second seven registers 80 _1-7 , the second pulse counter 81 and the second decoder 82 and the trigger 83. The first and second information inputs of the register block 68 are the first / information / bit inputs of the first seven registers 77 _1-7 and combined bitwise first / informational / the inputs of the bits of the second seven registers 80 _1-7 . The outputs of the bits in each register are combined and are 1-7 outputs of a block of 68 registers. There are four control inputs: the first is the combined first control inputs of the first 69 and third 71 keys connected to the first output of trigger 65 in block 11 / Fig. 7/, the second are the combined signal inputs of the second 70 and fourth 72 keys connected to the third output of block 1 , the third - the combined signal inputs of the keys 69 and 71 connected to the first output of block 1, the fourth - the combined first control input of the key 70, the second control input of the key 72 and the second output of the trigger 83, connected through the diode to the first control output of the block approx. _68,480 registers.

Block 17 modulation of radiation / 11 / is made of 480 channels, each includes sequentially arranged emitter 84 of the three primary colors R, G, B, micro-lens 85 and the focusing cone of the fiber 86 / fokon / [3, p.77]. The inputs of block 17 are the inputs of emitters 84 _1-480 , connected to the outputs of blocks 14, 15, 16 of pulse amplifiers, the outputs are the radiation of 480 output windows of the focons 86 _1-480 . Micro-lenses 85 introduce radiation from emitters 84 into the input windows of the focons 86. 480 focons form a vertical ruler, and their output windows are formed on a piezoelectric reflector 28/11/480 color circles, each 0.02 mm in diameter. The exit windows of the foci 86 are arranged vertically in increments of 0.02 mm in diameter, so the projections of the circles on the piezoelectric reflector 28 reflector are arranged in increments of 0.02 mm. When scanning 480 lines from left to right (Fig. 2/), 86 circles of radiation of odd lines of a raster are projected by focons on the reflector of piezoelectric deflector 28; when scanning lines from right to left, the reflector of piezoelectric deflector 28 is shifted by a step of 0.02 by the control signal from block 27 / Fig. 1/ mm with a downward slope, and the circles of radiation of even lines are projected by focons in the intervals between circles from odd lines / Fig.2/. The length of the reflector of the piezoelectric deflector 28 is 19.2 mm / 480 × 0.02 mm /. The radiating plane of the emitter 84 is located in the rear focal plane of the lens 85, in the front focal plane of which the input window of the focal plane 86 is located. The radiating sides of the emitters 84 are connected optically to the reflector of the first piezoelectric deflector 23 through the micro-lenses 85, foci 86, and the reflector of the piezoelectric deflector 23. Each emitter is an array of 21 LEDs. The matrix consists of 7 red LEDs, 7 - green and 7 - blue. The free end face with the reflector of the piezoelectric deflector 28 makes oscillatory movements with an amplitude of 0.02 mm in the control pulse from the second amplifier 27, which generates control signals in amplitude and duration, the frequency of the control signals is 7.68 kHz. Block 26 divides the frequency of 76.8 kHz 10: 1, 7.68 kHz pulses of duration equal to the line duration of 65.1 μs / meander waveform / are received at the input of amplifier 27. The piezoelectric deflectors 23 and 28 are identical (Fig. 12/), they are end faces of two bimorph piezoelectric plates and a light reflector at the free end. Structurally made [4, p.118] from the first 87 and second 88 piezoelectric plates, the inner electrode 89, the first 90 and the second 91 external electrodes, one end of the piezoelectric plates is rigidly fixed in the holder 92, a reflector 93 is fixed to the free end. The piezoelectric deflector 23 performs horizontal scanning 480 lines at a time. A frequency divider 18 performs a frequency division of 76.8 kHz 10: 1. The input of the master oscillator 20 in block 16 receives pulses of 7.68 kHz. Block 20 generates control rectangular pulses with a period of two lines / 65.1 μs × 2 / 130.2 μs, which enter the output stage 21, which generates a triangular control voltage (Fig. 2/ with a period of 130.2 μs, supplied to the input of the amplifier 22, amplifying the control voltage to the required value, which is supplied to the internal electrode 89 of the piezoelectric deflector 23 / Fig.12/. Corresponding reference voltages are supplied to external electrodes 90, 91 from the first 24 and second 25 sources of reference voltages, the end face of the piezoelectric deflector 23 with a reflector comes into vibrational motion [4, p.122] with a frequency of 7.68 kHz and scans an odd 460 segment from left to right and 480 even lines when moving from right to left / Fig.2/. Over a 6.25 ms frame period, the piezo deflector 23 performs 96 repeats of scans in parallel to 480 lines: 48 scans from left to right of odd lines and 48 scans from right to left of even lines / 65.1 μs × 96 = 6.25 ms /. The reflector of the piezoelectric deflector 23 is located in the rear focal plane of the projection lens 31, which is wide-angle to reduce the distance to the screen. The matte screen 32 is located in the external focal plane of the projection lens 31 projecting onto the screen 32 images of sequentially left and right frames, the image from the screen is perceived by the viewer as surround through the ZD glasses 35 [2, p. 588-563, 565]. When playing sequentially the left and right frames, the glasses of the ZD glasses alternately lose transparency, each eye sees only its own frame, which gives a stereo effect. The glasses of the ZD glasses are made using the technology of LCD cells of the translucent type, used as electronically controlled filters / shutters /. With the arrival of an 80 Hz stereo clock sync pulse to the IR transmitter 33, it emits an IR pulse of 6.25 ms duration, the frame duration received by the IR receiver 34 / Fig. 1/, located on the frame of the ZD glasses. The IR receiver 34 provides a control signal to the LCD cell of the right glass, dimming it by 6.25 ms, then it outputs a second control signal to the LCD cell of the left glass, dimming its transparency by 6.25 ms. Each eye sees its frame. The transparency of the LCD cells in the open state is less than 100%, hence the need to increase the brightness of the image on the screen 32. For this purpose, the frame scan on the screen is simultaneously used in 480 lines with a repeat of 96 times, which allows you to increase the brightness of the image for the viewer's eye by 46080 times / 960 _pages × 48 /. The sampling frequency of the ADC codes 2, 3, 4 is:

480 _lines × 640 _counts × 160 Hz = 49.152 MHz.

where: 160 Hz - frame rate / 80 left + 80 right /,

640 - the number of samples per line in video mode

640 × 480 × 160.

From the video adapter PC, f _{P the} operating frequency is supplied to the first input of the monitor unit 1, the clock pulses of the stereo pair 80 Hz are sent to the second input of the monitor unit 1. A frequency synthesizer 1 generates: from the first output, sampling pulses of 49.152 MHz coming into three ADCs and blocks 5, 6, 7 / input 1 /, from the second output - pulses of doubled sampling frequency 98.304 MHz into blocks 8, 9, 10 / input 1 / , from the third - U _output signals to blocks 11, 12, 13 / input 4 / 19.6608 MHz, from the fourth - frame pulses 160 Hz to blocks 11, 12, 13 / input 1 /, from the fifth output - pulses, frequency 76 , 8 kHz to blocks 8, 9, 10 / input 3 /, to block 18 and 26. The analog video signals R, G, B from the video adapter PC sequentially left and right frames are fed to 1, 2, 3 information inputs of a digital monitor and from data inputs respectively to the ADC 2, ADC 3, ADC 4. The ADC 2, 3, 4, convert the analog color signals into 8-bit binary codes with a sampling frequency of 49.152 MHz which are supplied to the control input of the ADC pulse / LED / 3. From the ADC outputs, codes of video signals in parallel form from 1 to 7 bits / low 8 bits are omitted / fed to the information 1-7 inputs of blocks 5, 6, 7. respectively. The output of the eighth bit of the code is not used due to its low significance / 0.39% at radiation. The ADCs have one conversion principle, which consists in scanning the beam (Fig. 3/) from the pulsed LED 40 by the piezoelectric deflector 37 reflector along the plane of the entrance pupils of the photodetectors of line 43, in which the light signal is converted into an electric signal that excites the corresponding encoder bus 44, which outputs an 8-bit instantaneous code input signal values in parallel. The conversion is performed at a frequency of 49.152 MHz. The source of radiation is a pulsed LED with a response time of up to 20 ns. Line 43 contains 255 photodetectors for encoding a video signal with an 8-bit code. Photodetectors are avalanche photodiodes of the APD with a response time of 10 ns. The encoder is a K155IV1 chip with a response time of 20 ns [5, p.231]. The encoder 44 generates codes c 00000001 through 11111111. The first photodetector of line 43 corresponds to the code 00000001, the second to the code 00000010, the third to the code 00000011, etc., the 255th to the code 11111111. The codes from the ADC encoder are received in parallel or without low category / to the information input of block 5/6, 7 / code processing / Fig. 4/, and in block 5 to the information inputs of block 46 keys. Block 5 doubles the samples in a row from 640 to 1280.

Doubling of samples is carried out by obtaining codes of intermediate / average / samples between each past and subsequent samples: in the block, the previous code is added with the subsequent one and the amount is divided in half. Each code is used twice: the first time as the next, the second time as the previous, so block 5 has four registers 48, 49, 50, 51. With the arrival of the first pulse of 49.152 MHz to the input of trigger 45, pulse U _vyd1 opens the keys in block 46, gives " code 0 "from the second register 49 to the first inputs of the adder 52 and" code 0 "from the register 50 to the delay unit 54 and through diodes to the second inputs of the adder 52. And the registers 48, 49 are filled with the first code" code 1 ". The adder 52 performs the addition of codes, made of K500IM180 microcircuits [5, p.440] with an addition time of 10 ns. At the end of the addition, the adder 52 is reset to zero by the pulse U ₀ , it also gives the sum code to the output, the sum code is divided by shifting the code by one bit so that the least significant bit of the sum code is discarded. A shift by one bit is performed by the corresponding connection of the outputs of the bits of the adder to the outputs of the block 52 itself:

, это время соответствует времени сложения кодов сумматором 52. По истечении 10 нс сложения с выхода блока 52 следует код №1

.Bit 0 means transfer to the high bit when the sum of codes. After doubling the samples in a row from 640 to 1280, the period of the codes is 10 ns

, this time corresponds to the time of addition of codes by the adder 52. After 10 ns of addition from the output of block 52, code No. 1 follows

.

After 10 ns, code No. 1 is followed by a code from block 54 delays code No. 2, this is ″ code 0 ″. Blocks 53 and 54 delay the codes by 20 ns.

следует на выход. Через 10 нс за ним следует с блока 53 код №4 "код 1". С приходом третьего импульса в триггер 45 сигнал U_выд3 /он же U_выд1/ с первого выхода триггера открывает ключи в блоке 46, выдает "код 1" с регистра 49 в сумматор 52, выдает "код 2" с регистра 50 в блок 54 задержек и через диоды в сумматор. Регистры 48, 49 заполняются кодом "код 3". Идет сложение и деление, и код №5

следует на выход. Через 10 нс за ним с блока 54 идет код №6 ″код 2″. С приходом 4-го импульса в триггер 45, сигнал U_выд4 /он же U_выд2/ с второго выхода триггера открывает ключа в блоке 47, выдает "код 2" с регистра 51, "код 3" с регистра 48 в блок 53 задержек и через диоды в сумматор 52. Регистры 50, 51 заполняются кодом "код 4". Идет сложение и деление, и код №7

следует на выход, за ним через 10 нс следует с блока 53 код №8 ″код 3″. С приходом 5-го импульса и последующих в триггер 45 процессы повторяются. Выходы сумматора 52 и блоков 53, 54 задержек поразрядно объединены и являются выходом блока 5. С выхода блока 5 коды в параллельном виде поступают на входы первого блока 55 задержек в блоке 8, 9, 10 удвоения строк, на входы второго блока 57 задержек и на первые входы сумматора 56. Блок 55 выполняет задержку кодов строки на длительность строки /13,02 мкс/ и участвует в формировании отсчетов промежуточных строк. Так как развертка нечетных строк и четных в растре идет встречно /фиг.6/, то для получения нечетных промежуточных строк необходимо выдавать коды в сумматор 56 в последовательности с последнего кода /1280-го/ в строке к первому, а при получении четных промежуточных строк выдавать коды с блока 55, начиная с первого кода строки к последнему, при развертке первой строки растра в блоке 55 открывается первый ключ 59 /фиг.6/, импульсы двойной частоты дискретизации 98,304 МГц поступают в первый распределитель 61 импульсов, выдающий тактовые импульсы с 1-го по 1280 последовательности на первые управляющие входы, начиная с первых разрядов регистров 63_1-7 к 1280 разрядам, при развертке первой строки кадра регистры 63_1-7 заполняются кодами первой строки: первые разряды кодов поступают в регистр 63₁, вторые разряды кодов поступают в регистр 63₂, третьи разряды кодов поступают в регистр 63₃..., седьмые разряды кодов поступают в регистр 63₇. Импульс с последнего 1280-го выхода блока 61 закрывает ключ 59, открывает ключ 60. На вход второго распределителя 62 импульсов поступают импульсы 98,304 МГц. Выходы с распределителя 62 импульсов подключены к первым управляющим входам разрядов регистров 63_1-7 в обратном порядке: первый выход подключен к последнему 1280-м разрядам, а последний выход /1280/ подключен к первым разрядам регистров 63_1-7. При развертке второй строки кадра импульсы с выходов второго распределителя 62 импульсов выдают на вторые входы сумматора 56 коды задержанной первой строки в последовательности с 1280 кода к первому, соответственно следованию отсчетов при развертке второй текущей строки кадра. Сумматор 56 формирует первую промежуточную строку. Освобождающиеся разряды регистров 63_1-7, заполняются кодами отсчетов второй /текущей/ строки в порядке с 1280 кода к 1-у. Импульс с последнего выхода /1280/ распределителя 62 закрывает ключ 60 и открывает ключ 59. Следует развертка третьей строки /текущей/, при которой коды второй строки выдаются из регистров 63 в сумматор 56, начиная с 1-го кода к 1280-у. Сумматор 56 формирует /фиг.5/ вторую промежуточную строку. Далее процессы повторяются. Коды с выходов сумматоров 56 блоков 8, 9, 10 являются кодами 640 промежуточных строк. Вторые блоки задержек 57 в блоках 8, 9, 10 выполняют задержку кодов текущих строк на 10 нс, на время срабатывания сумматоров 56, чтобы коды текущих строк с блока 57 и коды промежуточных строк с блока 56 приходили на входы накопителей 11, 12, 13 кодов синхронно и синфазно.The first half of the delay / 10 ns / is the addition in the adder 52, the second half of the delay / 10 ns / is the period of the codes after doubling the samples. With the arrival of the second pulse in trigger 45, the signal U _out2 from the second output of the trigger opens the keys in block 47, issues a “code 0” from register 51 to the adder and ″ code 1 ″ from register 48 to delay units 53 and through diodes to adder 52. Registers 50 and 51 are filled with the code ″ code 2 ″. It follows the addition, dividing the amount code in half, and code number 3

should exit. After 10 ns, it follows from block 53 the code No. 4 "code 1". With the arrival of the third pulse in trigger 45, the signal U _out3 / also U _out1 / from the first trigger output opens the keys in block 46, issues a "code 1" from register 49 to the adder 52, gives a "code 2" from register 50 to the delay block 54 and through the diodes to the adder. Registers 48, 49 are filled with the code "code 3". There is addition and division, and code No. 5

should exit. After 10 ns, code 6 ″ code 2 ″ follows it from block 54. With the arrival of the 4th pulse in trigger 45, the signal U _out4 / also U _out2 / from the second trigger output opens the key in block 47, gives "code 2" from register 51, "code 3" from register 48 to delay block 53 and through diodes to the adder 52. Registers 50, 51 are filled with the code "code 4". There is addition and division, and code number 7

follows the exit, after 10 ns it follows from block 53 code No. 8 ″ code 3 ″. With the arrival of the 5th pulse and subsequent to trigger 45, the processes are repeated. The outputs of the adder 52 and the delay blocks 53, 54 are bitwise combined and are the output of block 5. From the output of block 5, the codes are sent in parallel to the inputs of the first block of 55 delays in block 8, 9, 10 of line doubling, to the inputs of the second block of 57 delays and the first inputs of the adder 56. Block 55 delays the line codes by the line length / 13.02 μs / and participates in the formation of samples of intermediate lines. Since the scanning of odd lines and even lines in the raster is counter-active / Fig.6/, to obtain odd intermediate lines, it is necessary to issue codes to the adder 56 in the sequence from the last code / 1280th / in the line to the first, and when receiving even intermediate lines give codes from block 55, starting from the first code of the line to the last, when scanning the first line of the raster in block 55, the first key 59 / Fig.6/ opens, pulses of the double sampling frequency 98.304 MHz go to the first distributor 61 pulses, issuing clock pulses from 1 to 1280 The sequence for the first control inputs, from the first 63 bits of the register 1280 discharges to _1-7, when scanning the first row of the frame 63 registers _1-7 are filled with the first line codes: the first level code received into the register 63 _1, the second level code received into the register 63 ₂ , the third bits of the codes go to register 63 ₃ ..., the seventh bits of the codes go to register 63 ₇ . The pulse from the last 1280th output of block 61 closes the key 59, opens the key 60. 98.304 MHz pulses arrive at the input of the second pulse distributor 62. The outputs from the distributor 62 pulses are connected to the first control inputs of the bits of the registers 63 _1-7 in the reverse order: the first output is connected to the last 1280-m bits, and the last output / 1280 / is connected to the first bits of the registers 63 _1-7 . When scanning the second line of the frame, pulses from the outputs of the second pulse distributor 62 provide the second inputs of the adder 56 with the codes of the delayed first line in the sequence from 1280 to the first code, respectively, following the samples when the second current line of the frame is scanned. The adder 56 forms the first intermediate line. The freed bits of the registers 63 _1-7 are filled with the codes of samples of the second / current / line in the order from 1280 code to the 1st. The pulse from the last output / 1280 / of the distributor 62 closes the key 60 and opens the key 59. There follows a scan of the third line / current /, in which the codes of the second line are issued from registers 63 to the adder 56, starting from the 1st code to 1280. Adder 56 forms / FIG. 5/ a second intermediate line. Next, the processes are repeated. The codes from the outputs of the adders 56 blocks 8, 9, 10 are codes 640 intermediate lines. The second delay blocks 57 in blocks 8, 9, 10 delay the codes of the current lines by 10 ns, for the time of operation of the adders 56, so that the codes of the current lines from block 57 and the codes of intermediate lines from block 56 arrive at the inputs of codes 11, 12, 13 synchronously and in phase.

The operation of drives 11, 12, 13 codes / Fig. 7, 8 /.

When the first frame is scanned, the stereo pair clock from the second control input of the digital monitor opens the key 64 / in the drive 11/12, 13 / of codes for the duration of the entire operation process / and the frame pulse / 160 Hz / belonging to the left frame is fed to the trigger input 65, s the first output of which he launches the drive 66 codes of an odd frame. When the second frame pulse, which is the pulse of the right frame, arrives at the trigger 65, the signal from the second output of the trigger 65 starts the drive 67 of the codes of the even frame.

In block 66, the codes of each odd frame / left / are concentrated, in block 67, the codes of each even frame are concentrated, i.e. right. Blocks 66, 67 each / Fig. 8, 9 / includes 480 blocks 68 _1-480 registers, which, in turn, each contains the first seven registers 77 _1-7 and the second seven registers 80 _1-7 . In the first period of the frame, block 66 accumulates codes of 960 lines of the first frame, in the second period of the frame, codes are received from all blocks 68 of _{1-480 /} Fig. ₈ / simultaneously 480 odd lines and then 480 even lines, which is repeated 48 times each others. At the same time / in the period of the second frame / block 67 accumulates codes 960 lines of the second frame / right /. In the third period of the frame, codes are issued from block 67, and codes of 960 lines of the third frame are accumulated by block 66, and so alternating, the process repeats.

, 96 - частота повторения строк. Делитель 18 частоты выполняет деление 10:1 частоты 76,8 кГц. На вход задающего генератора 20 /фиг.1/ поступает частота 7,68 кГц. Развертка всех строк выполняется за кадр 96 раз: 48 раз слева направо и 48 раз справа налево, повтор по 48 раз задается счетчиками 78, 81 импульсов и дешифраторами 79, 82. В конце каждой строки сигнал с 1280 выхода блока 74 /76/ в качестве счетного импульса поступает в счетчик 78 /81/. После 48 разверток счетчик формирует код 110000, который дешифрируется дешифратором 79, 82, выходной сигнал с дешифратора обнуляет разряды регистров 77, 80, подготавливая их к заполнению кодами следующего кадра. Смену последовательности выдачи кодов от строки к строке задает триггер 83. Вход его через диоды подключен к 1280-м выходам блоков 74, 76. Первый выход триггера 83 подключен к второму управляющему входу ключа 70 и первому управляющему входу ключа 72, второй выход триггера подключен к первому управляющему входу ключа 70 и к второму управляющему входу ключа 72. Каждый накопитель 11, 12, 13 кодов выдает в параллельном виде коды 480 строк с 1-3360 выходов /480×7/. Коды с блока 11 поступают в блок 14 импульсных усилителей, с блока 12 в блок 15, с блока 13 в блок 16 импульсных усилителей. Каждый из блоков импульсных усилителей включает по 3360 импульсных усилителей с временем срабатывания до 10 нс К531АП4П [5, с.128]. Соответствующие выходы блоков 14, 15, 16 подключены к входам своих излучателей в блоке 17 модуляции излучений /фиг.1/. Каждый излучатель 84 включает 21 светодиод, из которых 7 - красного излучения, 7 - зеленого и 7 - синего излучения. Для излучения светодиод запитывается импульсным сигналом со своего импульсного усилителя. 480 излучателей содержат 10080 светодиодов /480×21/. Исключение 8-го разряда из кодов ввиду его весовой незначительности 0,39% /табл.1/ позволяет сократить в блоках 14, 15, 16, 1440 штук импульсных усилителей /480×3/, в блоке 17 сократить 1440 светодиодов /480×3/ и определенное число регистров в блоках 68_1-480. Блок 17 выполняет яркостную модуляцию излучений 480-ю излучателями 84 /фиг.11/, в которых применяются светодиоды типа HL МР компании "Хьюлетт-паккард" [6, с.71]. Для красного излучения применяются светодиоды HL MP-AL00 с силой света 0,4 кд, длиной волны 0,56 мкм при токе 0,02 A [6, c.71], для зеленого - светодиоды HL MP-АМ00 с силой света 0,8 кд, длиной волны 0,526 мкм при токе 0,02 А, для синего излучения светодиоды HL MP-AB00 с силой света 0,3 кд, длиной волны 0,475 мкм при токе 0,02 А. Яркостная модуляция излучений выполняется включением на излучение числа светодиодов в излучателе 84 соответственно весу разряда в коде по таблице 1.Blocks 68 registers work as follows. All keys of blocks 68 in the initial state are closed. With the arrival of the trigger 65 (Fig. 7/) of the first frame pulse / left frame / from the 1st output of trigger 65, the pulse opens the first key 69 / Fig. 9/ and the third key 71, which pass the frequency of 49.152 MHz to the distributors 73 and 75 pulses. From the outputs of these blocks, the clock signals U _{t are} sequentially fed to the first control inputs of the bits of the resistors 77 _1-7 and 80 _1-7 . The information / first / inputs of which are received by the codes of the line codes from block 8/9, 10 /, and the codes from the first output of block 8 enter the bits of the registers 77, and the codes from the second output of the block 8/9, 10 / go into the bits of the registers 80 _1-7 , i.e. registers 77 are filled with codes of current lines from block 57, and registers 80 are filled with codes of intermediate lines from block 56. At the end of the line period, registers 77 and 80 are filled with 1280 codes of the first line. The pulse from the 1280th output of block 73 closes the key 69 and is the first control output / Fig. 9/ to the next block 68 ₂ , the signal of which opens the same keys 69, 71 in the second block 68 _{2 /} Fig. 10/ and it follows identical process of filling in the codes of the second line of registers 77 _1-7 , 80 _1-7 . Similarly, codes 3 ... 960 are filled in with lines of registers 77, 80 in blocks 68 _3-480 . As a result, block 66 focuses codes 960 lines of the first frame. With the arrival of the trigger 65 (Fig. 7/) of the second frame pulse / right frame / pulse from the second output of trigger 65 opens the keys 69, 71 in block 68 of the drive 67 of the even-frame / right / code codes /, and identical processes of accumulation of codes 960 are going on in it lines of the right frame of the stereo pair. At the same time, the control signal from the control output 1 of block 68 ₄₈₀ in the drive 66 / Fig. 8/ enters in parallel to the fourth control inputs of all blocks 68 _1-480 and opens the keys 70, 72 in them, which are passed to the inputs of the distributors 74, 76 pulse signals U _vyd 19.6608 MHz. The outputs of block 74 are connected to the second control inputs of the bits of the registers 77 _1-7 in the sequence from 1 to 1280: the first output to the second control inputs of the first bits of the registers 77, the last output / 1280 / to the second control inputs of the last bits of the registers 77. Scan 480 odd lines goes from left to right / Fig.2/, the codes are issued simultaneously from registers 77 _{1-7 of} all 480 blocks 68 / Fig. 8/. When the piezoelectric reflector reflector 23 is rotated backward from right to left / there is a scan of 460 even lines, codes are issued in parallel with registers 80 _{1-7 of} all 480 blocks 68 _{1-480 /} Fig. ₈ /. And the codes from the registers 80 are issued, starting from the 1280th bits of the registers to the 1st bits, and the outputs of the distributor 76 pulses are connected to the second control inputs of the bits of the registers 80 _1-7 in the reverse order: the first output is connected to the last bits / 1280 /, and the last output is connected to the first bits of the registers 80 / Fig.9, 10 /. During the oscillation period, the piezoelectric deflector 23 scans two lines: the first is odd when scanning from left to right, the second is even when scanning from right to left. Duration of lessons 65.1 μs

, 96 - repetition rate of lines. A frequency divider 18 performs a 10: 1 division of a frequency of 76.8 kHz. At the input of the master oscillator 20/1 / receives a frequency of 7.68 kHz. All lines are scanned 96 times per frame: 48 times from left to right and 48 times from right to left, a repeat of 48 times is set by counters 78, 81 pulses and decoders 79, 82. At the end of each line, the signal from the 1280 output of the block 74/76 / as counting pulse enters the counter 78/81 /. After 48 sweeps, the counter generates a code 110000, which is decoded by the decoder 79, 82, the output signal from the decoder resets the bits of the registers 77, 80, preparing them for filling with the codes for the next frame. The trigger 83 sets the sequence of issuing codes from line to line. Its input through diodes is connected to the 1280th outputs of blocks 74, 76. The first output of trigger 83 is connected to the second control input of key 70 and the first control input of key 72, the second trigger output is connected to the first control input of the key 70 and the second control input of the key 72. Each drive 11, 12, 13 codes gives in parallel a code of 480 lines from 1-3360 outputs / 480 × 7 /. Codes from block 11 enter block 14 of the pulse amplifiers, from block 12 to block 15, from block 13 to block 16 of pulse amplifiers. Each of the blocks of pulse amplifiers includes 3360 pulse amplifiers with a response time of up to 10 ns K531AP4P [5, p.128]. The corresponding outputs of the blocks 14, 15, 16 are connected to the inputs of their emitters in the block 17 of the modulation of radiation / 1 /. Each emitter 84 includes 21 LEDs, of which 7 are red radiation, 7 are green and 7 are blue radiation. For radiation, the LED is fed by a pulse signal from its pulse amplifier. 480 emitters contain 10,080 LEDs / 480 × 21 /. The exclusion of the 8th category from the codes, due to its weight insignificance of 0.39% / table 1/, allows reducing in units 14, 15, 16, 1440 pieces of pulse amplifiers / 480 × 3 /, in block 17 reducing 1440 LEDs / 480 × 3 / and a certain number of registers in blocks 68 _1-480 . Block 17 performs the brightness modulation of emissions by the 480th emitters 84 (Fig. 11/), in which HL MP LEDs of the Hewlett-Packard company are used [6, p. 71]. For red radiation, HL MP-AL00 LEDs with a light intensity of 0.4 cd, a wavelength of 0.56 μm at a current of 0.02 A are used [6, p. 71], for green radiation, HL MP-AM00 LEDs with a light intensity of 0, 8 cd, wavelength 0.526 μm at a current of 0.02 A, for blue radiation LEDs HL MP-AB00 with a light intensity of 0.3 cd, wavelength 0.475 μm at a current of 0.02 A. Luminance modulation of radiation is performed by switching on the number of LEDs on the radiation in the emitter 84, respectively, the weight of the discharge in the code according to table 1.

The total radiation of the LEDs of three colors R, G, B from the emitter 84 is mixed during focusing by the lens 85 / Fig. 11/ and introduced into the input window of the focon 86, which outputs the radiation in the form of a circle with a diameter of 0.02 mm

Table 1 Discharge number in code one 2 3 four 5 6 7 8 senior level low order LEDs per discharge one one one one one one one - Multiplicity of the filter - 2 ^x 4 ^x 8 ^x 16 ^x 32 ^x 64 ^x 1128 ^x The weight of the discharge in the code, in% fifty% 25% 12.5% 6.25% 3.1% 1.57% 0.78% 0.39%

480 emitters give 28,480 circles on the piezoelectric reflector. The brightness, saturation and hue of the resulting color of the circle on the reflector is determined by the total energy and the mutual ratio of the three colors. The total luminous intensity of one emitter, given that the LEDs of all colors have a light intensity of 0.3 cd / blue LED /, is:

3 × 0.3 cd / 1 + 0.5 + 0.25 + 0.125 + 0.0625 + 0.03125 + 0.0156 / = 0.9 cd × 1.98 = 1.782 cd.

where: 3 - the number of colors in the emitter,

1 ... 0,0156 - coefficients of 1-7 binary digits of the code.

The total luminous intensity from 480 emitters: 1,782 cd × 480 = 855.36 cd.

With 96 horizontal line repeats per frame:

855 cd × 96 = 82,080 cd.

Taking into account losses during the projection from the emitters to the screen 32, the averaged maximum possible radiation power is 20 times: 820 × 80 cd: 20 = 4104 cd.

The brightness of the image on the screen 32 depends on its size, i.e. remoteness of the screen, taking the magnification of the image magnification by the projection lens 31 by 10 times, the screen will be:

horizontal 10 · / 0.04 mm × 1280 _count / = 512 mm,

vertical 10 · / 0.04 mm × 960 _lines / = 384 mm,

diagonally 640 mm or 25 inches. 0.04 mm resolution element on the piezoelectric reflector 23. The perception of a three-dimensional image on a 25 ″ screen with an image emission power of 4104 cd will create good satisfaction for the individual PC user with the equipment. Technical characteristics of the inventive digital monitor in table 2.

The work of a digital monitor. The analog video signals of the three light signals of the left and right frames of the stereo pair come from the PC video adapter separately to 1-3 information inputs of the monitor, to the 1 and 2 control inputs of which come from the PC operating frequency / input 1 / and sync pulses of stereo pairs / 80 Hz /, input 2. ADCs 2, 3, 4 convert analog video signals into 8-bit codes of color signals R, G, B. Sampling conversion 49.152 MHz. Codes with the ADC in parallel form are received in blocks 5, 6, 7 of the code processing, performing a doubling of the number of samples in a row. From the outputs of blocks 5, 6, 7, codes doubled in frequency arrive at the inputs of blocks 8, 9, 10, which double the lines in a frame from 480 to 960. Blocks 8, 9, 10 have two outputs: from the first to the first input of drive 11 / 12, 13 / codes are followed by codes of 480 odd lines of the frame, from the second output to the second input of the drive 11/12, 13 / codes are followed by codes of 480 even lines of the frame. Each drive 11, 12, 13 codes contains an odd frame code store 66 and an even frame code store 67.

After concentrating the codes of the odd / left / frame in block 66, the codes are sent from block 66 to block 14/15, 16 / of pulse amplifiers. During the period of their issuance, codes for the next even / right / frame are accumulated in block 67. In the period of the next odd frame, codes are sent from block 67 to block 14/15, 16 / of pulse amplifiers and the codes of the odd frame are accumulated again in block 66. Block 17 modulation of radiation performs luminance modulation, respectively, of the code values in parallel with 480 lines. Radiation from 480 emitters is projected by the 480th focusing cones of the optical fibers 86 onto the reflector of the piezoelectric deflector 28 with a pitch of 0.02 mm in line diameter, reflecting from which the radiation from the strings is transmitted to the reflector of the piezoelectric deflector 23, which simultaneously performs horizontal scanning of 480 odd lines when the reflector is rotated from left to right , when the reflector is turned from right to left, the even lines of 480 are scanned. The radiation of the focons 86 is projected with even lines in the intervals between the odd lines / Fig. 11/. For this, the reflector of the piezoelectric deflector 28 is rotated by a radiation offset of 0.02 mm by the control signal supplied to the internal electrode 89 / Fig. 12/ from the amplifier 26. For the frame, the scanning of all lines is repeated 48 times. The input of the master oscillator 20 in block 19 receives pulses of 7.68 kHz. The master oscillator 20 generates a control rectangular pulses with a repetition period of 130.2 μs / period of two lines /, which enter the output stage 21, which generates a triangular control voltage / 2 / with a period of 130.2 μs, supplied to the input of the amplifier 22 and from it to the internal electrode 89 of the piezoelectric deflector 23. Voltages from the first 24 and second 25 sources of reference voltages are supplied to the external electrodes. The end face of the piezoelectric deflector 23 with a reflector comes into oscillatory motion [4, p.122] with a frequency of 7.68 kHz and scans 960 lines in the rear focal plane of the projection lens 31, which projects the image onto a matte screen 32 with a magnification of 10 times. The viewer perceives a three-dimensional image through ZD glasses 35 with an IR receiver 34 on the frame, which receives control signals from an IR transmitter 33 located above the screen 32. The control signal for the IR transmitter 33 is a 80 Hz stereo clock clock input to the IR transmitter from the second control input of the digital monitor.

Used sources

1. Patent No. 2248103, cl. H 04 N 11/04, bull. No. 7 for 2005, a prototype.

2. Kolesnichenko O.V., Shishigin I.V. PC hardware. 5th ed., St. Petersburg, 2004, p. 588-565.

3. L.M. Kuchekyan. Light guides. M., 1973, p.77.

4. Fridland I.V., Soshnikov V.G. Automatic control systems in video recording devices. M., 1988, p.118, fig.5.5, p.122, fig.5.10.

5. Digital integrated circuits, reference book, Minsk, 1991, p.440, 231, 128.

6. "Radio" No. 7 for 1998, p. 71.

table 2 Specifications Values Input parameters PC video mode 640 × 480 × 160 Hz Input control signals operating frequency, clock pulses of stereo pairs 80 Hz Color signals R, G, V analog, separate Receiving frames in a stereo pair left right Monitor playback Video mode: samples, lines, frames 1280 × 960 × 160 Raster scan at the same time 480 lines with repeat per frame 48 times Frame scan no The number of active rows 960/480 × 2 / Counts per line 1280/640 × 2 / Sampling Code Sampling Rate 49.152 MHz Frame duration 6.25 ms Screen Duration 65.1 μs, no reverse Screen imaging Optoelectronic scan of 480 scopes at the same time and projection lens Estimated average light intensity when projecting an image 4104 cd Screen Size / Option / / 512 × 384 / mm. 25 ′ ′, diagonal 640 mm 3D image perception through ZD glasses with IR transmitter

Claims (1)

A digital monitor containing a frequency synthesizer, three channels, each of which includes a code processing unit and a series-connected code storage device and a pulse amplifier unit, a radiation modulation unit, the inputs of which are connected to the outputs of the pulse amplifier units, a first frequency divider, a horizontal scanning unit, the first amplifier and the first piezoelectric deflector with a reflector at the end, the first source of positive reference voltage, the output of which is connected to the second inputs of the first amplifier and the first the second piezoelectric deflector, the second source of negative reference voltage, the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector, the second amplifier and the second piezoelectric deflector in series with the reflector at the end, the third source of the positive reference voltage, the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector , the fourth source of negative reference voltage, the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector, pr a projection lens, in the outer focal plane of which there is a matte screen, the first output of the frequency synthesizer sampling pulses is connected to the first control inputs from the first to third code processing units, the horizontal scanning unit includes a serially connected master oscillator and an output stage, the output of which is the output of the horizontal scanning unit and connected to the input of the first amplifier, the code processing units are identical, each contains a trigger, from the first to the fourth registers, the adder and the corresponding the number of diodes, the trigger input, combined with the control input of the adder, is the control input of the code processing unit and is connected to the first output of the frequency synthesizer sampling pulses, the information inputs of the first and second registers are bitwise integrated, the information inputs of the third and fourth registers are bitwise combined, the first trigger output is connected to the control inputs of the second and third registers, the second trigger output is connected to the control inputs of the first and fourth registers, the outputs of the second register and the first register through the diodes are bitwise combined and connected to the first group of inputs of the adder, the outputs of the fourth register and the third register through the diodes are bitwise combined and connected to the second group of inputs of the adder, the control input of which is connected to the input of the trigger, the code drives are identical, each contains the corresponding number of blocks registers, the third control inputs of which are combined and connected to the corresponding output of the frequency synthesizer, the fourth control inputs of the register blocks are combined and connected They are connected to the first control output of the last block of registers, the outputs of the block of registers are the outputs of the code store and are connected to the inputs of their block of pulse amplifiers, the information inputs of the blocks of registers are bitwise combined, the blocks of registers are identical, each includes the first, fourth, first, second, third, and the fourth pulse distributors, the first seven registers, the second seven registers, the first counter of pulses connected in series and the first decoder, the second counter connected in series to them pulses and a second decoder, the first control input of the first key is the first control input of the register block, the first control input of the second key is the fourth control input of the register block, the second control input of the first key is the first control output of the register block, the output of the first key is connected to the input of the first distributor pulses, the outputs of which are connected in series to the first control inputs from the first to the last bits of the first seven registers, the output of the second key is connected to the input the second pulse distributor, the outputs of which are connected in series to the second control inputs from the first to the last bits of the first seven registers, the last output of the first pulse distributor is connected to the second control input of the first key, the last output of the second pulse distributor is connected to the input of the first pulse counter, the output of the first decoder connected in parallel to the third control inputs of the bits of the first seven registers, the output of the third key is connected to the input of the third distributor imp pulses, the outputs of which are connected in series to the first control inputs from the first to the last bits of the second seven registers, its last output is connected to the second control input of the third key, the output of the fourth key is connected to the input of the fourth pulse distributor, the last output of which is connected to the input of the second pulse counter, the output of the second decoder is connected in parallel to the third control inputs of the bits of the second seven registers, the outputs of the bits of the first seven registers and the outputs of the bits of the second seven registers Istras are bitwise combined and are the outputs of the block of registers and connected to the information inputs of the corresponding block of pulse amplifiers, the first control output of each previous block of registers is connected to the first control input of the first key of each subsequent block of registers, and the first control output of the last block of registers is connected in parallel to the fourth control the inputs of all blocks of the registers, the first, second and third blocks of pulse amplifiers are identical, each includes pulse amplifiers in the number of register blocks in the code stores and the number of bits in the code, the radiation modulation block is made of the corresponding number of channels, each of which contains a sequentially arranged emitter of three primary colors, micro-objects and a focusing cone of the fiber (focon), the inputs of the block are the inputs of the emitters connected to the corresponding outputs of the blocks of pulse amplifiers emitting the planes of the emitters are located in the rear focal plane of the micro-lenses, in the front focal plane of which are located the rear windows of the focusing cones of the optical fibers, the emitters through micro lenses, the focusing cones of the optical fibers, the reflector of the second piezoelectric deflector are optically connected to the reflector of the first piezoelectric deflector, which is located in the focal plane of the projection lens, in the outer focal plane of which there is a matte screen, characterized in that the second divider is introduced into it frequency, the output of which is connected to the input of the second amplifier, an IR transmitter located above the matte screen and the input of which is connected to the second amplifier the main input of the sync pulses of the stereo pairs of the frequency synthesizer, and the emitting window of the IR transmitter is located away from the screen, ZD glasses with an IR receiver located on the frame of the ZD glasses, the input window of which is located opposite the radiating window of the IR transmitter, into each of the three channels an ADC is introduced, the outputs of which are connected to the inputs of the code processing unit, and a line doubling unit, the inputs of which are connected to the outputs of the code processing unit of its channel, and the first, second, and third control inputs are connected respectively to the second output doubled pulses of the sampling frequency, the fourth output of the frames and the fifth pulse output of the frequency synthesizer lines, the first control input of the working frequency and the second control input of the clock pulses of the stereo pairs of the frequency synthesizer are connected to the corresponding outputs of the video adapter of the personal computer, the outputs of the frequency synthesizer are connected: the first output of the sampling pulses is connected in parallel to the control inputs of the first, second and third ADCs to the first control inputs from the first to third code processing units, the second pulse output of the doubled sampling frequency is connected to the first control inputs from the first to third line doubling units and to the third control inputs of the first, second and third code stores, the third output of the output signals is connected to the fourth control inputs from the first to third code stores, the fourth pulse output frames connected to the second control inputs of line doubling units, to the first control inputs of code stores, the fifth output of line frequency pulses is connected to the inputs of the first and second cases frequency amplifiers, to the third control inputs of the line doubling units, the first, second and third ADCs are identical, each includes a series-connected video amplifier, the input of which is an ADC input, and a piezoelectric reflector with a reflector at the end, a source of positive reference voltage, the output of which is connected to the second inputs of the video amplifier and a piezoelectric deflector, a source of negative reference voltage, the output of which is connected to the third inputs of the video amplifier and a piezoelectric deflector, an emitter from a pulsed LED, the input of which I It is controlled by the control input of the ADC, the slit aperture, and the micro lens, the line of the multi-element photodetector and the encoder, the outputs of which are the outputs of the ADC, the input windows of the line of the multi-element photo detector through the piezoelectric reflector are optically coupled through the micro lens and the slit diaphragm to the emitting side of the second pulse, the second LED and the input are respectively the first, second and third information inputs of a digital monitor connected to the corresponding outputs of the person adapter of the computer, the first, second and third blocks of line doubling are identical, each includes the first delay block and the adder and the second delay block connected in series, the information inputs of the first, second delay block and the first adder inputs are bitwise connected and connected to the outputs of the channel code processing block, the outputs of the second delay unit are the first output of the line doubling unit, the second output of which are the outputs of the adder, the first, second and third control inputs of the first delay unit are the second, third and third control inputs of the line doubling unit and are connected respectively to the second, fourth and fifth outputs of the frequency synthesizer, the first delay blocks are identical, each includes a series-connected element And and the first key, the second key, the first and second pulse distributors and seven registers with each corresponding number of bits, the signal inputs of the first and second keys are combined and are the first control input, connected to the second output of the frequency synthesizer, the second and third control input they are the first and second inputs of the And element connected to the fourth and fifth outputs of the frequency synthesizer, the output of the And element is connected to the second control input of the second key, the output of the first key is connected to the input of the first pulse distributor, the outputs of which are connected in series to the first control inputs from the first to the last bits of seven registers, the last output of the first pulse distributor is connected to the second control input of the first key and to the first control input of the second key and connect through the diode n to the first control inputs of the last bits of the seven registers, the output of the second key is connected to the input of the second pulse distributor, the outputs of which are connected to the first control inputs from the last bit to the first bit of the seven registers, and the last output of the second pulse distributor is connected through the diode to the control inputs of the first bits seven registers and through a diode connected to the second control input of the second key and to the first control input of the first key, information inputs of bits in each of the seven reg Istr are combined and are the first to seventh information inputs of the first delay block, the bit outputs in each of the seven registers are combined and are the outputs of the first delay block, connected to the second inputs of the adder in the line doubling block, the first and second key blocks are entered into each code processing block the inputs of which are bitwise combined and are the information inputs of the code processing unit, connected to the outputs of their ADC, the control input of the first block of keys is connected to the first output of the trigger, which controls the input of the second block of keys is connected to the second output of the trigger, the first and second blocks of delays are entered, the inputs of the first block of delays are connected to the outputs of the first register, the inputs of the second block of delays are connected to the outputs of the third register, the outputs of the first, second blocks of delays and the outputs of the adder are bitwise combined and are the outputs of the code processing unit, the first, second, and third code stores are identical, each key contains a key and a trigger, an odd frame (left) code store, and an even code store frame (right), the first and second information inputs are the bitwise combined first and second groups of inputs of the odd frame code store and the even code store, connected to the first and second groups of outputs of the line doubling unit, the first trigger output is connected to the first control input of the code store an odd frame, the second trigger output is connected to the first control input of the even-code drive, the first control input of the code-drive is the key signal input connected to the fourth output of the frequency synthesizer, the second control input is the control input of the key connected to the second control input of the clock pulses of the stereo pairs of the frequency synthesizer, the third control input is the combined second control inputs of the odd-frame code storage device and the even-frame code storage device connected to the second output of the synthesizer's double sampling frequency pulses frequencies, the fourth control input is the combined third control inputs of the odd frame code storage device and storage an even-code code generator connected to the third output of the frequency synthesizer output signals, an odd-frame code store and an even-frame code store, each includes 480 register blocks, the first control input of the first register block is the first control input of the odd (even) frame code store, the second control inputs of the register blocks are combined and are the third control input of the drive of codes of the odd (even) frame, the third control inputs of the register blocks are combined and are T The main control input, the outputs of the register blocks are the outputs of the odd (even) frame code storage device, the first and second inputs of the register blocks combined are bitwise the first and second information inputs of the odd (even) frame code storage device, a trigger is inserted into each register block, the input of which is connected through diodes to the last output of the second pulse distributor and to the last output of the fourth pulse distributor, the first trigger output is connected to the second control input of the second switch and to the first control input of the fourth key, the second trigger output is connected to the first control input of the second key and to the second control input of the fourth key, and the fourth control input of the register block is connected through a diode to the second output of the trigger, the signal inputs of the second and fourth keys are combined and are the second control input block of registers, the outputs of the fourth pulse distributor are connected to the second control inputs in sequence from the last to the first bits of the second seven registers, information the first (first) inputs of the bits of the first seven registers are bitwise combined and connected to the first group of outputs of the block of doubling strings, the information (first) inputs of the bits of the second seven registers are bitwise combined and connected to the second group of outputs of the block of doubling strings, the outputs of the bits in each register of the first seven registers combined and the outputs of the bits in each register of the second seven registers are combined and are the outputs of the register block, and the outputs of all the blocks of the registers are the outputs of the odd frame code store and the outputs of storage ring codes even frame, which are combined appropriately and are outputs code storage.

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