RU2326508C1 - Stereo television system - Google Patents

Abstract

FIELD: physics, radiotechnics.

SUBSTANCE: invention relates to the radio communication equipment and may be used for television broadcasting in the high-definition format. The technical effect a frame resolution of 1920×1080, increase in the image brightness, and doubling of the stereo pair frame rate. The technical effect attained by the following: four switches are introduced additionally at the transmitting side; six frame code accumulators and six control signal generation units are introduced additionally at the receiving side; the video data display device is represented by a flat-panel light-emitting diode screen with an IR transmitter on its enclosure, and 3D eye-glasses with an IR receiver on the eye-glass rim are introduced.

EFFECT: obtaining high frame definition, increase in image brightness stereo pair frame rate.

22 dwg, 1 tbl

Description

The invention relates to techniques for radio communications and can be used for television broadcasts in high resolution NDTV. Analogs are high-resolution television systems that claim to be the NTDV format [1 p.26-28], the disadvantages of these systems are: insufficient resolution, the need for broadband signal transmission channels, currently there are no 1920 × 1080 matrices for video cameras and get a picture 16: 9 is not yet possible [1 p.32], systems do not carry out a stereo effect at a resolution of 1920 × 1080, in fact there is a resolution of 1440 × 750 and without a stereo image. The digital stereo-television system [2] was adopted as a prototype. It contains a photoelectric converter on the transmitting side, which generates six analog color signals of the stereo pair from the right and left frames, six ADCs of video signals, a frequency synthesizer, three code shapers, a trigger, two keys and a radio signal transmitter from three channels , on the receiving side containing a control unit / channel selection /, three paths for receiving and processing codes of video signals, a channel for generating control signals, six blocks of pulse amplifiers, bl to modulate radiation, horizontal scanning unit, a first amplifier and a first pezodeflektor reflector on the end block frame scanning, the second amplifier and the second pezodeflektor reflector at the end, a projection lens, the matte screen and separate surveillance unit stereopair frames. The stereo pair frequency is 12.5 Hz, the frame rate is 50 Hz. The information of the codes of the right and left frames is transmitted by three radio channels, two carrier frequencies. At the receiving side, three radio signals are received in parallel, amplified, detected, the color codes of the video signals R, G, B are distributed over their channels, in which the samples are doubled in the lines and the lines are doubled in the frame. The frame scan is performed by two piezoelectric deflectors, a projection lens projects an image with magnification on a matte screen. The right and left frames are observed by the viewer separately by the right and left eye, the alternate overlapping of the field of view of which is performed by the separate observation unit by mechanical rotation of the neutral filters. The disadvantages of the prototype: insufficient resolution in the frame / 1200 × 800 /, low image brightness when scanning a frame on a matte screen that does not have an afterglow, low frame rate of stereo pairs 12.5 Hz.

The purpose of the invention is to increase the resolution of the frame to the format NDTV, increasing the brightness of the image and increasing the frame rate of stereo pairs. The technical result is: obtaining resolution in the frame of 1920 × 1080, increasing the image brightness and doubling the frame rate of stereo pairs. The result is achieved by obtaining a frame resolution of 2073600 pixels / 1920 × 1080 /, increasing the brightness of the image by using white LEDs in the flat panel screen 6220800/2073600 × 3 /. Matrix elements in the screen 2073600, each matrix element is a source of radiation of the three primary colors R, G, B. The resulting radiation of the three LEDs of the matrix element in space forms an image of one pixel.

Each element of the matrix includes three emitting LED cells, the brightness level of the color / R, G, B / emitting by each LED cell is determined by the duty cycle of the LED's radiation for the frame period: the ratio of the time when the LED emits to the time when it does not emit in the same frame period. The LEDs of all LED cells / LED cells / flat-panel screens synchronously start radiation from the beginning of the frame period, and each ends according to the code value of its color signal. On the receiving side for the frame period, the color signal codes are concentrated in the frame code stores, at the end of the frame period, the codes of three color signals are output into a block that converts the codes into the duration of the control signals that determine the duration of the emission of each LED in the frame period. There are no line and frame scans in the receiving side. For separate observation of the frames of a stereo pair, 3D glasses are used, made according to the technology of LCD cells [3 p.558-565]. The viewer receives volume perception through 3D glasses, in which, simultaneously with the frame change, the field of view is alternately blocked for that of the eyes, the frame of which is not on the screen. A video mode of 960 × 540 × 50 Hz is formed on the transmitting side: 960 is the number of encoded samples in a line, 540 is the number of encoded lines in a frame, 50 Hz is the total frame rate, left and right. The frequency of stereo pairs is 25 Hz, the stereo pair includes right and left frames, following each other. Stereopair information is transmitted by three radio channels / side frequencies of two carrier frequencies, as in the prototype /. Codes are 8-bit. The scanning of lines on the transmitting side is progressive without reverse moves both in rows and frames. The clock frequency on the transmitting side is:

where 50 Hz - frame rate / 25 Hz + 25 Hz /,

540 - the number of lines in the frame,

960 is the number of encoded samples per line,

2 - coding of samples by a bipolar signal: positive and negative half-sine waves,

8 - the number of bits in the code.

Code Sampling Rate:

Line frequency: f ₀ = 540 × 50 Hz = 27 kHz.

Line length

frame duration

Piezo-deflector oscillation frequency on the transmitting side during horizontal scanning

During the oscillation period, two lines unfold: from left to right and from right to left.

Codes Period

sequence of bits in the serial code

On the receiving side, the video mode is 1920 × 1080 × 50 Hz. The number of samples in a line is 1920, the lines in a frame are 1080, the frame rate is 50 Hz, the frequency of stereo pairs is 25 Hz. The receiving side provides the viewer with a perception of the three-dimensional image.

The essence of the invention is that in a stereo television system comprising a transmitting side including a photoelectric converter, three ADCs of a video signal, three code shapers, a trigger and two keys, a pulse counter, two self-propelled pulse distributors, a frequency synthesizer and a transmitter, and a receiving side including a unit control, three paths for receiving and processing codes of video signals, a channel for generating control signals and a device for displaying video information, the third to sixth keys are entered on the transmitting side, on the receiving side from the first to the sixth drive codes of the frame, from the first to the sixth blocks of the formation of control signals, and the video information display device is represented by a flat-panel LED screen with an IR transmitter on the screen body and 3D glasses with an IR receiver on their frame are introduced.

The transmitting side in Fig. 1, the frame raster in Fig. 2, the shape of the control voltages in Fig. 3, the structure of the digital streams in Fig. 4, the ADC of the video signal in Fig. 5, the construction of the piezoelectric deflector in Fig. 6, the R / G signal code generator / in Fig. 7, code generator B in Fig. 8, the receiving side in Fig. 9, the code processing unit in Fig. 10, the first delay unit in Fig. 11, the frame code storage in Fig. 12, the register block in Fig. 13 and 14, the bipolar amplitude detector in FIG. 15, the stereo clock sync pulses block in FIG. 16, the emitting LED cell in FIG. 17, the composition and shape of one th element of the matrix 18, the arrangement of the elements of the matrix and the SD-cells in the screen 19, the frequency spectra of the signals of the transmitter 20, the control signal generating unit 21, the system operation time chart in Figure 22.

The transmitting side of the system includes (Fig. 1) a photoelectric converter 1, which is a sensor of video signals of two images of the same space and generates three video signals of the right frame R _p , G _p , V _p and three video signals of the left frame R _l , G _l , V _l and contains the first lens 2 right, connected in series with the first amplifier 3 and the first piezoelectric deflector 4 with a reflector at the end located in the focal plane of the lens 2, the first source 5 of positive reference voltage, the second source 6 of negative reference voltage connected in series to the second amplifier 7 and the second piezoelectric deflector 8, the front end of which has two faces located at an appropriate angle to each other and with a reflector on each face, a third source of positive reference voltage, fourth source 10 of negative reference voltage, second lens 11 the left, connected in series with the third amplifier 12 and the third piezoelectric deflector 13 with a reflector at the end located in the focal plane of the second lens 11, the fifth source 14 of the positive reference n voltage, a sixth source of negative reference voltage 15, a horizontal scanning unit 16 from a driving generator 17 and an output stage 18, a vertical scanning unit 19 including a series connected element And 20, a driving generator 21 and a summing amplifier 22, the first 23 and second 24 dichroic mirrors, located sequentially one after another and against the first reflector of the piezoelectric deflector 8, first 25, second 27, third 26 micro lenses, first 28, second 30, third 29 photodetectors, first 31, second 33, third 32 pre-amplifiers, tre 34 and fourth 35 dichroic mirrors arranged successively one after another and against the second piezoelectric reflector 8, fourth 36, fifth 38, sixth 37 micro-lenses, fourth 39, fifth 41, sixth 40 photodetectors, fourth 42, fifth 44 and sixth 43 preamplifiers . The second lens 11 is located to the left of the lens 2, the optical axis of the lens 11 is parallel to the optical axis of the lens 2, the distance between the axes of the lenses corresponds to the optimal stereoscopic effect for human vision.

The transmitting side includes a trigger 45, the first 46, the third 47, the fifth 48 keys, the second 49, the fourth 50, the sixth 51 keys, the first ADC 52 for the signals R _p and R _l , the second ADC 53 for the signals G _p and G _{l the} third ADC 54 for signals V _p and V _l , the first shaper 55 codes, the second shaper 56 codes, the third shaper 57 codes, the first 58 and second 59 self-propelled pulse distributors, a counter 60 pulses, a master oscillator 61 of a sinusoidal oscillation and a synthesizer 62 frequencies, the first 63 and second 64 ADCs of a sound signal, to the inputs of which sound signals Sv1 and Sv2 are applied and transmitted uk 65 radio signals of the three channels. The first channel includes a series-connected first carrier frequency amplifier 66, an amplitude modulator 67 and an output amplifier 68, the second channel includes an amplitude modulator 72 and an output amplifier 73, the third channel includes a second carrier frequency amplifier 69, an amplitude modulator 70 and an output amplifier 71. Each of the amplitude modulators 67, 72, 70 includes a series-connected ring modulator and a band-pass filter [4 p.234], filtering out the unnecessary side frequency in the spectrum of the amplitude-modulated carrier, the ring module torus suppressed carrier frequency. ALC 52, 53, 54 are identical (Fig. 5/), each contains an amplifier 74 and a piezoelectric deflector 75 with a reflector at the end, a positive reference voltage source 76, a negative reference voltage source 77, an emitter including a pulsed LED 78, aperture diaphragm 79, and a micro lens 80 , and includes a line of 81 multi-element photodetectors and an encoder 82. All piezoelectric deflectors 4, 8, 13, 75 are end bimorph piezoelectric elements with a light reflector at the end, are structurally executed / Fig.6/ equally [5 c.118] from the first 83 and second 84 piezoelectric plate, inside the lower electrode 85, the first 86 and the second 87 external electrodes. One end of the piezoelectric plates is fixed in the holder 88, a reflector 89 is fixed on the free end. The free end of the piezo deflector 8 is made of two faces located at an appropriate angle to each other, each face has its own reflector, they separate the rays of the right 2 and left 11 lenses in their directions . ADCs 63 and 64 are identical [2 p.30 of Fig. 7], they are used without changes, they convert sound signals into 16-bit codes, which are fed to the second information inputs of blocks 55, 56. The first 55 and second 56 code generators are identical / fig. .7 /, each includes a trigger 90 and a switching unit 91 and three channels. The first and second channels are identical. The first channel includes a series-connected block of 92 AND elements, the first 93, second 94 OR elements and an output switch 95 and a self-propelled distributor 96 of pulses, the second channel includes a second block 97 of AND elements, a third 98, fourth 99 OR elements and an output switch 100 and a self-propelled distributor 101 pulses. The third channel includes two blocks 102, 105 of AND elements, fifth 106 and sixth 106 OR elements, and two self-propelled pulse distributors 104, 107.

Blocks 55, 56 include first 108, second 109 keys, pulse counter 110 and decoder 111. In the first code generator 55, the decoder 111 has first and second outputs connected to the corresponding inputs of the keys 108, 109. In the second code generator 56, the decoder 111 has and the third output, which is the second output of block 56, is connected to the input of the first self-propelled pulse distributor 58 and to the counting input of the pulse counter 60. The first and second information inputs of blocks 55, 56 are the inputs of the switching unit 91 and the inputs of the blocks 102, 105 of AND elements, the third and fourth information inputs are the third inputs of the second and fourth elements OR 94, 99. The control inputs are: the first is the trigger input 90, the second - the combined inputs of the counter 110 pulses and keys 108, 109 / 6.48 MHz /, the third - the signal inputs of the output keys 95, 100 / 103.68 MHz /, the fourth - the control input of the counter 110 pulses, 27 kHz.

The output in block 55 is the combined outputs of the output keys 95, 100. In block 56 there are two outputs: the first is the output of the output keys 95, 100, the second is the third output of the decoder 111. The third code generator 57 contains / Fig. 8/ trigger 90, block 91 switching and two identical channels: the first includes a block of 92 AND elements, the first 93 and second 94 OR elements and an output switch 95, and a self-propelling pulse distributor 96, the second includes a block of 97 AND elements, the third 98, the fourth 99 OR elements and the output key 100, and a self-propelled distributor of 101 pulses. The first information input is the inputs of the switching unit 91, the second and third are the second inputs of the blocks 94, 99 of the elements of the OR elements. The first control input is the trigger input 90, the second is the combined inputs of the blocks 96, 101 / 6.48 MHz /, the third is the signal inputs of the output keys 95, 100 / 103.68 MHz /.

строк кадра 186_1-540. Информационным входом накопителя кодов кадра являются поразрядно объединенные 1-8 входы 540 блоков 186 регистров. Информационные входы накопителей кодов кадра подключены: 146 и 147 к выходам соответственно блоков 122, 123, 148 и 149 к выходам блоков 144, 145, 150 и 151 к выходам блоков 133, 134. Управляющими входами накопителей кодов являются: первым - первый управляющий вход первого блока 186₁ регистров, вторым - объединенные вторые управляющие входы /54 кГц/ блоков 186 регистров, третьим - объединенные третьи управляющие входы /U_д 25,92 МГц/ блоков 186_1-540 регистров. Каждый управляющий выход предыдущего блока 186 регистров является первым управляющим входом каждого последующего блока регистров. Управляющий выход последнего блока регистров 186₅₄₀ подключен параллельно к четвертым управляющим входам всех блоков 186 регистров. Блоки регистров 186 идентичны /фиг.13 и 14/, каждый включает первый 187 и второй 188 ключи, распределитель 189 импульсов и восемь регистров 190_1-8. Информационным входом блока регистров являются поразрядно объединенные третьи входы разрядов восьми регистров 190. Выходами блока регистров 186 являются параллельные выходы всех разрядов восьми регистров 190, всего 15360 выходов /1920×8/. Выходы 540 блоков регистров являются выходами каждого накопителя 146-151 кодов кадра, которых 8294400 /15360×540/. Управляющими входами являются: первым - первый управляющий вход первого ключа 187, вторым - сигнальный вход /U_выд 54 кГц/ второго ключа 188, третьим - сигнальный вход первого ключа 187 /U_д 25,92 МГц/, четвертым - первый управляющий вход второго ключа 188, подключенный к управляющему выходу последнего блока 186₅₄₀ регистров. Последний выход /1920/ распределителя 189 импульсов подключен к второму управляющему входу первого ключа 187 и является управляющим выходом блока 186 регистров, подключенным к первому управляющему входу следящего блока 186₂ регистров. Выход первого ключа 187 подключен к входу распределителя 189 импульсов, выходы которого последовательно с первого по 1920-й подключены параллельно к первым управляющим входам разрядов восьми регистров 190_1-8. Выход второго ключа 188 подключен параллельно к вторым управляющим входам разрядов восьми регистров 190 и к второму управляющему входу ключа 188, закрывая его после прохода одного импульса U_выд. Выходы накопителей 146-151 кодов кадра подключены к входам соответственно блоков 152-157 формирования управляющих сигналов, назначение которых выполнять преобразование "код - длительность излучения" и запитывать светодиоды во всех СД-ячейках на длительность, соответствующую величине кода. Каждый из блоков 152-157 содержит преобразователей "код - длительность излучения" по числу отсчетов в строке /1920/ и числу строк своего накопителя кодов кадра 1036800 /1920×540/.The receiving side includes / FIG. 9 / antenna, control unit 112 / channel selection /, first, second and third paths for receiving and processing video signal codes, a channel for generating control signals, a video information display device and two sound reproduction channels. The first path for receiving and processing codes of video signals receives and processes the codes of signals R _p and R _l and includes serially connected radio signal receiving unit 113, a radio frequency amplifier 114 and a bipolar amplitude detector 115, first 116 and second 117 pulse shapers, and a signal channel R containing first 118, second 119 signal registers R, code processing unit 120, first delay unit 121, adder 122 and second delay unit 123. The second path for receiving and processing codes of video signals receives and processes the codes for signals In _p and V _l and includes a block 124 for receiving, radio signals, radio frequency amplifier 125 and a bipolar amplitude detector 126, first 127, second 128 pulse shapers, and signal channel B including the first 129, second 130 are signal registers B, a code processing unit 131, a first delay unit 132, an adder 133 and a second delay unit 134. The third path of the reception and processing of codes of video signals receives and processes the codes of signals G _p and G _l and contains serially connected radio signal receiving unit 135, a radio frequency amplifier 136 and a bipolar amplitude detector 137, first 138 and second 139 pulse shapers, and a signal channel G including the first 140, second 141 G signal registers, code processing unit 142, first delay unit 143, adder 144 and second delay unit 145. The receiving side includes frame code drives introduced from the first 146 to the sixth 151, the control signal generation blocks from the first 152 to the sixth 157, a flat-panel LED screen 158 / LED screen /, an IR transmitter located on the body of the LED screen, 3D glasses 160 with an IR receiver 161 on the frame of 3D glasses. The operating side of the receiving side provides a channel for generating control signals, including a block 162 for extracting horizontal sync pulses / SSI /, a frequency synthesizer 163, a key 164 connected in series, a pulse counter 165 and a decoder 166, and a stereo pair / SIS / sync puller 167. The receiving side includes identical first 168, second 169 sound reproduction channels, the image from the screen 158 is perceived by the viewer as surround through 3D glasses 160. When the right and left frames are played on the screen, the glasses of 3D glasses alternately lose transparency: each eye sees only its own frame, which and gives a stereo effect. Glasses of glasses are made by the technology of LCD cells of the translucent type, used as electronically controlled filters / shutters /. With the arrival of the 25 Hz SIS clock pulse to the IR transmitter 159, it emits an IR pulse received by the IR receiver 161 (Fig. 9/), which provides a control signal to the LCD cell of the left glass, dimming it for 20 ms, then gives a second signal to LCD cell of the right glass, dimming it for 20 ms. Each eye sees its frame. Blocks 120, 131, 142 of the code processing are identical (Fig. 10/), each includes a trigger 170, the first block of delay elements 171, the first to fourth 172-175 registers, the second block of delay elements 176, fifth register 177, sixth register 178, adder 170 and 16 diodes. Block 171 delays the codes by 77 ns to restore the even codes to the odd ones. Disc 176 delays codes by 14.5 ns. Registers 177 and 178 operate storing codes 77 ns and outputting their signals U _vyd a first flip-flop 170. The data input registers are combined bitwise inputs 172, 173, the second - the inputs 1-8 of the first unit delay elements 171. The output is the bitwise integrated outputs of the registers 177, 178 and block 176. The control input is the input of the trigger 170. The first delay blocks 121, 132, 143 are identical (Fig. 11/), each includes the And 180 element, the first 181, the second 182 keys, the first 183 , the second 184 pulse distributors and eight registers 185 _1-8 , each of which contains the number of samples in a row of 1920 bits. Blocks 121, 132, 143 delay the codes of each line by a line duration of 37 μs. Drives 146-151 frame codes are identical / 12 /, each includes blocks of 186 registers for the number of half

lines of frame 186 _1-540 . The information input of the frame code storage device is the bitwise integrated 1-8 inputs of 540 blocks of 186 registers. The information inputs of the frame code drives are connected: 146 and 147 to the outputs of blocks 122, 123, 148 and 149, respectively, to the outputs of blocks 144, 145, 150 and 151 to the outputs of blocks 133, 134. The control inputs of the code stores are: first - the first control input of the first block 186 ₁ registers, the second - the combined second control inputs / 54 kHz / blocks 186 registers, the third - the combined third control inputs / U _d 25.92 MHz / blocks 186 _1-540 registers. Each control output of the previous block of registers 186 is the first control input of each subsequent block of registers. The control output of the last block of registers 186 _{540 is} connected in parallel to the fourth control inputs of all blocks of 186 registers. The blocks of the registers 186 are identical (Figs. 13 and 14), each of which includes the first 187 and second 188 keys, a pulse distributor 189 and eight registers 190 _1-8 . The information input of the register block is the bitwise combined third inputs of the bits of eight registers 190. The outputs of the block of registers 186 are the parallel outputs of all bits of the eight registers 190, a total of 15 360 outputs / 1920 × 8 /. The outputs of 540 register blocks are the outputs of each drive 146-151 frame codes, of which 8294400/15360 × 540 /. The control inputs are: the first is the first control input of the first key 187, the second is the signal input / U _output 54 kHz / second key 188, the third is the signal input of the first key 187 / U _d 25.92 MHz /, the fourth is the first control input of the second key 188 connected to the control output of the last block of 186 ₅₄₀ registers. The last output / 1920 / of the pulse distributor 189 is connected to the second control input of the first key 187 and is the control output of the register block 186 connected to the first control input of the servo unit 186 of ₂ registers. The output of the first key 187 is connected to the input of the pulse distributor 189, the outputs of which are connected in series from the first to the 1920th in parallel with the first control inputs of the bits of eight registers 190 _1-8 . The output of the second key 188 is connected in parallel to the second control inputs of the bits of eight registers 190 and to the second control input of the key 188, closing it after passing one pulse U _vyd . The outputs of the drives 146-151 frame codes are connected to the inputs of the control signal generation blocks 152-157, respectively, the purpose of which is to perform the code-to-radiation duration conversion and power up the LEDs in all LED cells for a duration corresponding to the code value. Each of the blocks 152-157 contains converters "code - duration of radiation" by the number of samples in the line / 1920 / and the number of lines of its drive frame codes 1036800/1920 × 540 /.

коду 00000010 соответствует длительность излучения светодиода в два импульса с генератора 193-156 мкс, коду 00000011 - три импульса 234 мкс и т.д., коду 11111110 соответствует длительность излучения в 254 импульса 18942 мкс, коду 11111111 - 255 импульсов 19922 мкс. Инерционность срабатывания светодиодов менее 1 мкс, что легко выполнимо. По окончании накопления кодов блоками 146-151 сигнал U_к/50 Гц/ открывает все первые 194 и вторые 197 ключи в блоках 152-157. Коды кадра синхронно и в параллельном виде поступают на информационные входы вычитающих счетчиков 195 с 1-го по 1036800. Открытые ключи 194 пропускают импульсы 12,8 кГц с генератора 193 на счетные входы вычитающих счетчиков 195. Напряжение питания с источников 198 питания через открытые ключи 197 запитывает светодиоды 191 в СД-ячейках, которые излучают с длительностью, соответствующей величине кода. Процесс вычитания в счетчиках 195 длится до появления кода 00000000.The flat-panel LED screen 158 represents a set of 2073600/1920 × 1080 / matrix elements made directly in the glass of the LED screen and includes screen glass and matrix elements according to the number of screen resolutions 158. Each matrix element includes three emitting LED cells, each of which emits one from the main colors / R, G, B /. The emitting LED cell / LED cell / contains / Fig.17/ sequentially located white LED 191 and the corresponding color filter 192. Three LED cells in the matrix element form a triangle / Fig. 18/, the arrangement of the matrix elements and LED cells in the screen glass screen in Fig.19. Elements of the matrix housing do not have. The screen glass for placing the SD cells has corresponding recesses, in which the LEDs 191 with light filters are placed. The control input / power conductor / of each LED is connected to its output in blocks 152-157. The action of the LED cell is based on a directly proportional dependence of the duration / duty cycle / radiation of the LED on the value of the color signal code. The brightness level perceived by vision corresponds to the duration of the LED radiation in the frame period. The total emission of three colors by the matrix element forms the corresponding color tone of the pixel for vision. The radiation of each LED is involved in the process not only of its pixel, but also of the neighboring LED cells / to the right, left, top, bottom /. As light-emitting diodes, super-bright white-light emitting diodes of the Nichia NEPW 500 company with a luminous intensity of 4.6 cd and an emission angle of 15 ° are adopted [6 p. 47]. LEDs with color filters of miniature design without enclosures and with a diameter of up to 0.5 mm are made inside the screen glass. Blocks 152-157 for generating control signals are identical (Fig. 21/), each includes a pulse generator 193 and 1036800 code-to-radiation duration converters (1920 × 540), which are identical, and each includes a first key 194 connected in series, subtracting a pulse counter 195 , the decoder 196 and the second key 197, and the LED power supply 198, the output of each second key 197 is connected to its LED in the SD cell, and the signal input of the key 197 is connected to the output of the power source 198. The initial state of the keys 194, 197 is closed. The pulse generator 193 is a frequency multiplier, it multiplies 50 Hz × 256 = 12.8 kHz and provides a frequency of 12.8 kHz to the signal inputs of the first keys 194. The code-to-radiation-time converters operate identically. When the frame duration is 20 ms / 50 Hz / code 00000001 corresponds to the duration of the LED emission in one pulse 78 μs from the generator 193

the code 00000010 corresponds to the duration of the emission of the LED in two pulses from the generator 193-156 μs, the code 00000011 - three pulses of 234 μs, etc., the code 11111110 corresponds to the duration of the radiation of 254 pulses 18942 μs, the code 11111111 - 255 pulses of 19922 μs. The inertia of the LEDs is less than 1 μs, which is easily feasible. Upon completion of the accumulation of codes by blocks 146-151, the signal U _to / 50 Hz / opens all the first 194 and second 197 keys in blocks 152-157. The frame codes synchronously and in parallel form are fed to the information inputs of the subtracting counters 195 from the 1st to 1036800. The public keys 194 pass 12.8 kHz pulses from the generator 193 to the counting inputs of the subtracting counters 195. The supply voltage from the power sources 198 through the public keys 197 feeds the LEDs 191 in the LED cells, which emit with a duration corresponding to the value of the code. The subtraction process in the 195 counters lasts until the 00000000 code appears.

With the code 00000000, the decoder 196 generates a signal U _s , closing both keys 194 and 197. The LED interrupts the cure. The duration of the emission of each LED is perceived as the brightness level of the color emitted by it. The radiation of the LEDs of the three LED cells / R, G, B / form the color tone of the pixel. The emission rate of all the LEDs of the screen in the frame period / 20 ms / forms the brightness and color tones of all the pixels on the screen 158. Each LED is served by its own code-to-radiation-time converter. By modern technologies, microcircuits are created with tens of millions of transistors [7 p.65], therefore, each of blocks 146-151 and 152-157 can be made in one microcircuit. The diameter of each LED is taken to be 0.5 mm (Fig. 18/), the size of the matrix element / three LED cells / is 1 × 1 mm. The thickness of the screen glass / or other material / 5-7 mm. The line width is 1 mm / Fig. 19/. The size of the 158 LED screen is:

horizontal 1920 × 1 mm = 1920 mm,

vertical 1080 × 1 mm = 1080 mm, diagonal 2203 mm,

or 86.7 inches. The brightness of the LED with a light intensity of 4.6 cd with a diameter of the radiating part of 0.5 mm, the area of which is 0.2 mm ² / 3.14 × 0.25 ² / is:

where 0.2 mm ² / 0.2 · 10 ^-6 m ² / is the radiation area of the LED.

If the radiation is reduced by 50%, the brightness of the image on the screen will be quite sufficient. Block 167 allocation of clock pulses of stereopairs SIS includes / 16 / from the first 199 to the third 201 pulse counters, from the first 202 to the third 204 elements And, from the first to third 205, 206, 207 elements NOT and a diode. With the arrival at the counting inputs of counters 199-201 of three codes from units 11111111 and at the fourth input to element And 204 of the SSI pulse from block 162, the sync pulse of the SIS stereo pair appears at the output of block 167, their frequency is 25 Hz and fed to the input of the IR transmitter 159.

The photoelectric converter 1 generates six analog video signals of two images from the right 2 and left 11 lenses, which from the pre-amplifiers 31, 32, 33 are fed to the inputs of the keys 46, 48, 47 and from the pre-amplifiers 42, 43, 44 to the inputs of the keys 49, 51 , 50. From the outputs of the keys 46, 49, the analog signals are fed to the input of the first ADC 52, from the keys 47, 50 to the input of the second ADC 53, from the keys 48, 51 to the input of the third ADC 54. The alternate output of the stereo pair codes with the ADC is performed by trigger 45 and keys 46-48, 49-51. Pulses of 50 Hz from the tenth output of block 62 are sent to trigger 45. The signal from the first output of the trigger opens keys 46, 47, 48, which pass the analog video signals of the right frame during the period of the first frame to the inputs of the 52-54 ADC. With the arrival of the second 50 Hz pulse to trigger 45, the signal from its second output closes the keys 46-48 and opens the keys 49-51, which pass the analog video signals of the left frame during the second frame period in the 52-54 ADC. The clock inputs of the ADC from the first output of block 62 receive clock pulses of 12.96 MHz discretization codes. The 52-54 ADCs convert analog video signals into 8-bit codes. The shapers 55, 56, 57 of the code convert the parallel codes from the ADC into serial ones and replace the representation of units in the codes from pulses with positive and negative half-sinusoids of the single frequency 103.68 MHz from the fourth output of the frequency synthesizer 62 in them. The master oscillator 61 generates sinusoidal oscillations with a stability of 10 ^-7 . A frequency synthesizer 62 generates and issues: from the first output, sampling pulses of 12.96 MHz to the ADC 52-54 clock inputs and to the first control inputs of the shapers 55, 56, 57 codes, from the second output 6.48 MHz sampling pulses of the line to the second shaper inputs 55-57 codes to the first control inputs of the ADC 63, 64, from the third - pulses of 81 kHz sampling of the sound codes to the second inputs of the ADC 63, 64, from the fourth - sinusoidal oscillations of 103.68 MHz to the third control inputs of the shapers of 55-57 codes, from the fifth output - pulses of 27 kHz line frequencies to the fourth directs inputs formers 55, 56 codes the first input unit 19 and third control inputs of the ADC 63, 64, the sixth output - pulses 25 Hz frequency stereopairs the second input unit 19 and the control 60 of the pulse counter input U _o, from the seventh output - 13.5 kHz pulses to the input of the horizontal line block 16, from the eighth — sinusoidal oscillations of the first carrier frequency 1244.16 MHz / 103.68 MHz × 12 / for amplifier 66, from the ninth — sinusoidal oscillations of the second carrier frequency 933.12 MHz / 103.68 MHz × 9 / for the amplifier 69, from the tenth output - pulses of 50 Hz frame rates to the input t rigger 45. The ADC 63, 64 converts the sound signals into 16-bit codes that are fed to the second information inputs of blocks 55, 56. Self-propelled pulse distributor 58 with the start signal U _p coming from the second output of block 56 / at the time of line sampling pulse 479 figure 4 / gives a code of eight units 11111111, which is the code of the horizontal sync pulse SSI / 959 counting in each line of figure 4 /, to the third information inputs of the drivers 55, 56 codes and to the second information, the input of the generator 57 codes. A self-propelled distributor of 59 pulses with the arrival of a start signal U _p from the second output of block 60 gives a code of eight units 11111111, which is a clock pulse of the SIS stereo pairs / 960th count in the last line of the left frame of the stereo pair of Fig. 4 / to the fourth information inputs of blocks 55 56 and to the third information input of block 57. The two-bit counter 60 gives a start signal U _p from the second output for block 59 with the second pulse coming to the input of the counter 60 from the second output of block 56, after which the counter 60 is reset to a stereo frequency signal U _o 25 Hz . The second pulse from block 56 means the end of the period of the second / left / frame of the stereo pair. The ICU code represents the end of the stereo pair, followed by the first frame / right / of the next stereo pair.

The spectrum of the amplitude-modulated signal of the transmitter 65 / Fig.20/ consists of a carrier frequency and two side frequencies. One of the side frequencies and the carrier itself in the information sense are redundant. Therefore, in each amplitude modulator 67, 70, 72, the carrier frequency is suppressed and one of the side / unnecessary / frequencies is filtered out. Amplitude modulator 67 outputs to the output amplifier 68 an upper side frequency of 1347.84 MHz / f ₁ + 103.68 MHz / from the first carrier. The amplitude modulator 72 outputs to the input of the output amplifier 73 the lower side frequency of 1140.48 MHz / f ₁ - 103.68 MHz / from the first carrier. The amplitude modulator 70 outputs to the output amplifier 71 an upper side frequency of 1036.8 MHz / f ₂ + 103.68 MHz / from the second carrier. The first channel of the transmitter 65 emits an upper side frequency of 1347.84 MHz with the information of the codes R _p and R _l and with carrier stability of 10 ^{-7, the} occupied band on the air is ± 135 Hz or 270 Hz. The second channel emits the lower side frequency of 1140.48 MHz with the information of the codes In _p and B _l , the occupied band on the air ± 114 Hz or 228 Hz, the third channel emits the upper side frequency of the second carrier 1036.8 MHz with the information of the codes G _p and G _l , occupied band on the air ± 104 Hz or 208 Hz. A total of 706 Hz bandwidth over three channels. Lens 2 creates the right image in the focal plane in which the reflector of the piezoelectric deflector 4 is located. Its reflector has a width of 0.02 mm, a length of 10.8 mm / 0.02 mm × 540 /. The dimensions of the deploying element are 0.02 × 0.02 mm. According to the control voltages (Fig. 3/) from the amplifier 3, the piezoelectric deflector 4 vibrates the end face with the reflector relative to the first reflector of the piezoelectric deflector 8, scanning the right image. The lens 11 creates a left image in the focal plane where the reflector of the piezoelectric deflector 13 is located. Its reflector has the same dimensions as the reflector of the piezoelectric deflector 4, and vibrates the end face relative to the second reflector of the piezoelectric deflector 8, scanning a row of the left image. Block 16 line scan produces a linearly varying voltage in the form of an isosceles triangle / 3 /, the period of the control voltage is equal to the duration of two lines. For a raster of 540 lines at 50 Hz frames, piezo-deflectors 4 and 13 oscillate at a frequency of 13.5 kHz. During the period of one oscillation, two lines are scanned, the line frequency is 27 kHz. The progression of lines is progressive without reverse moves / Fig. 2/. The piezoelectric deflector 8 performs a frame scan synchronously of two frames: when scanning down, an odd / right / frame goes, when scanning up, there is an even / left / frame.

The piezoelectric deflector 8 oscillates at a frequency of 25 Hz, which is 50 frames per second. Frame scan is also without reverse moves. The width of the reflectors of the piezoelectric deflector 8 of 0.02 mm, the length of each 19.2 mm / 0.02 mm × 960 samples /. From the output of the summing amplifier 22, a linearly varying and stepwise voltage is supplied to the amplifier 7, Fig. 3, amplified to the required value by the amplifier 7 [5 p.122]. Summing amplifier 22 performs the summation of the line voltage from the master oscillator 21 with pulses of 27 kHz line frequency. Each line impulse moves the line at the end of its move by one line step, it turns out 540 lines, all active. Mixed color R, G, B reflected from the first reflector of the piezoelectric deflector 8 are directed to their micro-lenses, which collect them into their photodetectors 28, 30, 29, respectively. Analog video signals are sent from the photodetectors to pre-amplifiers 31, 33, 32. The rays are subjected to a similar process from the second reflector of the piezoelectric deflector 8, the analog video signals are supplied to the preamplifiers 42, 44, 43. From the preamplifiers, the signals of the right frame through the public keys 46, 48, 47 are fed to the ADC 52-54. In the next frame period (left), the signals from the preamplifiers 42, 44, 43 through the public keys 49, 50, 51 enter the ADC 52-54. The ADCs 52-54 have one conversion principle, which consists in scanning the beam (Fig. 5/) from the LED 78 with a piezoelectric deflector 75 reflector along the plane of the entrance pupils of the photodetector line 81 of the multi-element photodetector. The light pulse is converted into an electrical signal that excites the corresponding bus of the encoder 82, which gives the code of the instantaneous value of the input signal. Discretization of the conversion of 12.96 MHz. The source of cure is a pulsed LED AL402A with a response time of 25 ns. Line 81 includes 255 photodetectors for encoding signals with an 8-bit code. Photodetectors in the line 81 avalanche photodiodes of the APD with a response time of 10 ns. An encoder from K155IV1 microcircuits with a response time of 20 ns. The encoder generates codes from 00000001 to 11111111. The first photodetector in line 81 corresponds to the code 00000001, the second to the code 00000010, the third to 00000011, etc., the 265th to the code 11111111. The conversion time to the ADC is 30 ns, satisfying a frequency of 12.96 MHz / 77 ns /. The first shaper 55 codes gives from the first to 952-th signal codes R _p or R _l , three sound codes, SSI code and in the last line of the left frame SIS code / 4 /. Units in codes of odd samples of a line are represented by positive half-sinusoids of a single frequency of 103.68 MHz with a stability of oscillations of 10 ^-7 , units in codes of even samples of a line are represented by negative half-sines of the same frequency. The second generator 56 codes gives from the first to the 952nd signal codes G _p or G _l , three sound codes, the SSI code and the SIS code. The third generator 57 codes gives from the first to the 952nd signal codes In _p or V _l , the SSI code and the SIS code.

The operation of the shapers 56, 55 codes, Fig.7.

The ADC codes 52, 53 arrive in parallel with a frequency of 12.96 MHz at the inputs of the switching unit 91, which branches the stream of 12.96 MHz codes into two at 6.48 MHz: the first stream is the codes of the odd samples of the line, the second is the codes of the even samples of the line / Fig. 4/. Block 91 of four K176KT1 microcircuits, which are 4-channel switches with a response time of 25 ns [8 p. 222]. The channel 90 is connected to the outputs of block 91 in turn by a trigger 90. At the second inputs of the elements AND of blocks 92, 97, 8 pulses are received sequentially from self-propelled distributors 96, 101 pulses, each having 8 bits. Starting pulses for them are 6.48 MHz pulses. From the outputs of the elements AND blocks 92, 97, the pulses of the codes sequentially through the OR elements 93, 94 and 98, 99 open the output keys 95 and 100 for a duration of 10 ns. The signal inputs of the output keys receive 103.68 MHz single-frequency sinusoids. The first output switch 95 in the open state passes one positive half-sine wave, the second output key 100 in the open state passes one negative sine-wave. At the output of the code generator 55/56 / units in the codes of odd samples of the string are represented by positive sine waves, in the codes of even samples of the string are represented by negative sine waves. Zeros appear to be the absence of both. The output signal from blocks 55, 56 appears to be full or incomplete sinusoids of a frequency of 103.68 MHz with a stability of 10 ^-7 . These signals modulate carrier frequencies. Timing diagrams of the operation of blocks 56, 55 in Fig.22. Each sound code consists of two parcels of 8 bits. The first premise / the first half of the code is 1–8 bits / goes to the first inputs of AND elements of block 102 and through the OR elements 103, 94 goes to the input of the output key 95, the second premise 9–16 bits goes to the first inputs of AND elements of block 105 and through the elements OR 106, 99 is fed to the input of the output key 100. The keys 108, 100 are designed to separate the codes of the video signals from the sound codes. The key 108 is opened by the signal from the first output of the decoder 111 at the moment 480 of the line sampling pulse / Fig. 4/ and remains open from the first to 476 line sampling pulse. At the moment 476 of the pulse from the second output of the decoder 111, the signal closes the key 108 and opens the key 109. At the moments 477, 478, 479 pulses of the line, three sound codes arrive at the inputs of the output keys 95, 100. At the moment of the 480 pulse / count 959 / the third input OR element 94, an SSI code is received from block 58, triggered by a signal U _p / 479 pulse / from the third output of the decoder 111. At the last 540th line of each left frame of the stereo pair, block 59 generates a line / 960th sample / SIS code at the moment of pulse 480 to the third input of the OR element 99. The start signal U _p for block 59 gives a counter 60 pulses . The operation error of the code generator 57 is similar to the operation of block 55 and is simpler; it does not participate in the formation of sound codes.

On the receiving side, three radio signals are received by blocks 113, 124, 135 (Fig. 9/), which are channel selectors of the corresponding ranges with electronic tuning. Each unit includes an input circuit, a radio frequency amplifier, and a mixer [9 p.132]. The band-pass filter of the radio frequency amplifier in each range is tuned by the bias voltage from the control unit 112 / channel selection /. The radio frequency signal through the communication loop is fed to the mixer, two frequencies equal to the first and second carrier frequencies of the transmitter 65, which are necessary for the detection of a single-band signal [10 p.146], are supplied from the synthesizer 163 frequencies / outputs 5 and 6 /. The signal from the mixer, which is the output signal of the block 113/124, 135 /, is fed to the input of the amplifier 114/125, 136 / of the radio frequency, where it is amplified to the required value and fed to the input of the bipolar amplitude detector 115/126, 137 /. The second inputs of block 163 are connected to the second group of outputs of block 112, when the transmission channel is turned on, the signal from the corresponding output of block 112 enters block 163 and determines the output of two frequencies from it to the third inputs of blocks 113, 124, 135. Bipolar amplitude detectors 115-126, 137 are made according to the scheme in Fig.15. Diode D1 selects the positive envelope of the modulating signal / Fig. 22/. The diode D2 from the modulating one selects the envelopes of the positive half sine / unit symbols in the codes of odd samples /, the diode D3 from the modulating one selects the envelopes of the negative half sine / unit symbols in codes of even samples /. From the first output of the bipolar amplitude detector, the detected positive half-sine waves with a frequency of 103.68 MHz are fed to the input of the first driver 116 pulses / 127, 138 /, from the second output the detected negative half-sinusoids are fed to the input of the second driver 117/128, 139 / pulses. The pulse shapers are made according to the scheme of an asymmetric trigger with emitter coupling [11 p.209], which forms rectangular pulses from harmonically changing signals. The pulses have the same polarity and duration equal to the pulse duration in the codes on the transmitting side. Units in codes are now represented by the presence of momentum, zeros by their absence. After turning on the power of the receiving side, all keys are in the closed state. The operating procedure is determined by control signals from the channel for generating control signals. The decisive role belongs to block 162 allocation of sync pulses. The condition for the appearance of the clock pulse of the SIS from block 162 is the simultaneous arrival at the counting inputs of the block 162 of pulses of three codes of eight units 11111111. In all codes, usually except for the SSS, there will always be one or more zeros, and even more so in three codes at the same time. With the arrival of three codes from one unit 11111111, block 162 will output a horizontal sync pulse at the output, their frequency is 27 kHz. The SSI pulse from block 162 is supplied to blocks 163, 167, 164, 121, 132, 143. The SSI pulse adjusts the frequency in the frequency synthesizer 163 to the frequency and phase of the master oscillator on the transmitting side, the natural frequency stability of the synthesizer is 163 frequencies 10 ^-6 . The synthesizer 163 frequency outputs from the first output pulses of 6.48 MHz sampling line, from the second - 103.68 MHz clock, the third - the pulses 81 kHz sampling rate U _vyd sound, output from the fourth - 12.96 MHz sampling pulses codes with fifth and sixth - sinusoidal oscillations of two carrier frequencies to the third inputs of blocks 113, 124, 125, from the seventh output - pulses of 25.92 MHz double frequency sampling codes, from the eighth - pulses of a frame frequency of 50 Hz, from the ninth - pulses of 54 kHz double lowercase frequency. Codes R _{p of} odd samples of the line from the output of the pulse shaper 116 and codes R _{l of} even samples of the line from the shaper 117 of the pulses are received in sequential form in the registers 118, 119, filling the bits which take a parallel form. Similar processes go through the codes G _p , G _l and V _p , V _l , filling in the registers 140, 141 and 129, 136. The issuance of codes from the registers to blocks 120, 142, 131 is performed by 6.48 MHz pulses from the first output of block 163, they the registers are reset to zero. The code processing units 120, 142, 131 are identical and double the samples in each row from 960 to 1920 to obtain intermediate / average / samples between each passing code and the next one. Blocks add up the previous and next codes and divide the sum code into two. The operation of the block in figure 10. The code of the first sample of the line from register 118 is supplied in parallel to the inputs 1-8 of the registers 172, 173, the code of the second sample of the line is sent to the inputs of the first block 171 delay elements, which delays the even code by 77 ns, restoring the sequence of the second sample after the first. From block 171, the code is sent in parallel to the inputs of registers 174, 175. Each code is used twice: the first time as the next, the second time as the previous one. Therefore, four registers are applied. After turning on the power in the bits of the registers zeros. With the arrival of the first pulse of 12.96 MHz to the input of flip-flop 170 outputs this first U _vyd1 signal simultaneously outputs from register 173 "code 0" / of zeros / to the first inputs to the adder 179, the register 174 "code 0" in the sixth register 178 to store the code "code 0" 77 ns in it and through diodes to the second inputs of the adder 179. The output signals and reset the registers.

And in the registers 172, 173 at the same time the first code "code 1" is received. The adder produces the addition of "code 0 + code 0". An adder made of K555IM6 microcircuits [12 p. 258] with an addition time of 24 ns. With the advent of the flip-flop 170 of the second pulse it enters U _vyd signal to the adder 179, outputs from the code amount and it resets the adder bits. When the sum code is transferred from the adder to the second delay block 176, the sum code is divided by two. The division is performed without time, by shifting the sum code so that the least significant bit of the sum code / is discarded, as when dividing the decimal number by ten /. The shift is performed by connecting the outputs of the adder 179 to the inputs of the second block 176 of delay elements:

Bit 0 means transfer to the high bit when the sum of codes. Doubling the samples in the line from 960 to 1920 reduces the code period by half, which is 38.5 ns / 10 /. The addition process takes 24 ns, so block 176 must still delay the code by 14.5 ns / 38.5-24 /. After the code arrives at adder 179 to exit block 176, the code follows 38.5 ns, which is required. The first code from block 176 is code N

With the arrival of the second pulse in the trigger 170 from its second output, the signal U _vy2 simultaneously outputs from the register 178 "code 0" to the output, which is a code No. 2 "code 0", from the register 175 "code 0" to the adder 179 and from the register 172 "code 1" to the register 177 and through diodes to the adder for addition. At the same time, registers 174, 175 from block 171 are filled with the code "code 2". Registers 177 and 178 carry out the storage of codes for a time of 77 ns, of which the first half of the storage time 38.5 ns is accounted for by addition in the adder and delay by block 176, so each code issued from registers 177 or 178 follows the code from block 176 through 38.5 ns Issued by the signal U _vyd2 from the register 175 "code 0" and from the register 172 "code 1" are summed in the adder 179, when the sum code is sent to block 176, it is divided into two, code No. 3 follows from the output of block 176

With the arrival of the third pulse in trigger 170, the signal from its first output, _Ud3, simultaneously outputs code No. 4 "code 1" from register 177 to output, from code 173 from register 173 to adder, from code 174 from code 174 to register 178, and through diodes to the adder. Registers 172 and 173 are filled with the following code "code 3". The adder 179 performs the addition of "code 1 + code 2", then division by two, and from the output of block 176 to the output is the code number 5

идет на выход. With the arrival of the 4th pulse in the trigger 170 from its second output, the signal U _vy4 simultaneously generates code No. 6 "code 2" from register 178, from code 175 "register 2" to the adder, from code 172 "code 3" to register 177, and through diodes to the adder 179. Registers 174, 175 from block 171 are filled with the code "code 4", in parallel there is addition in the adder "code 2 + code 3", division by two, and code No. 7

goes to the exit.

идет на выход. With the arrival of the fifth pulse in the trigger 170 from its first output, the signal U _vyd5 simultaneously generates code 8 "code 3" from register 177, from code 173 from register 173 to adder, from code 174 from register 174 to register 178 and through diodes into the adder. Registers 172, 173 are filled with the following code "code 5". At the same time, the addition of "code 3 + code 4", division by two, and code No. 9

goes to the exit.

With the arrival of the 6th pulse in the trigger 170 and subsequent processes are repeated. The outputs of blocks 177, 176, 178 are bitwise combined and are the outputs of block 120. From the outputs of blocks 120, 131, 142, line codes with a doubled sampling frequency of 25.92 MHz arrive at the inputs of the corresponding first delay blocks 121, 143, 132, at the first inputs adders 122, 144, 133 and second delay blocks 123, 145, 134. Then there is the process of doubling the lines in the frame, for this it is necessary to delay the codes of the current line relative to the next line for the line duration of 37 μs. The delay is performed by the first delay blocks 121, 143, 132 (Fig. 11/). When the frame is scanned on the transmitting side, the voltage of the scans of the odd lines relative to the even lines performs a counter-scan of the lines. With the arrival of a 50 Hz pulse at the first input of the And 180 element and at the second input of the SSI pulse of 27 kHz from the output of the And element, the signal opens the key 181, which transmits 25.92 MHz pulses to the 183 pulse distributor. Clock pulses from block 183 sequentially from the first to the 1920th outputs are fed to the first / clock / inputs of the bits of eight registers 185. Codes signals are sent to 1-8 information inputs of block 121. The signals of the first bits of the codes are fed to the second inputs of the bits of the first register 185 ₁ , the signals of the second bits of codes are fed to the second inputs of the bits of the second register 185 ₂ , etc., the signals of the eighth bits of the codes are fed to the second inputs of the eighth register 185 ₈ . Starting from the period of the second row, 1920 codes of the first row from the registers 185 _1-8 are sequentially output to the adder 122 and at the same time, the freed-up bits of the registers are filled with the signals of the digits of the codes of the next row. The issuance of codes is performed by the leading edge of the clock pulses; the input of the signal signals is entered by the same clock pulse. Since the scan of the second line goes counter to the first, the issuance of codes of the first line from registers 186 goes in the opposite order: it starts from the 1920th discharge to the first. This is accomplished by a second pulse distributor 184, the outputs of which are connected to the first inputs of the bits of the registers 185 in the reverse order from the 1920th discharge to the first. In the period of the third line, the codes are issued again from the pulse distributor 183, starting from the first bit of the registers 185.

Adders 122, 144, 133 perform the addition of codes of the same samples of the current and delayed lines. Codes of the current line from block 120/142, 131 / come to the first inputs of adders, codes delayed by 37 μs from block 121/143, 132 / come to the second inputs. Adders 122, 144, 133 are identical, made of K555IM6 microcircuits with an addition time of 24 ns. The division of the sum code into two is performed by the corresponding connection of the outputs of the adder to the inputs of its drive 146/148, 150 / frame codes, similarly to blocks 179 and 176 in FIG. 10. The second delay blocks 123, 145, 134 delay the codes by 24 ns, for the time of addition by the adders 122, 144, 133, so that the codes of the current and intermediate lines arrive at the frame code stores synchronously. Codes of the current 540 lines of signal R from block 123 enter the drive 147 frame codes, codes of intermediate 540 lines of signal R from block 122 go to the drive 146 codes, codes of the current 540 lines of signal G from block 145 go to the drive 149 frame codes, intermediate codes 540 lines of signal G from block 144 are sent to drive 148 frame codes, codes of the current 540 lines of signal B are sent from block 134 to drive 151 codes, codes 540 of intermediate lines of signal B from block 133 are sent to drive 150 of frame codes.

The operation of blocks 186 _1-540 registers, Fig.13 and 14.

The signals of the bits of the codes are sent in parallel to the third inputs of the bits of the registers 190 _1-8 . Filling the registers with line codes begins with the opening of a 50 Hz pulse of the first key 187, which transmits pulses U _d 25.92 MHz to the input of the pulse distributor 189. The clock pulses from the outputs of block 189 are sequentially supplied to the first control inputs of the bits of eight registers 190. The signals of the first bits of codes are sent to the bits of the first register 190 ₁ , etc., and the eighth bits of codes are sent to the bits of the eighth register 190 ₈ . Upon filling in the registers 190, the signal from the last 1920th output of block 189 closes the first key and, as a control output signal, opens the key 187 in the second block of registers 186 ₂ , the registers of which are similarly filled with the codes of the second line. Thus, for a frame period of 20 ms, the registers 190 of all blocks 186 _{1-540 are sequentially populated} . After filling in the registers 190 in all blocks 186, the output signal from the last block 186 ₅₄₀ opens in 540 blocks 186 the second keys 188, which pass one pulse U _output 54 kHz, which simultaneously simultaneously sends out all frame codes from all blocks 186 of the code storage units to blocks 152- 157 the formation of control signals and resets the bits of the registers 190 to receive codes for the next frame. Each drive of frame codes from 146-151 has from the 1st to 8294400 outputs / 1920 × 8 × 540 /, which are connected to the same inputs in each of the blocks 152-157 of the shapers of control signals, each of which has from the first to 1036800 / 1920 × 540 / code-to-radiation-duration converters. The outputs of blocks 152-157 6220800/1036800 × 6 / are connected to the same inputs 6220800 in the LED screen 158. Due to the large number of connections 49766400/1920 × 8 × 540 × 6 / from six drives 146-151 frame codes to six blocks 152-157 of the formation of control signals and from them to the LEDs 6220800/1920 × 1080 × 3 / of the screen 158, the best option for their reliable operation is the execution of frame code drives and control signal generation blocks on the back of the flat-panel screen in a single, non-separable design.

The operation of the stereo system.

The photoelectric converter 1 generates analog video signals of the right and left frames of the stereo pair, which are converted by the 52-54 ADC into 8-bit codes with a sampling rate of 12.96 MHz. Shapers 55, 56, 57 codes form consecutive codes from parallel codes, replacing in them representations of units from pulses to positive and negative half-sinusoids of a single frequency of 103.68 MHz. On the transmitting side, 540 lines are encoded with 960 samples each. Line scan line by line without reverse moves. Frame rate 50 Hz, stereo pair frequency 25 Hz, stereo pair from the right and left frames. The information of the codes of the right and left frames is transmitted by three channels of the transmitter 65. The receiving side receives three radio signals by three paths of receiving and processing codes of video signals, amplifies the radio signals, detects them, selects the horizontal sync pulses of the SSI and sync pulses of the SIS stereo pairs, the frequency synthesizer 163 reproduces two carrier frequencies. Representation of units in codes returns to impulses. The signal codes R, G, B are distributed over their channels, in which doubling of samples in each row and doubling of rows in the frame are performed, i.e. NDTV video mode is formed: 1920 × 1080 × 50 Hz. The first control inputs of drives 146-151 frame codes receive clock pulses of a frequency of 50 Hz frames from the 8th output of block 163, the second control inputs receive pulses of 54 kHz from the ninth output of block 163 and the 3 control inputs receive pulses U _{d of} sampling 25 , 92 MHz from the 7th output. During the first frame, the registers 190 of the blocks 186 _1-540 are filled with the codes of the first frame. Each block 186 focuses on one line of code. During the frame period, six frame stores focus all frame codes. With the end of the frame period, the control output signals from blocks 186 ₅₄₀ are fed to the fourth control inputs of blocks 186 and give out all of the frame codes synchronously and parallel to blocks 152-157, whose code-to-radiation-time converters control signals, respectively, of the code values, determine the radiation duration their LEDs in the frame period. When forming an image at the same time with all the elements of the matrixes of the screen 158, there is no need for line and frame scans. Image formation of the entire frame allows the viewer to perceive the image on the screen according to the nature of human vision. The viewer perceives a three-dimensional image through 3D glasses. The control signals for the IR transmitter 159 / Fig. 9/ are the pulses of the SIS stereopairs from block 167. The technical characteristics of the claimed system in the table. The first 168 and second 169 channels reproduce stereo sound. The clock from block 162 opens the key 164 / 9.9 /, transmitting 6.48 MHz pulses to the counter 165 pulses. With the arrival of pulse 476, the decoder 166 generates a signal from the first output, opening the corresponding keys in channels 168, 169, passing three sound codes each, which are converted into analog signals and reproduced by loudspeakers. Upon receipt of the 479th pulse of line sampling in the counter 165, the decoder 166, with the signal from the second output, closes the keys in channels 168, 169, resets the counter 165 and closes the key 164. Each of the sound reproduction channels contains the corresponding blocks that convert sound codes to analog signals, amplifiers power and loudspeakers. The execution of the receiving side is proposed to be performed in two parts: first, include the paths for receiving and processing codes with signal channels R, G, B, a channel for generating control signals and sound channels, in the second part, include six drive codes for the frame, six blocks of drivers of control signals and LEDs -Screen. The second part is performed in a single, non-separable design.

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12. Digital integrated circuits. Directory. Minsk, 1991, p. 258.

Table. Specifications Values Transmission side   Signal Code Transmission R _p , R _l 1347.84 MHz upper side. f ₁ In _p , in _l 1140.48 MHz lower side. f ₁ G _p , G _l 1036.8 MHz upper side. f ₂ Occupied bands on the air 270 Hz, 228 Hz, 208 Hz. System Clock 103.68 MHz The number of encoded lines / samples per line 540/960 Video Sampling 12.96 MHz Frame rate / stereo pair frequency 50 Hz / 25 Hz Line frequency 27 kHz Line / Frame Duration 37 μs / 20 ms Video coding 255 levels, 8 digits Transmit Side Video Mode 960 × 540 × 50 Hz Receiving side Playable format NTDV 1920 × 1080 × 50 Hz Number of lines / samples per line 1080/1920 Line Rate / Frame Rate -/50 Hz Video Sampling 25.92 MHz Frame Resolution 2073600/1920 × 1080 / The number of LEDs used is three 6,220,800 pieces colors: R, G, B The size of the flat panel LED screen 1920 × 1080 mm, 86 ". Diagonal 2203 mm. Frame format 16: 9 3D image perception through 3D glasses

Claims (1)

Stereo TV system,  containing the transmitting side,  including photoelectric converter,  the first,  second,  third analog-to-digital converters (ADC),  the first and second ADCs of the sound signal,  to the information inputs of which sound signals are given,  serially connected sine oscillation generator and frequency synthesizer,  the first,  second and third code generators,  first and second self-propelled pulse distributors,  pulse counter  trigger,  first and second keys and a radio signal transmitter,  containing three channels  the first channel includes a series-connected amplifier of the first carrier frequency,  the input of which is connected to the eighth output of the frequency synthesizer,  amplitude modulator and output amplifier,  the second channel includes a series-connected amplitude modulator,  the first input of which is connected to the output of the amplifier of the first carrier frequency,  and an output amplifier,  the third channel includes a series-connected amplifier of the second carrier frequency,  whose input is connected to the ninth output of the frequency synthesizer,  amplitude modulator and output amplifier,  the first trigger output is connected to the first control input of the first key and to the second control input of the second key,  the second trigger output is connected to the second control input of the first key and to the first control input of the second key,  the first and second information inputs of the first code generator are connected to the outputs of the first ADC and the first ADC of the sound signal,  the first and second information inputs of the second code generator are connected to the outputs of the second ADC and the second ADC of the sound signal,  the first information input of the third code generator is connected to the output of the third ADC,  third information inputs of the first,  the second shaper codes and the second information input of the third shaper codes are connected to the output of the first self-propelled pulse distributor,  the fourth information inputs of the first and second code shapers and the third information input of the third code shaper are connected to the output of the second self-propelled pulse distributor,  the control input of which is connected to the output of the second discharge of the pulse counter,  the counting input of which and the control input of the first self-propelled pulse distributor are combined and connected to the second output of the second code generator,  the first output of which is connected to the second input of the amplitude modulator of the third channel of the radio signal transmitter,  the output of the first code generator is connected to the second input of the amplitude modulator in the first channel of the radio signal transmitter,  the output of the third code generator is connected to the second input of the amplitude modulator in the second channel of the radio signal transmitter,  the first output of the frequency synthesizer is connected to the control inputs of the first,  second and third code generators,  the second output of the frequency synthesizer is connected to the second control inputs from the first to third code generators and to the first control inputs of the first and second ADCs of the sound signal,  the third output of the frequency synthesizer is connected to the second control inputs of the first and second ADCs of the sound signal,  the fourth output of the frequency synthesizer is connected to the third control inputs from the first to third code generators,  the fifth output is connected to the fourth control inputs of the first and second code generators,  to the third control inputs of the first and second ADCs of the sound signal and to the first control input of the frame scan unit,  the second control input of which is connected to the sixth output,  the control input of the pulse counter is also connected to it,  the seventh output of the frequency synthesizer is connected to the input of the horizontal scanning unit of the photoelectric converter,  which contains the first lens,  connected in series to the first amplifier and the first piezoelectric deflector with a reflector at the end,  located in the focal plane of the first lens,  the first source of positive reference voltage  the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector,  a second source of negative reference voltage,  the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector,  connected in series to a second amplifier and a second piezoelectric deflector,  the free end of which of two faces at an appropriate angle to each other,  each face has its own reflector,  the first reflector of the second piezoelectric deflector is optically connected to the reflector of the first piezoelectric deflector,  a third source of positive reference voltage,  the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector,  a fourth source of negative reference voltage,  the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector,  contains a second lens,  located to the left of the first lens at an appropriate distance and whose optical axis is parallel to the optical axis of the first lens,  connected in series to a third amplifier,  the first input of which is connected to the first input of the first amplifier,  and a third piezoelectric deflector with a reflector at the end,  located in the focal plane of the second lens and optically connected to the second reflector of the second piezoelectric deflector,  fifth source of positive reference voltage  the output of which is connected to the second inputs of the third amplifier and the third piezoelectric deflector,  sixth source of negative reference voltage,  the output of which is connected to the third inputs of the third amplifier and the third piezoelectric deflector,  contains the first and second dichroic mirrors,  arranged sequentially one after another and against the first reflector of the second piezoelectric deflector,  the first,  second and third micro lenses,  the first,  second,  third photodetectors,  the first,  second,  third preamplifiers,  the input window of the first photodetector is optically connected through the first micro lens and the first dichroic mirror with the first reflector of the second piezoelectric deflector,  the input window of the second photodetector is optically connected through the second micro lens and through both dichroic mirrors to the first reflector of the second piezoelectric deflector,  the input window of the third photodetector through the third micro lens,  the second dichroic mirror and through the first dichroic mirror is optically connected to the first reflector of the second piezoelectric deflector,  exits from the first,  second  the third photodetectors are connected respectively to the inputs of the first,  second  third preamplifiers,  whose outputs are the first,  second  the third outputs of the photoelectric converter,  which contains the third and fourth dichroic mirrors,  located sequentially one after another and against the second reflector of the second piezoelectric deflector,  fourth,  fifth,  sixth micro lens,  fourth,  fifth,  sixth photodetectors,  fourth,  fifth,  sixth preamplifiers,  the input window of the fourth photodetector is optically connected through the fourth micro-lens and the third dichroic mirror to the second reflector of the second piezoelectric deflector,  the input window of the fifth photodetector is optically connected through the fifth micro-lens and through both dichroic mirrors to the second reflector of the second piezoelectric deflector,  the input window of the sixth photodetector is optically connected through the sixth micro lens,  a fourth dichroic mirror and through a third dichroic mirror with a second reflector of the second piezoelectric deflector,  fourth exits  fifth  the sixth photodetectors are connected respectively to the inputs of the fourth,  fifth  sixth preamplifiers,  whose outputs are fourth,  fifth  sixth outputs of the photoelectric converter,  the frame scanning unit of the photoelectric Converter contains a series-connected element And,  master oscillator and summing amplifier,  the second input of which is connected to the first input of the AND element,  the control input of the summing amplifier is connected to the output of the element And,  the output of the summing amplifier is the output of the frame scan unit and is connected to the first input of the second amplifier,  the first and second inputs of the element And are the inputs of the frame scan unit,  the first,  second,  the third ADCs are identical,  each contains a series-connected amplifier and a piezoelectric deflector with a reflector at the end,  source of positive reference voltage  the output of which is connected to the second inputs of the amplifier and piezoelectric deflector,  negative reference voltage source  the output of which is connected to the third inputs of the amplifier and piezoelectric deflector,  emitter from a pulsed LED,  slit diaphragm and micro lens,  series-connected line of multi-element photodetector and encoder,  the outputs of which are the outputs of the ADC,  the control input is the pulse LED input,  the first and second code generators are identical,  each contains a serially connected trigger and a switching unit,  the inputs of which are the first information input of the code generator,  and three channels  the first and second channels are identical,  their inputs are connected to the corresponding outputs of the switching unit,  and the outputs of the three channels are combined,  the first channel includes a series-connected block of elements AND,  the first and second elements OR and the output key,  and a self-propelled pulse distributor,  the second channel includes a series-connected block of elements AND,  the third and fourth elements OR and the output key,  and a self-propelled pulse distributor,  the first inputs of the block of elements AND are connected to the corresponding outputs of the switching block,  the second inputs of the block of elements And are connected to the outputs of the self-propelled pulse distributor of its channel,  the outputs of the output keys are combined and are the first output in the first and second code generators,  the third channel includes two blocks of AND elements,  the inputs of which are the second information input,  fifth and sixth elements OR,  the output of the fifth OR element is connected to the second input of the second OR element in the first channel,  the output of the sixth OR element is connected to the second input of the fourth OR element in the second channel,  and two self-propelled pulse distributors,  the outputs of which are connected to the second inputs of the corresponding blocks of AND elements,  includes the first and second keys,  and series-connected pulse counter and decoder,  two outputs of which are connected respectively to the first and second control inputs of the first and second keys,  in the second code generator, the decoder also has a third output,  which is the second output of the second code generator,  connected to the counting input of the pulse counter and to the input of the first self-propelled pulse distributor of the transmitting side,  the output of the first key is connected to the inputs of the self-propelled pulse distributors in the first and second channels,  the output of the second key is connected to the inputs of the self-propelled pulse distributors in the third channel,  the third and fourth information inputs of the code generators are the third inputs of the second and fourth OR elements,  the first control input is the trigger input,  the second is the combined inputs of the keys and the counting input of the pulse counter,  the third is the combined signal inputs of the output keys,  the fourth is the control input of the pulse counter,  the third code generator contains a serially connected trigger and a switching unit,  and two identical channels,  the channel inputs are connected to the outputs of the switching unit,  and their outputs are combined and are the output of the third code generator,  the first channel includes a series-connected block of elements AND,  the first and second elements OR and the output key,  and a self-propelled pulse distributor,  the second channel includes a series-connected block of elements AND,  the third and fourth elements OR and the output key,  and a self-propelled pulse distributor,  the first inputs of the blocks of elements AND are connected to the corresponding outputs of the switching unit,  the second inputs of the blocks of elements AND are connected to the outputs of the self-propelled pulse distributor of their channel,  the first information input is the inputs of the switching unit,  the second and third information inputs are the second inputs of the second and fourth elements OR,  the first control input is the trigger input,  the second is the combined inputs of self-propelled pulse distributors,  the third is the combined signal inputs of the output keys,  the combined output of which is the output of the third code generator,  and containing the receiving side,  including antenna  control unit (channel selection),  the first,  second and third paths for receiving and processing video signal codes,  the inputs of which are connected to the antenna,  channel for generating control signals,  a video information display device and two sound reproduction channels,  the first path for receiving and processing codes of video signals contains a series-connected unit for receiving a radio signal,  whose first input is connected to the antenna,  the second group of inputs is connected to the first group of outputs of the control unit,  radio frequency amplifier and bipolar amplitude detector,  first and second pulse shapers,  connected respectively to the first and second outputs of the bipolar amplitude detector,  and the signal channel R,  containing the first and second registers of the signal R,  connected respectively to the outputs of the first and second pulse shapers,  series-connected code processing unit,  the first and second information inputs of which are connected to the outputs of the first and second registers of the signal R,  first delay block and adder,  and the second block of delays,  the inputs of which and the first inputs of the adder are connected to the outputs of the code processing unit,  the second inputs of the adder are connected to the outputs of the first block of delays,  the second path for receiving and processing codes of video signals contains a series-connected unit for receiving a radio signal,  whose first input is connected to the antenna,  the second group of inputs is connected to the first group of outputs of the control unit,  radio frequency amplifier and bipolar amplitude detector,  first and second pulse shapers,  connected to the first and second outputs of a bipolar amplitude detector,  and signal channel B,  including the first and second registers of signal B,  connected to the outputs of the first and second pulse shapers, respectively,  series-connected code processing unit,  the first and second information inputs of which are connected to the outputs of the first and second registers of signal B,  first delay block and adder,  and the second block of delays,  the inputs of which and the first inputs of the adder are connected to the outputs of the code processing unit,  the second inputs of the adder are connected to the outputs of the first block of delays,  the third path for receiving and processing codes of video signals contains a series-connected unit for receiving a radio signal,  whose first input is connected to the antenna,  the second group of inputs is connected to the first group of outputs of the control unit,  radio frequency amplifier and bipolar amplitude detector,  first and second pulse shapers,  connected respectively to the first and second outputs of the bipolar amplitude detector,  and signal channel G,  including the first and second registers of the signal G,  connected to the terminals of the first and second pulse shapers,  series-connected code processing unit,  the first and second information inputs of which are connected to the outputs of the first and second registers of the signal G,  first delay block and adder,  and the second block of delays,  the inputs of which and the first inputs of the adder are connected to the outputs of the code processing unit,  the second inputs of the adder are connected to the outputs of the first block of delays,  the channel for generating control signals includes serially connected block selection horizontal sync pulses (SSI),  frequency synthesizer  key,  pulse counter and decoder,  three inputs of the SSI selection block are connected to the outputs of the first pulse shapers in the first,  the second and third paths for receiving and processing codes of video signals,  the output of the block is connected to the first control input of the frequency synthesizer,  to the first control input of the key and to the second control inputs of the first delay blocks in the signal channels R,  G  AT,  the second group of inputs of the frequency synthesizer is connected to the second group of outputs of the control unit,  the first output of the frequency synthesizer is connected to the signal input of the key and to the first control inputs of the signal registers R,  G  AT,  the second output is connected to the second (clock) control input of the signal registers R,  G  In and to the third control inputs in the first and second channels of sound reproduction,  to the fourth control inputs of which the third output of the frequency synthesizer is connected,  the fourth output of which is connected to the control inputs of the code processing units in the signal channels R,  G  AT,  the fifth output of the frequency synthesizer is connected to the third inputs of the blocks of the reception of the radio signal in the first and second paths of the reception and processing of codes of video signals,  the sixth output is connected to the third input of the radio signal receiving unit in the third path of receiving and processing video signal codes,  the seventh output of the frequency synthesizer is connected to the third control inputs of the first delay blocks and to the first control inputs of the adders in the signal channels R,  G  AT,  the eighth output is connected to the first control inputs of the first delay blocks in the signal channels R,  G  AT,  the first output of the decoder is connected to the first control inputs in the first and second channels of sound reproduction,  its second output is connected to the control input of the pulse counter,  to the second control input of the key and to the second control inputs in the first and second channels of sound reproduction,  the first and second information inputs of which are connected respectively to the outputs of the first and second pulse shapers in the first and second paths of the reception and processing of video signal codes,  code processing units are identical,  each includes a trigger,  whose input is the control input of the block,  first to sixth registers,  the first and second blocks of delay elements,  adder and 16 diodes,  the control input of the adder is connected to the input of the trigger,  the information inputs of the first and second registers are bitwise combined,  the second information input of the code processing unit is the inputs of the first block of delay elements,  the outputs of which are connected bitwise combined inputs of the third and fourth registers,  the first trigger output is connected to the control inputs of the fifth,  second  third registers,  the second trigger output is connected to the control inputs of the sixth,  the first  fourth registers,  the outputs of the first register are connected to the inputs of the fifth register and through diodes to the first inputs of the adder,  to which the outputs of the second register are connected,  the outputs of the third register are connected to the inputs of the sixth register and through diodes to the second inputs of the adder,  to which the outputs of the fourth register are connected,  the adder outputs are connected to the inputs of the second block of delay elements,  the outputs of which are bitwise combined with the outputs of the fifth and sixth registers and are outputs of the code processing unit,  the first delay blocks are identical,  each includes a series-connected element And,  first and second keys,  first and second pulse distributors,  eight registers  each of which contains the number of bits according to the number of samples in a row,  information inputs are bitwise combined second inputs of bits of eight registers,  outputs are bitwise combined outputs of bits from the first to eighth registers,  the first and second control inputs are the first and second inputs of the And element,  the third control input is the combined signal inputs of the first and second keys,  the output of the AND element is connected to the first control input of the first key and to the second control input of the second key,  the output of the first key is connected to the input of the first pulse distributor,  the outputs of which are connected in series to the first (clock) inputs from the first to the last bits from the first to eighth registers,  the last output (1920) of the first pulse distributor is connected to the second control input of the first key and to the first control input of the second key,  and through the diode to the first inputs of the last bits of eight registers,  the output of the second key is connected to the input of the second pulse distributor,  the outputs of which are sequentially from the first to the last connected to the first inputs of the bits of eight registers in sequence from the last bit of the registers to the first,  the last output of the second pulse distributor is connected through a diode to the first inputs of the first bits of eight registers and through a diode connected to the first control input of the first key and to the second control input of the second key,  characterized in  that on the transmitting side the frequency synthesizer has a tenth output of frame rate pulses,  connected to the trigger input,  and the third to sixth keys are entered on the transmitting side,  the first control inputs of the third and fifth keys and the second control inputs of the fourth and sixth keys are connected to the first output of the trigger,  the second control inputs of the third and fifth keys and the first control inputs of the fourth and sixth keys are connected to the second output of the trigger,  on the receiving side are entered from the first to the sixth drive code frame,  the first to sixth blocks of the formation of control signals,  the video information display device is represented by a flat panel LED screen (SD screen),  on the upper part of the body of which an IR transmitter is located,  introduced 3D glasses with an IR receiver on the frame of 3D glasses,  the input windows of which, when used, are located against the output window of the IR transmitter,  in the channel for the formation of control signals, a block for isolating stereo clock pulses (SIS) is introduced,  the output of which is connected to the input of the PC transmitter,  and the first one  the second and third inputs of the SIS isolation block are connected to the outputs of the second pulse shapers in the first and third paths of receiving and processing video signal codes and its fourth input is connected to the output of the horizontal sync pulse allocation block (SSI),  frame code drives are identical,  each includes blocks of registers according to the number of half lines of the reproduced frame,  the information input of each drive codes codes are bitwise combined 1-8 inputs of register blocks,  information inputs of the first,  third  fifth drive codes codes are connected to the first to eighth outputs of the adders, respectively, in the signal channels R,  G  AT,  information inputs of the second,  the fourth  the sixth drive codes of the frame are connected to 1-8 outputs of the second delay blocks, respectively, in the signal channels R,  G  AT,  the first control input of the frame code storage device is the first control input of the first block of registers,  the second control input is the combined second control inputs of the register blocks,  the third is the combined third control inputs of the register blocks,  the first control inputs of the drive codes of the frame are combined and connected to the eighth output of the frequency synthesizer,  their second control inputs are combined and connected to the ninth output of the frequency synthesizer,  third control inputs are combined and connected to the seventh output of the frequency synthesizer,  each control output of the previous block of registers is the first control input of each subsequent block of registers,  the control output of the last block of registers (540) is connected in parallel to the fourth control inputs of all blocks of registers,  the outputs of each drive code frames are the outputs of all blocks of registers,  connected to the inputs of its block forming control signals,  register blocks are identical,  each includes the first and second keys,  pulse distributor and eight registers,  the information inputs of the register block are bitwise combined third inputs of the bits of eight registers,  the outputs of all bits of the eight registers are the outputs of the register block,  the first control input is the first control input of the first key,  the second is the signal input of the second key,  the third is the signal input of the first key,  fourth - the first control input of the second key,  connected to the control output of the last block of registers,  the output of the first key is connected to the input of the pulse distributor,  the outputs of which are connected in series from the first to the last in parallel with the first control inputs of the bits of eight registers,  the last output is connected to the second control input of the first key and is the control output of the register block,  the output of the second key is connected in parallel to the second control inputs of all bits of the eight registers and to the second control input of the second key,  control signal generating units are identical,  each includes a pulse generator and, according to the number of samples per line (1920) and the number of frame lines provided (540), the code-to-radiation-time converters,  which are identical and each includes a series-connected first key,  subtracting pulse counter  decoder and second key,  the output of which is the output of the code-to-radiation duration converter,  and includes a power source,  the output of which is connected to the signal input of the second key,  the signal inputs of the first keys of all converters are connected to the output of the pulse generator,  the control input of which and the first control inputs of the first and second keys are combined and connected to the control input of the control signal generation unit,  which is connected to the eighth output of the frequency synthesizer,  the output of each first key,  connected to the counting input of the subtracting pulse counter,  the decoder output is connected to the second control inputs of the first and second keys of its code-to-radiation duration converter,  information inputs of which are from the first to eighth information inputs of a subtracting pulse counter,  and the information inputs of the control signal generation unit are the information inputs of all the code-to-radiation-time converters,  the outputs of which are the outputs of the control signal generation unit,  connected to the inputs of the LEDs of the respective emitting cells,  in the code processing unit, the bitwise combined information inputs of the first and second registers are the first information input of the block,  the block allocation of stereo pulses includes the first,  second,  third pulse counters,  whose counting inputs are the first,  second  third information inputs of the block,  the first,  second,  the third elements are NOT,  the inputs of which are connected respectively to the inputs of the first,  second  third pulse counters,  the first,  second,  third elements And,  the inputs of the first element And are connected to the outputs of the first and second pulse counters,  the inputs of the second element And are connected to the outputs of the first element And and the third pulse counter,  the inputs of the third AND element are connected to the output of the second AND element and to the fourth information input of the block,  the output of the third element And is the output of the block,  connected through a diode and to the combined outputs of the elements NOT  which are connected to the control inputs of the pulse counters,  a flat-panel LED screen consists of screen glass and matrix elements according to the number of screen resolutions (1920 × 1080),  each matrix element includes three emitting LED cells (LED cells),  each of which contains a sequentially located white LED and a color filter of one of the primary colors (R,  G  AT),  three radiating LED cells of the primary colors in the matrix element form a triangle,  screen glass according to the number of matrix elements has corresponding recesses,  in which there are three LED cells of the primary colors,  the LED inputs of the LED cells are connected to the corresponding outputs in their control signal generation units.

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