RU2246801C1 - Digital stereo television system - Google Patents

Abstract

FIELD: radio communications engineering.

SUBSTANCE: novelty is that newly introduced in prior-art system designed for telecasting in ultrahigh-frequency band over ground television networks and over satellite communication lines on sending end are three video-signal analog-to-digital computers, third code generator, pulse counter, flip-flop, and two switches, photoelectric converter is provided in addition with second lens, third piezodeflector, two dichroic mirrors, three microlenses, three photodetectors, and three preamplifiers, and third channel is inserted in transmitter; newly introduced on receiving end are third channel for receiving and processing video signal codes, optical projection system, radiator, and separate frame viewing unit, radiation modulation unit is provided in addition with second radiator of three basic colors. Effective frequency band is 316.8 Hz, number of active lines in frame is 800 with 1200 readings per line, frame repetition frequency is 50 Hz and that of resolving dots in frame is 960 000.

EFFECT: improved conditions for producing stereo effect to facilitate viewing of stereo images.

1 cl, 20 dwg, 2 tbl

Description

The invention relates to radio communications technology, can be used for television broadcasting, starting with the decimeter range in terrestrial TV networks, and via satellite communication lines.

3a, the prototype adopted a digital high-definition television system [1], which contains a photoelectric converter, three ADCs of a video signal, two ADCs of a sound signal, a sinusoidal oscillator and a frequency synthesizer, the first and second code generators, the first and second self-propelled pulse distributors, two-channel transmitter radio signals, the first channel of which includes a carrier frequency amplifier, an amplitude modulator and an output amplifier, the second channel includes an amplitude modulator and an output amplifier, and the receiving side comprising an antenna, a touch control unit, two paths for receiving and processing video signal codes, a channel for generating control signals, two sound channels, six pulse amplifier units, a radiation modulation unit, a frequency divider, a horizontal scanning unit, a first amplifier and a first piezoelectric deflector with a reflector at the end, a frame scan unit, a second amplifier and a second piezoelectric deflector with a reflector at the end, four sources of reference voltages and an opaque screen. The information of the video signal codes is transmitted via two radio channels of the upper and lower side frequencies of one carrier frequency. According to a first channel of video signals transmitted codes and E _R E _G, the second - codes _EV. At the receiving side, two radio signals are received, amplified, detected, unit symbols in the codes are converted from half-sine waves to pulses, video signal codes are distributed across the channels, and without conversion to analog video signals, a color image is displayed on a matte screen, the clock frequency in the system is 70 MHz, the active lines are 1000, samples in line 1400, interlaced frame scan, frame rate of 25 Hz, occupied band on air 252 Hz. The disadvantage of the prototype: there is no stereo image.

The aim of the invention is the formation of a stereo image system perceived by the viewer.

The technical result is the creation by the system of conditions of a stereoscopic effect for the viewer to perceive a stereo image. the transmitting side forms the right and left images of one object from two different positions, the receiving side reproduces the conditions of the stereoscopic effect for the viewer. The technical characteristics of the system are shown in Table 1. The transmitting side generates three streams of codes of the right and left images of one object, which follow one after another after 0.08 s, i.e. four frames in a row. The inertia property of vision / preservation of the visual image for 150 ms [2] / is used to reduce the frequency of rotation of the frames of the optical filters in glasses on the receiving side.

The frequency of the left and right images of each at 25 Hz, alternating in groups of four frames. The total frame rate of 50 Hz. The repetition rate of groups of four frames is 12.5 Hz. Two carrier frequencies are used. The codes E _Rп / image from the right lens / and Е _Rл / image from the left lens / are transmitted by the upper side frequency of the first carrier frequency, codes E _GP and Е _{GL are transmitted} by the upper side frequency of the second carrier. Transmission of codes E _VP and E _{VL is} made by the lower side frequency of the first carrier. Discretization of video signals of 12 MHz. Information on the color tone is carried by the side frequency of the carrier, and on the color brightness is the code of the amplitude of the video signal. The color saturation is set by the spectral band of the LEDs used in the radiation modulation unit. Sound codes are transmitted in three codes at the end of each line. Line frequency 20 kHz, the number of lines in the frame encoded on the transmitting side, 400, all active, progressive / progressive scan lines. The receiving side receives three radio signals by three paths of receiving and processing video signal codes, detects them, replaces the unit symbols in half-sine waves with pulses of the same polarity, selects horizontal and frame sync pulses / SSI and CSI /, doubles the number of samples per line from 600 to 1200, the number lines from 400 to 800, reproduces by electron-optical scanning the right and left images (four frames in a row) on the matte screen, viewed by the viewer separately: the right with the right eye and the left with the left eye. The frequency of the change of the right and left images is 12.5 Hz. The essence of the claimed system is that in a digital stereo television system containing a photoelectric converter, three ADCs of a video signal, two ADCs of a sound signal, a sinusoidal oscillator and a frequency synthesizer, the first and second code generators, the first and second self-propelled pulse distributors, the radio signal transmitter of two channels, on the receiving side, an antenna, a touch control unit, the first and second paths for receiving and processing video signal codes, each of which includes a radio reception unit a signal, a radio frequency amplifier, a bipolar amplitude detector and two pulse shapers and a channel for processing video signal codes, comprising a channel for generating control signals, two sound reproduction channels, a frequency divider, a horizontal scanning unit, a first amplifier and a first piezoelectric reflector with an end reflector, a frame scanning unit, a second amplifier and a second piezoelectric deflector with a reflector at the end, four sources of reference voltages, six blocks of pulse amplifiers, a block of modulation of radiation, including two radiation Three primary colors and an optical system, and a matte screen, three ADCs of a video signal, a third code generator, a pulse counter, a trigger and two keys are introduced on the transmitting side, a second lens, a third amplifier and a third piezoelectric reflector with a reflector at the end are introduced into the photoelectric converter, fifth and sixth voltage reference sources, third and fourth dichroic mirrors, fourth, fifth, sixth micro lenses, fourth, fifth, sixth photodetectors, fourth, fifth and sixth pre-amplifiers, to the transmitter a third channel is introduced, a third channel for receiving and processing video signal codes, a projection optical system, an emitter, and a unit for separate observation of frames are introduced on the receiving side.

The block diagram of the transmitting side in figure 1, a progressive scan of the raster in figure 2, the shape of the control voltage of the scan in figure 3, the structure of the digital streams in figure 4, the ADC of the video signal in figure 5, the design of the piezoelectric deflector in figure 6, the ADC signal 7 in FIG. 7, video signal generator E _R / E _G / in FIG. 8, video signal generator E _B in FIG. 9, receiver side diagram in FIG. 10, circuit diagram of a bipolar amplitude detector in FIG. 11, processing unit codes in FIG. 12, the radiation modulation unit in FIG. 13, the summing amplifier on f ig. 14, block selection of horizontal sync pulses in Fig. 15, block allocation of frame sync pulses in Fig. 16, block for separate observation of frames in Fig. 17, frequency spectra of transmitter signals in Fig. 18, the first block of delay elements in Fig. 19, temporary system operation diagrams in FIG.

The transmitting side includes / Fig. 1 / photoelectric converter 1, which is a sensor of video signals of two images of one object: right / E _RP , E _GP , E _VP / and left / E _RL , E _GL , E _VL /, including the first lens 2 / right /, the first piezoelectric deflector 3 with a reflector on the end located in the rear focal plane of the right lens 2, the first source 4 of positive reference voltage, the second source 5 of negative reference voltage, the first amplifier 6, the second piezoelectric deflector 7, the front end of which has two faces, is located at a corresponding angle to each other and with a reflector on each side, the second amplifier 8, the third source 9 of the positive reference voltage, the fourth source 10 of the negative reference voltage, the second lens 11 / left /, the third piezoelectric deflector 12 with a reflector at the end located in the back the focal plane of the second lens 11, the third amplifier 13, the fifth source 14 of the positive reference voltage, the sixth source 15 of the negative reference voltage, the horizontal block 16, including a master oscillator 17 and an output to skad 18, frame scanning unit 19, including the And 20 element, the driving generator 21 and the summing amplifier 22, the first 23 and the second 24 dichroic mirrors, the first 25, the second 26, the third 27 micro lenses, the first 28, the second 29, the third 30 photodetectors, the first 31, second 32, third 33 pre-amplifiers, third 34 and fourth 35 dichroic mirrors, fourth 36, fifth 37, sixth 38 micro lenses, fourth 39, fifth 40, sixth 41 photodetectors, fourth 42, fifth 43 and sixth 44 pre-amplifiers. The photoelectric converter 1 is part of the transmitting television camera, which includes the first ADC 45 / video signal E _RP /, the second ADC 46 / video signal E _GP /, the third ADC 47 / video signal E _VP /, the fourth ADC 48 / video signal E _RL /, fifth ADC 49 / video signal E _GL /, sixth ADC 50 / video signal E _VL /. The second lens 11 is located to the left of the first lens 2, its optical axis is parallel to the optical axis of the lens 2, the distance between them corresponds to the optimal stereoscopic effect. The transmitting side includes the first ADC 51 and the second ADC 52 of the sound signal, the inputs of which are accompanied by sound signals E _ZVI , E _ZV2 , a master oscillator 53 of a sinusoidal oscillation, a frequency synthesizer 54, the first 55, second 56 and third 57 code _generators respectively E _RP and E _RL , E _GP and E _GL , E _VP and E _VL , first 58 and second 59 self-propelled pulse distributors, pulse counter 60, trigger 61, first 62, second 63 keys, radio signal transmitter 64, including three channels. The first channel includes a series-connected first carrier frequency amplifier 65, an amplitude modulator 66 and an output amplifier 67, the second channel includes an amplitude modulator 71 and an output amplifier 72, the third channel includes a second carrier frequency amplifier 68, an amplitude modulator 69 and an output amplifier 70. Each of the amplitude modulators 66, 69, 71 consists of a series-connected ring modulator and a band-pass filter [3 p.234], filtering one of the side frequencies in the spectrum of the amplitude-modulated carrier.

The ADCs 45, 46, 47, 48, 49, 50 are identical (Fig. 5/); each contains a serially connected amplifier 73 and a piezoelectric deflector 74 with a reflector at the end, a positive reference voltage source 75, a negative reference voltage source 76, and a pulsed LED emitter 77, aperture diaphragm 78 and a micro lens 79, a multi-element photodetector line 80 and an encoder 81. All piezoelectric deflectors 3, 7, 12, 74, 93, 182, 190 are end bimorph piezoelectric elements with a light reflector at the free end, structurally made / Fig.6/ equally [ 4 p.118] from the first 82 and second 83 piezoelectric plates, the inner electrode 84, the first 85 and second 86 external electrodes. One end of the piezoelectric plates is fixed in the holder 87, a light reflector 88 is located on the free end face. The free end of the piezoelectric deflector 7 is made of two faces at an appropriate angle to each other, each face has its own reflector for diluting the reflected rays in different directions. The ADC 51, 52 are identical (Fig. 7/), each contains a series-connected voltage divider 89, a key block 90, a matching amplifier 91, an amplifier 92 and a piezo-deflector 93 with a reflector at the end, a source of positive reference voltage 94, source 95 of negative reference voltage, an emitter of a pulsed LED 96, a slit aperture 97 and a micro lens 98, a multi-element photodetector line 99, a first decoder 100, an encoder 101 and a second decoder 102, connected in series with a pulse counter 103, a third decoder 104 and block 105 registers.

The first 55 and second 56 code generators are executed in the same way / Fig. 8/, each contains a trigger 106 and a switching unit 107 and three channels connected in series. The first and second channels are identical. The first channel includes an AND element block 108 connected in series, the first 109, the second 110 OR elements, and an output switch 111, and a self-propelled pulse distributor 112, the second channel includes a second AND element block 113, a third 114, a fourth 115 OR element, and an output switch 116, and self-propelled pulse distributor 117, the third channel includes two blocks of 118 and 121 AND elements, fifth 119 and sixth 122 OR elements, and two self-propelled pulse distributors 120, 123, includes the first 124, second 125 keys, serially connected pulse counter 126 and decoder 127. In p In the first shaper 55, the decoder 127 has the first and second outputs connected to the corresponding key inputs 124, 125. In the second shaper 56, the decoder 127 has a third output, which is the second output of the shaper 56, connected to the input of the first self-propelled pulse distributor 58 and counter input 60 pulses. The first and second information inputs are the inputs of the switching unit 107 and the inputs of the blocks 118, 121 of AND elements, the third and fourth information inputs are the third inputs of the second and fourth elements OR 100, 115. The control inputs are: the first is the trigger path 106/12 MHz /, the second - the combined inputs of the counter 126 pulses and keys 124, 125/6 MHz /, the third - the signal inputs of the output keys 111, 116/48 MHz /, the fourth - the control input of the counter 126 pulses / 20 kHz /. The output is the combined outputs of the output keys 111, 116. In the second code generator 56, the second output is the third output of the decoder 127. The third code generator 57 contains / Fig. 9/ trigger 105, switching unit 107 and two channels. The first and second channels are identical. The first channel includes an AND element block 108, a first 109, a second 110 OR element, and an output switch 111, and a self-propelled pulse distributor 112. The second channel includes an AND element block 113, a third 114 and a fourth 115 OR element, and an output switch 116, and a self-propelled pulse distributor 117. The first information input is the inputs of the switching unit 107, the second and third information inputs are the second inputs of the second 110 and fourth 115 OR elements. The first control input is the trigger input 106/12 MHz /, the second is the combined inputs of the self-propelled valves 112, 117 pulses / 6 MHz /, the third is the signal inputs of the output keys 111, 116/48 MHz /, the output is the combined output of the output keys 111, 116 .

The receiving side (Fig. 10/) contains an antenna, a touch control unit 128, first, second and third paths for receiving and processing video signal codes, a channel for generating control signals and two sound reproduction channels. The first path for the reception and processing of codes of video signals receives and processes the codes of video signals E _RP and E _RL and includes a series-connected radio signal reception unit 129, a radio frequency amplifier 130 and a bipolar amplitude detector 131, first 132 and second 133 pulse shapers, and a video signal channel E _R , including a first 134 and a second 135 video signal registers E _R , a code processing unit 136, a first delay element block 137, an adder 138 and a second delay element block 139. The second path of the reception and processing of codes of video signals receives and processes the codes of video signals E _VP and E _VL and includes a series-connected radio signal receiving unit 140, an radio frequency amplifier 141 and a bipolar amplitude detector 142, first 143 and second 144 pulse shapers, and a video signal channel E _B , including the first 145 and second 146 registers of the video signal E _B , the processing unit 147 codes, the first block 148 delay elements, the adder 149 and the second block 150 delay elements. The third path for the reception and processing of codes of video signals receives and processes codes of video signals E _GP and E _GL and includes serially connected radio signal receiving unit 151, radio frequency amplifier 152 and bipolar amplitude detector 153, first 154, second 155 pulse shapers, and video signal channel E _G , including a first 156, a second 157 video signal registers E _G , a code processing unit 158, a first delay element block 159, an adder 160 and a second delay element block 161. The receiving side includes from the first 162 about the sixth 167 pulse amplifier units, a radiation modulation unit 168, a first frequency divider 169/2: 1 /, a horizontal scanning unit 170, a first amplifier 171 and a first piezoelectric deflector 172 with a reflector at the end, the first source 173 a positive reference voltage, a second source of negative reference voltage 174, a vertical scanning unit 175 comprising an AND 176 element, an oscillator 177 and a summing amplifier 178, a second amplifier 179, a second piezoelectric deflector 180 with a reflector at the end, a third source of positive reference voltage 181, a fourth source of negative reference voltage 182, a projection optical system 183 including a spherical mirror arranged in series, a flat mirror with an inclination of 45 ° relative to the optical axis of the spherical mirror and a correction lens, an opaque screen 184, a second frequency divider 185/2 : 1 /, emitter 186 and block 187 for separate observation of frames. The first and second sound reproduction channels are identical and each includes the first 188, second 189 keys, the first 190, the second 191 blocks of sound registers, and the digital-to-analog converter 192 / DAC / in series, a low-pass filter 193, a power amplifier 194 and a loudspeaker 195. Consistent the operating side of the receiving side provides a channel for generating control signals, comprising a block 196 for selecting horizontal sync pulses, a frequency synthesizer 197, a key 198 connected in series, a pulse counter 199, and a decoder 2 00, and a frame sync selection block 201.

Code processing blocks 136, 147, 158 are identical, each includes / Fig. 12/ trigger 202, first 203, second 204, third 205, fourth 206 registers, first 207, second 208, third 209 delay element blocks, fifth 210, sixth 211 registers, adder 212 and 16 diodes. Block 207 delays the codes by 10 ns, block 208 delays the codes by 93 ns / 83 ns + 10 ns /, block 209 delays the codes by 17.6 ns / 41.6 ns - 24 ns /. The registers 210 and 211 carry out the storage of 83 ns codes and issue them in parallel form according to the output signal U _iss . The first and second information inputs are the inputs of the delay element blocks 207, 208, the output is the combined outputs of the blocks 209, 210, 211. The control input is the input of the trigger 202 and the combined control input of the adder 212.

The radiation modulation unit 168 includes (Fig. 13/) a first emitter 213 of three primary colors, a second emitter 214 of three primary colors R, G, B and an optical system 215. Each emitter is an emitting matrix of 36 LEDs, which includes 12 red LEDs R, 12 of the green color of the radiation G, 12 of the blue color of the radiation B. The emitting plane of the emitters 213, 214 is located in the rear focal plane of the optical system 215, in the front focal plane of which is the reflector of the first piezoelectric deflector 172. Emitters cut the optical system 215, the reflectors of the piezoelectric deflectors 172, 180 and the projection optical system 183 are optically coupled to the matte screen 184. The summing amplifiers 22 and 178 are identical and each includes a / Fig. 14/9 bit counter 216 pulses, a decoder 217, the first 218, the second 219 keys, the first 220, the second 211 pulse shapers and the output amplifier 222. The first information input is the first input of the output amplifier 222, the second is the counting input of the pulse counter 216. The control input is the combined input of the control inputs of the keys 218, 219 and the control input of the pulse counter 216. The output of the summing amplifier 22 is the output of the output amplifier 222.

Block 196 selection of horizontal synchronization pulses / Fig.15/ includes the first 223, second 224, third 225 pulse counters, the first 226, the second 227 elements And, the first 228, the second 229, the third 230 elements NOT and a diode. The information inputs of the block are the counting inputs of the pulse counters. The output is the output of the second element And 227. With the arrival of three codes from the same units 11111111 at the output of the block 196, a horizontal sync pulse / SSI / appears, the SSI frequency is 20 kHz. Block 201 allocation of frame sync pulses / Fig.16/ contains the first 231, second 232, third 233 pulse counters, the first 234, second 235, third 236 elements And, the first 237, second 238, third 239 elements NOT and a diode. With the arrival of three codes 11111111 and a horizontal sync pulse to the counting inputs from block 196 to the second input of the element and 236, a frame clock / CSI / appears at the output of block 201, this is the 600th count in the last line in each even frame on the transmitting side, their frequency is 25 Hz The emitter 186 includes a pulsed infrared LED, the output window of which is the output of the emitter. With the arrival of 12.5 Hz pulses to the input of the LED from block 185, the LED emits 12.5 Hz infrared pulses of the corresponding amplitude for the divided frame observation block 187, which includes / Fig. 17/ series infrared photodetector 240, a pulse shaper 241 generating pulses of the corresponding duration and the amplitudes and the piezoelectric motor 242. The piezoelectric motor 242 according to the control pulses from the block 241 makes turns of its shaft with a resolution of 90 °. Two cylindrical frames 243 are fixed on the shaft, in which two neutral filters 244, each with a density of 4 ^x , made of nets, are located opposite each other / through 180 ° /. Each filter 244 occupies one fourth of the cylindrical surface of the frame 243. The filters are located in the frame through 180 °. A photodetector 240, a pulse shaper 241, a piezoelectric motor 242 with a shaft and cylindrical frames 243 are mounted on it on the outside of the case 245 points, the case 245 has right and left eye windows with transparent glasses / for eye safety /. Right and left cylindrical frames 243 with two neutral filters 244 are located against the eye windows of the case of glasses. To watch a stereo broadcast, glasses are put on the eyes. For one revolution of the motor shaft 242, each eye window is blocked by light filters twice / through 180 ° /. The multiplicity of one filter is 4 ^x , when the eye window is blocked, their magnification is added up to 8 ^x . For separate observation of the frames by the right and left eye, the position of the filters 244 in the frames 243 is offset 90 ° from each other, so each eye observes its image: the right eye - the right eye, the left eye - the left eye, which alternate after 0.08 s / te . 4 frames in a row is the right image, then 4 frames left /. The alternation interval is selected from the condition of reducing the rotation speed of the motor shaft 242 and not exceeding the properties of inertia of vision to preserve the visual image / 150 ms / [2 p.197]. With a frequency of overlapping eye windows of 12.5 Hz / 0.08 s /, the shaft rotation speed is 3.125 r / s, i.e. 187.5 rpm The overlap frequency of the ocular windows can be doubled, for which a frequency of 50 Hz is applied to the input of the trigger 61 at the input side, and a control signal is sent to the emitter unit 186 at the receiving side, bypassing the frequency divider unit 185. In this case, the rotation speed of the motor shaft 242 will be 6.5 r / s.

Like lenses 2 and 11 on the transmitting side, the viewer's eyes observe on the screen 184 an image of the same object from different positions, obtaining a stereoscopic effect [5 p.389]. The number of blocks 187 on the receiving side should correspond to the number of spectators. The piezoelectric motor [6 p.40] rotates the shaft in increments of 90 °, the excitation voltage is 5 V, the current consumption is 0.1 A, the starting time is 0.001 s / 1 ms /, the mass of the engine is 10 g, and the noise level is more than 20 dB. For each control pulse, the engine 242 rotates the filters 244 through 90 °, while one eye window is opened alternately, the other is blocked by two filters 244. Frames of the right image / 4 pcs / are reproduced synchronously with the opening of the right window on the screen 184, when the left window is opened, on the screen there are frames of the left image / 4 pcs. /. Without glasses, the usual two-dimensional image will be observed.

The first blocks 137, 148, 159 delay elements are identical, each includes / Fig. 19/ element 246, the first 247 and second 248 keys, the first 249, the second 250 pulse distributors, eight registers 251 _1-8 , each of which contains 1200 bits for placement of signals in them on one bit from the 8-bit code of 1200 line samples. Blocks 137, 148, 159 delay the codes of each line for a line duration of 50 μs. The clock frequency in the system is:

where: 400 - the number of lines in the frame on the transmitting side,

50 Hz - frame rate, 400 × 50 Hz = 20 kHz line frequency,

- число пар отсчетов в строке при двухполярной передаче кодов /фиг.4/,

- the number of pairs of samples in a row during bipolar transmission of codes / 4 /,

8 _bits - the number of bits in the code.

Photoelectric converter 1 generates six analog video signals of two images that come from pre-amplifiers 31, 32, 33 in ADC 45, 46, 47 and from pre-amplifiers 42, 43, 44 in ADC 48, 49, 50. Photoelectric converter 1 and six ADCs structurally placed in a transmitting chamber, the output of which is six binary codes of video signals: the right image E _RP , E _GP , E _VP and the left image E _RL , E _GL , E _VL . ADCs convert analog video signals to 8-bit codes. Alternate output of video signals from the ADC 45, 46, 47 and the ADC 48, 49, 50 is performed by the trigger 61 and keys 62, 63. The 25 Hz pulses from the sixth output of the synthesizer 54 frequencies are fed to the input of the trigger 61, the signal from the first output of which opens the first a key 62, which transmits 12 MHz pulses for 0.08 s to the ADC clock inputs 45, 46, 47, the codes of which are transmitted to the drivers 55, 56, 57 for 4 frames. The ADC 48, 49, 50 during these 4 frames do not give out codes; 12 MHz clock pulses do not arrive at their clock inputs.

With the arrival of the second 25 Hz pulse to trigger 61, the key 62 closes, the second key 63 opens, transmitting 12 MHz pulses to the clock inputs of the ADCs 48, 49, 50, codes from which for 0.08 s / duration of the next 4 frames / arrive shapers 55, 56, 57. At this time, the ADCs 45, 46, 47 do not issue codes, 12 MHz pulses do not arrive at their clock inputs. Shapers 55, 56, 57 codes convert parallel codes of video signals and sound into serial ones and replace the representation of units from pulses with positive and negative half-sinusoids of a 48 MHz monofrequency from a 54 frequency synthesizer. The master oscillator 53 generates sinusoidal oscillations with a stability of 10 ^-7 . A frequency synthesizer 54 generates and issues: from the first output, 12 MHz pulses to the ADC 45-50 clock inputs via keys 62 and 63 and to the first control inputs of the shapers 55, 56, 57 codes, from the second output 6 MHz pulses to the second control inputs of the shapers 55 , 56, 57 codes and the first control inputs of the ADC 51, 52, from the third output pulses of 60 kHz to the second control inputs of the ADC 51, 52, from the fourth output sinusoidal oscillations of 48 MHz to the third control inputs of the drivers 55, 56, 57 codes, s fifth output pulses of 20 kHz to the fourth control inputs form ers 55, 56 codes the first input unit 19, vertical scan and the third control inputs of the ADC 51, 52, with six pulses of 25 Hz to the second input unit 19, the input of flip-flop 61 and to the control input 60 pulses / U counter ₀ / from the seventh, 10 kHz pulses to the input of the horizontal scanning unit 16; from the eighth, sinusoidal oscillations of 480 MHz of the first carrier frequency for amplifier 65; from the ninth, sinusoidal oscillations of 576 MHz of the second carrier frequency for amplifier 68. The ADCs 51, 52 convert three sound signals into 16 bit codes that enter the second information inputs s formers 55, 56 codes. Self-powered dispenser 58 pulses with the arrival of signal U _n starting from the second output driver 56 codes / at the time of the 300-th sampling pulse string / outputs a code of eight units 11111111, which is the source of horizontal sync / FID / 599th count in each row, on the third information inputs of the shapers 55, 56 codes and the second information input of the shaper 57 codes. Self-powered dispenser 59 pulses with the arrival of signal U _n starting from the second output of the counter 60 pulse outputs code of eight units 11111111, which is the code frame pulse / CSI / 600th count of the last row of each even frame, to the fourth information inputs of the formers 55, 56 codes and to the third information input of the third shaper 57 codes. A two-bit pulse counter 60 generates a start signal U _p for the self-propelled pulse distributor 59 from the output of the second discharge, with a second pulse arriving at its counting input from the second output of the code generator 56, and then it is reset by a 25 Hz pulse from the 54 frequency synthesizer.

The spectrum of the amplitude-modulated signal / Fig. 18/ consists of a carrier and two side frequencies. One of the side frequencies and the carrier frequency itself in the information sense are redundant. Therefore, in each amplitude modulator 66, 69, 71 the carrier frequency is suppressed [3 p.234] and one of the side frequencies is filtered out. Amplitude modulator 66 outputs to the output amplifier 67 an upper side frequency of 528 MHz from the first carrier.

The amplitude modulator 71 outputs to the input of the output amplifier 72 a lower side frequency of 432 MHz from the first carrier. The amplitude modulator 69 outputs to the input of the output amplifier 70 an upper side frequency of 624 MHz from the second carrier frequency.

The receiving side receives three radio signals, amplifies them, detects sine waves based on the polarity, divides the codes into channels, selects horizontal and frame sync pulses, generates two carrier frequencies, separates the audio codes from the video codes, doubles the number of samples in each line from 600 to 1200 , doubles the number of lines from 400 to 800, performs luminance modulation of the radiation according to the code of each video signal and reproduces the right and left color images on a matte screen with stereo sound by.

Lens 2 / Fig. 1/ creates a right color image in the focal plane in which the reflector of the first piezoelectric deflector 3 is located. The reflector has a width of at least 0.02 mm and a length of at least 8 mm: 0.02 mm × 400 lines. The dimensions of the deploying element are 0.02 · 0.02 mm. According to the control voltages (Fig. 3/) from the amplifier 6, the piezoelectric deflector 3 vibrates the end face with the reflector relative to the first reflector at the end of the second piezoelectric deflector 7, scanning a row of the right image. The lens 11 creates a left color image in the focal plane in which the reflector of the third piezoelectric deflector 12 is located. Its reflector has dimensions identical to the dimensions of the reflector of the piezoelectric deflector 3. According to the control voltages from the amplifier 13, the piezoelectric deflector 12 vibrates the end face with the reflector relative to the second reflector of the piezoelectric deflector 7, scanning lines of the left image.

Block 16 line scan outputs a linearly varying voltage / Fig.2/ in the form of an isosceles triangle. The voltage first increases in proportion to time, the reflectors of piezoelectric deflectors 3 and 12 at a uniform speed synchronously and in-phase rotate from left to right, when the edge of the raster is reached, the scan voltage decreases in proportion to time, the reflectors return at the same speed. The control voltage period is equal to the duration of two lines, therefore, to build a raster of 400 lines at 50 frames per second, the piezo-deflectors 3 and 12 oscillate with a frequency of 10 kHz, two lines unfold in one oscillation period. Line frequency 20 kHz, line scan in the frame is line-by-line, without reverse moves. The frequency of 10 kHz in block 16 comes from the 7th output of the synthesizer 54 frequencies. Block 16 from the master oscillator 17 and the output stage 18. The signal from the amplifier 6/13 / is fed to the internal electrode 84 of the piezoelectric deflector / Fig.6/, the voltage from the source 4 of the positive reference voltage is applied to the external electrode 85, and the voltage c is applied to the external electrode 86 source 5/15 / negative reference voltage. When a control voltage is applied to the inner electrode 84, the piezoelectric plates 82, 83 are deformed [4 p.122], a bending moment of forces occurs, the end face with the light reflector 88 rotates and rejects the vertical image line. Images of two vertical lines are fed to the first and second reflectors of the second piezoelectric deflector 7, which performs a vertical scan /. When scanning a frame, odd frames go down, when scanning up, even frames go. The width of the reflectors of the piezoelectric deflector 7 is not less than 0.02 mm, the length of each is not less than 12 mm: 0.02 mm × 600 count. The piezoelectric deflector 7 oscillates at a frequency of 25 Hz, which is 50 frames per second. Line and frame scan without reverse moves / Fig.2/. From the output of the summing amplifier 22, a linearly varying and stepwise voltage is output, amplified to the required value by the amplifier 8. When scanning lines from top to bottom, odd frames are expanded, when scanning lines from bottom to top, even frames go. The summing amplifier 22/178 / performs / Fig. 14 / the summation of the line voltage from the master oscillator 21 with pulses of 20 kHz from block 54/196 /. Each line impulse moves the line at the end of its course by one line step at the moment the ray enters the edge of the screen / on both sides /, 400 lines of the frame are obtained and all are active. The purpose of the blocks (Fig. 14/ from 216 to 221 is to apply to the second input of the output amplifier 222 at the right time positive / for odd frames / and negative / for even frames / pulses of the desired amplitude and duration. Before the start of a vertical sweep, the signal U ₀ from the And 20 element resets the bits of the counter 216. The 9-bit counter 216 produces a line pulse count of 20 kHz, and a cycle of counting 400 pulses. The signal U ₀ simultaneously with the zeroing of the counter 216 opens the first key 218, which passes urgent pulses to the input of the first 220 pulse shaper, which produces positive pulses of the corresponding amplitude and duration, and feeds them to the second input of the output amplifier 222. An odd-frame scan follows. With the arrival of the 400th pulse counter, the counter 216 generates a code from the number 400/110010000 /, which is decrypted, from the output of the decoder 217, the pulse closes the first key 218 and opens the second key 219, which transmits horizontal pulses to the second pulse shaper 221, issuing negative pulses to the second input of the output amplifier 222, followed by an even-frame scan. With the arrival of the next signal U _{0, the} process repeats.

Mixed colored rays reflected from the first reflector of the piezoelectric deflector 7 are directed: red is reflected from the first dichroic mirror 23, collected by the lens 25 into a photodetector 28, blue is transmitted by the first dichroic mirror 23, reflected from the second 24 and reflected by the lens 26 in the photodetector 29, the green color passes through both mirrors 23 and 24 and the lens are collected in the photodetector 30. photodetectors analog video signals _rp E, E _GP, E _VI enter the preamplifiers 31, 32, 33. a similar process is tested rays from a orogo pezodeflektora reflector 7, analog video signals E _RL, E _dl, E _is fed to preamplifiers 42, 43, 44. preamplifiers analog video signals: the right image to the inputs of the ADC 45, 46, 47, the left image of the same object at the inputs ADCs 48, 49, 50. ADCs 45-50 have one conversion principle, which consists in scanning the beam (Fig. 5/) from the LED 77 by the piezoelectric reflector 74 along the plane of the entrance pupils of the photodetector line 80 of the multi-element photodetector, the light pulse is converted into electrical a signal exciting one of the input buses of the encoder 81, which provides a code for the instantaneous value of the input video signal. The conversion is performed with a sampling rate of 12 MHz, the sampling pulses are fed to the input of the LED 77 from block 54. The slit aperture 78 and the micro lens 79 form a beam with an aperture equal to the size of one input window of the photodetector line 80. A pulsed LED AL402A with a pulse rise time of 25 ns was adopted as a radiation source with a margin satisfying sampling of 12 MHz / 83 ms /. The photodetectors in the line are the avalanche photodiodes of the APD with a response time of 10 ns. Line 80 contains 255 photodetectors for encoding video signals with an 8-bit code. The output of each photodetector is connected to the corresponding input of the encoder 81. The encoder is represented by K155IV1 microcircuits with a response time of 20 ns [11 p.231]. The encoder generates codes from 00000001 to 11111111. The first photodetector in line 80 corresponds to the code 00000001, the second to 00000010, the third to code 00000011, etc., the 255th to code 11111111. The conversion time is 30 ns / 10 ns + 20 ns / or 33 · 10 ⁶ prev / s, with a margin satisfying the frequency of 12 MHz / 83 ns /.

ADC 45-47 and ADC 48-50 give out, alternating, four frames in a row. First, the clock pulses from the output of the first key 62 arrive for 4 frames on the ADC 45-47, the right image codes are issued, then the key 62 is closed, the clock pulses from the second key 63 are issued on the clock inputs of the ADC 48-50, codes 4- x frames of the left image. Information creation speed by each ADC 96 Mbit / s: 12 MHz × 8 _bits .

The ADCs 51, 52 convert two audio signals into 16-bit codes. During one line, the ADC generates three codes, a sampling rate of 60 kHz. To obtain codes with 16 bits, the transfer coefficient of the voltage divider 89 is changed.

The divider 89/7 / presents a seven-step resistive divider. The key unit 90 has seven keys for connecting the corresponding stage of the divider 89 to the matching amplifier 91, which is an emitter follower. The line of multi-element photodetector 99 contains 1024 photodetectors and converts the sound signal into a 10-bit code, 2 ¹⁰ . Resolution adopted 10 μV. The encoding range of line 99 only is 0-0.01024 V. The conversion of signals exceeding 2 ¹⁰ into the code is performed by the first decoder 100, the encoder 101, the second decoder 102, the voltage divider 89 and the key block 90. Using them, the encoding range of the sound signals is 0-0.65536 V, i.e. 2 ¹⁶ . The pulse from each photodetector enters the decoder 100, from it to the encoder 101. If there is no signal at the input of the divider 89, the code from the zeros comes to the input of the second decoder 102, the signal from the first output of the decoder 102 opens the first key in block 90, thereby determining the transmission coefficient 1.0 divider 89. When the signal reaches the value of code 2 ²⁰ , a signal appears on the second output of the second decoder 102, which opens the second key in block 90 and closes the first key, the coefficient becomes 0.5, with code 2 ¹¹ - the coefficient 0.25, with code 2 ¹² - 0.125, with code 2 ¹³ 0.0625, with code 2 ¹⁴ -0.03125, with code 2 ¹⁵ - 0.015625, which remains until code 2 ¹⁶ . With decreasing signal amplitude, the process is the opposite of increasing transmission coefficient. Units in codes are represented by the presence of an impulse, zeros by their absence. During one line, the encoder 101 issues three codes, one after the other, to block 105, which contains three 16-bit registers. In the process of receipt, the codes are shifted from register to register by pulses U _sd shift. In block 105, three codes are accumulated, which are consecutively sent to the first 55 and second 56 code generators at the moments 297, 298, 299 of the line sampling pulses / Fig. 4/. The output signals come from the third decoder 104 at the moments 297, 298, 299 of the line sampling pulses / 6 MHz /. The output signals form a pulse counter 103 and a third decoder 104. The 9-bit counter 103 produces a 6 MHz count, the count cycle is 300 pulses. The counter 103 is reset to the leading edge of the pulse U _{0 of} the line frequency of 20 kHz at the time of the 300th line sampling pulse. The first shaper 55 codes gives from 1 to 592 codes of video signals E _RP and E _RL , three sound codes, SSI code / 500th line count / and in the last 400th line of each even frame, the CSI code / 600th line count /, figure 4. Units in codes of odd samples of a line are represented by positive half-sine waves of mono frequency 48 MHz with stability of 10 ^-7 , units in codes of even samples of a line are represented by negative half-sine waves of mono frequency of 48 MHz. The second _generator 56 codes gives from 1 to 592 codes of video signals E _GP , E _GL , three sound codes, CCi code and CSI code. The third generator 57 codes gives from 1 to 592 codes of video signals E _VP , E _VL , SSI code and CSI code.

The operation of the shapers 55, 56 codes / Fig. 8/.

Codes with ADCs 45, 48/46, 49 / are received in parallel with a frequency of 12 MHz at the inputs of a switching unit 107 that branches a stream of 12 MHz codes into two at 6 MHz: the first stream is the codes of odd samples, the second is the codes of even samples of a line. Block 107 includes four K176KT1 microcircuits, which are 4-channel switches with a response time of 25 ns [14 p.222].

The outputs of the first two microcircuits are connected to the first inputs of the AND elements of block 108, the outputs of the other two microcircuits are connected to the first inputs of the AND elements of block 113. A trigger 106 is connected to the outputs of the block 107 by a trigger 106, which receives 12 MHz pulses. Eight pulses from the first 112 and second 117 self-propelled pulse distributors having eight bits each receive sequentially the second inputs of the AND elements of blocks 108, 113, and the starting pulses U _p for them are 6 MHz pulses arriving at the second control input. From the outputs of the AND elements of blocks 108, 113, the code pulses sequentially open the OR elements 109, 110 and 115 for the duration of their duration / clock period / 20.8 ns / 10 ⁹ ns: 48 MHz / output keys 111, 116. To signal inputs output keys are sine waves 48 MHz. The first output switch 111 in the open state passes one positive half-sine wave, the second output key 116 in the open state passes one negative half-sine. At the output of the code generator, the units in the codes of the odd samples are represented by positive half-sine waves, in the codes of even samples, the terms are represented by negative half-sines. Zeros appear to be the absence of both. The output signal at the output of the shapers 56, 55 codes are either full sine waves of 48 MHz or incomplete sine waves of the same frequency. These signals modulate the carrier frequencies: from the shaper 55, the first carrier frequency in block 66, from the shaper 56, the second carrier frequency in block 69 of the transmitter 64. Timing diagrams of this process in Fig. 20. Each sound code consists of two parcels of 8 bits. The first package / half of the sound code / 1-8 bits goes to the first inputs of AND elements of block 118 and through the OR elements 119, 110 it goes to the input of the first output key 111, the second package / second half of the sound code / 9-16 bits goes to the first inputs elements AND block 121 and through the elements OR 122, 115 is fed to the input of the second output key 116. The keys 124, 125 are designed to separate the codes of the video signals from the sound codes. The key 124 is opened by the signal from the first output of the decoder 127 at the time of the 300th pulse of the line sampling and remains open from the 1st to 296 pulse of the line undecretization / from 1 to 592 line samples, Fig. 4 /. At the moment 296 of the sampling pulse, the pulse from the second output of the decoder 127 closes the key 124, opens the key 125. At the moments 297, 298, 299 of the discrete pulses of the line, three sound codes arrive at the inputs of the output keys 111, 116. At the time of the 300th pulse / 599 count line / to the third input of the element OR 110 receives the SSI code / 11111111 / from the self-propelled pulse distributor 58, which is triggered by the signal U _p from the third output of the decoder 127, issued at the moment 299 of the line sampling pulse. With the last 400th line in an even frame, the second self-propelled distributor of 59 pulses gives out at the moment of the 300th sampling pulse the code KSI / 11111111 / for 600 counts of the line to the third input of the element or 115. The signal U _p for starting the self-propelled distributor of 59 pulses gives 2- x bit counter 60 pulses with a counting cycle two pulses coming from the second output of the shaper 56 codes. The counter 60 is reset to zero by a signal U ₀ 25 Hz from the sixth output of the frequency synthesizer 54, then the counter 60 receives two pulses from the second output of the code generator 56, the second pulse corresponds to the end of an even frame / 299th sampling pulse of the last line of an even frame /. With the arrival of the second pulse in the counter 60 from the output of its second discharge, a start signal U _P follows to start the self-propelled distributor of 59 pulses. The CSI code is the 600th count of the last line only in every even frame. Self-propelled pulse distributors are made according to [7 p.274]. The process of the third generator 57 codes is similar to the operation of the generator 55 codes and simpler, it does not generate sound codes.

The first channel of the radio signal transmitter 64 emits an upper side frequency of 528 MHz from the first carrier of 480 MHz with information of codes E _RП and Е _RЛ , with the stability of the carrier 10 ^{-7 the} occupied band on the air is ± 52.8 Hz or 105.6 Hz. The second channel emits an upper side frequency of 624 MHz from the second carrier 576 MHz with information codes E _GP and E _GL , which occupies the band of ± 62.4 Hz or 124.8 Hz. The third channel emits a lower side frequency of 432 MHz from the first carrier with information of the video signal codes E _VP and E _VL , which occupies the band of ± 43.2 Hz or 86.4 Hz. In total, the occupied band on the air is 316.8 Hz.

Three radio signals are received by the blocks / Fig. 10/129, 140, 151 of the radio signal reception, which are selectors of the decimeter band channels / ACS / with electronic tuning, and receive radio signals in the range 430-790 MHz. Each unit includes an input circuit, a radio frequency amplifier, and a mixer / transistor VT2 / is used from the frequency converter [8 c.132 fig. 4.2]. The band-pass filter of the radio frequency amplifier in each range is tuned by applying the mixing voltage to the varicaps from the electronic switch of the touch control unit 128, which is a program selection unit, for example, USU-1-15 [8 p. 86]. The amplified radio frequency signal through the communication loop [8 p.132] goes to the emitter of the mixer / VT2 /, the frequency equal to the carrier on the transmitting side, necessary for detecting a single-band signal [9 p.146], is also supplied from the frequency synthesizer 197. The local oscillator circuit and the IF filter, available in SKD-24 [8 Fig. 4.2], are not needed. The signal from the VT2 collector, which is the output signal of block 129/140, 151 /, is fed to the input of the amplifier 130/141, 152 / of the radio frequency, where it is amplified to the required value and fed to the input of the bipolar amplitude detector 131/142, 153 /. The second inputs of the synthesizer 197 frequencies are connected to the second group of outputs of the block 128 / after the diodes D11-D18 [8 p. 86] /. When the transmission channel is turned on, the voltage from the corresponding diode determines the output of two frequencies to the third inputs of blocks 129, 151 / first carrier frequency, output 5 of block 197 / and block 140 / second carrier frequency, output 6 of block 197 /. Bipolar amplitude detectors 131, 142, 153 are made according to the scheme in Fig.11. Diode D1 emits a positive envelope of the modulating signal. Diode D2 from the modulating one selects envelopes of positive half-sine waves / unit symbols in codes of odd samples /, diode D3 from a modulating one selects envelopes of negative half-sinusoids / unit symbols in codes of even samples /. From the first output of the bipolar amplitude detector, the detected positive half-sine waves with a frequency of 48 MHz are fed to the input of the first shaper 132/143, 154 / pulses, from the second output, the detected negative half-sine waves are fed to the input of the second shaper 133/144, 155 / pulses. The pulse shapers are made according to the scheme of an asymmetric trigger with emitter coupling [10 p.209], which forms rectangular pulses from harmonically changing signals. The pulses from the formers have one polarity and a duration equal to the pulse duration in the codes on the transmitting side. Units in codes are represented by the presence of an impulse, zeros by their absence. After turning on the power in the receiving side, the keys are in a closed state. The operating procedure of the receiving side is determined by control signals from the channel for generating control signals. The decisive role belongs to block 196 allocation of horizontal sync pulses / SSI /. A condition for the appearance of the SSI from block 196 is the simultaneous arrival of eight codes of eight units into it from three formers 132, 143, 154. In all codes, except for 599 counts / Fig. 4/, one or more zeros will be present, especially in three codes at the same time. For each zero in the code, the NOT elements (Fig. 15/) will reset the counters in block 196. With the arrival of three codes 11111111, block 196 generates an output pulse, which is an SSI whose frequency is 20 kHz / line frequency /. The SSI opens the key 198, enters the frequency divider 169, to the input of the frame scanning unit 175, to the input of the CSI allocation block 201 and to the first input of the frequency synthesizer 197. According to the clock pulse, the frequency synchronization is performed in the synthesizer of 197 frequencies. Own synthesizer frequency stability 197 frequencies 10 ^-6 . Adjustment for the frequency and phase of the master oscillator of the transmitting side is made on the leading edge of the SSI from block 196.

A frequency synthesizer 197 produces 6 MHz line sampling pulses from the first output, 48 MHz clock pulses from the second output, 60 kHz pulses from the third output of sound codes from register blocks 190, 191, and from the fourth - 12 MHz pulses to the control inputs of blocks 136, 147 , 158 code processing, from the fifth and sixth sinusoidal oscillations of two carrier frequencies, respectively, of the received program to the third inputs of blocks 129, 140, 151, from the seventh output pulses of 24 MHz, from the eighth output pulses of 50 Hz for blocks of 137, 148, 159 delay elements. The odd code code of the video signal E _R from the output of the pulse shaper 132 enters in a sequential form into the first register 134 of the video signal E _R , filling the bits of which the code becomes parallel. The code of the even count of the video signal E _R from the output of the shaper 133 enters the second register 135 of the video signal E _R , fills its bits and becomes parallel. A similar process is tested codes E _G, filling the first 156 and second 157 registers the video signal E _G, E _B and codes, filling the first 145 and second 146 registers the video signal _EV. The issuance of codes from the registers to the corresponding code processing units 136, 147, 159 is performed by 6 MHz pulses from the first output of the frequency synthesizer 197, and they also reset the registers before receiving the next code. The processing units 136, 147, 158 of the codes are identical, they double the number of samples in each line by obtaining intermediate / average / sample values between each passing code and the one following it. Blocks perform the addition of the previous and subsequent codes and divide the sum code in half by 2.

The operation of the block 136/147, 158 / code processing, Fig.12.

The codes of the odd samples of the line from register 134 through the block 207 delay elements / 10 ns / arrive in parallel to the registers 203, 204. The codes of the even samples of the line from the second register 135 through the block 208 elements of the delay / 93 ns / arrive in parallel to the registers 205, 206. Each the code is used twice: the first time as the previous, the second time as the next, so block 136 has four registers 203, 204, 205, 206. With the arrival of the first 12 MHz pulse to the input of the trigger 202 from its first output, the signal U _vyd1 gives 0 code from the register 204 and 0 code / codes from one zeros / from register 205 and reset yelling them. 0 code from register 204 goes to the first inputs of adder 212, 0 code from register 205 goes to the inputs of sixth register 211 / storing it 83 ns / and through diodes to the second inputs of adder 212. 10 ns after issuing the code from register 204 to registers 203 , 204 comes from block 207 the next 1 code. Block 207 delays the code by 10 ns to prevent the incoming code from being overlaid with 1 code issued from register 204. Adder 212 performs the addition of codes 0 code + 0 code. As an adder, K555IM6 microcircuits were used [11 p. 258] with an addition time of 24 ns. At the end of the addition, the signal U _0/12 MHz / issues the sum code to the block 209 delay elements / 17.5 ns / and resets the adder circuits 212. Division of the sum code by two is performed by shifting the sum code by one bit so that the least significant bit of the sum code is discarded / as when dividing the decimal number by ten /. A shift by one bit is performed when issuing the code from the adder 212 to block 209 by a corresponding connection of the outputs of the adder and the inputs of block 209:

adder outputs 212 0 1 2 3 4 5 6 7 8 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ inputs of block 209 1 2 3 4 5 6 7 8

. На входы блоков 207 и 208 элементов задержек коды поступают одновременно. Блок 207 производит задержку кода на 10 нс для согласования по времени выдачи кода из регистров 203, 204 и поступления в них следующего кода. Блок 208 производит задержку кода на 93 нс: 83 нс для восстановления следования кода четного отсчета за кодом нечетного отсчета /второго кода за первым/ и 10 нс для согласования по времени выдачу кода из регистра 206 и поступления следующего кода. С приходом второго импульса 12 МГц в триггер 202 импульс во второго его выхода U_выд2 выдает код №2 0 код из регистра 211 на выход блока 136. Код №2 следует за кодом №1 через 41,5 нс, половина времени хранения кода в регистре 211 /210/ из 83 нс приходится на процесс сложения в сумматоре 212 /24 нс/ плюс задержка в блоке 209 17,5 нс. Далее импульс U_выд2 выдает 1 код из регистра 203 напрямую в пятый регистр 210 и через диоды в сумматор 212 и 0 код из регистра 206 в сумматор 212. Вслед за выдачей кода 0 код из регистра 206, регистры 205 и 206 заполняются кодом 2 код с блока 208. В это же время сумматор производит сложение 0 код + 1 код, а при выдаче кода суммы в блок 209 следует деление кода суммы на два, и на выходе блока 209 появляется код №3

. С приходом третьего импульса 12 МГц в триггер 202 с его первого выхода следует сигнал U_выд3, который выдает одновременно с пятого регистра 210 код №4 1 код, следующий за кодом №3 через 41,5 нс, с регистра 205 2 код в регистр 211 и через диоды в сумматор 212 и 1 код из регистра 204 в сумматор. Вслед идет заполнение регистров 203, 204 следующим кодом 3 код. Сумматор выполняет сложение 1 код + 2 код, затем деление на два, и код №5

следует на выход. С приходом четвертого импульса 12 МГц на вход триггера 202 сигнал U_выд4 одновременно выдает код №6 2 код с регистра 211, 2 код из регистра 206 в сумматор, из регистра 203 код 3 код в регистр 210 и через диоды в сумматор 212. Следует заполнение регистров 205, 206 следующим кодом 4 код. Идет сложение в сумматоре 212 2 код + 3 код, деление пополам, и код №7

идет на выход. С приходом пятого импульса на вход триггера 202 сигнал U_выд5 выдает с регистра 210 код №8 3 код, из регистра 204 код 3 код в сумматор, из регистра 205 код 4 код в регистр 211 и через диоды в сумматор 212. Следует сложение в сумматоре 3 код + 4 код, деление на два, и код №9

идет на выход блока 136. С приходом шестого и следующих импульсов 12 МГц в триггер процессы повторяются. Выходы регистров 210, 211 и блока 209 элементов задержек поразрядно объединены, с их выходов коды частотой 24 МГц поступают в блок 137 /148, 159/.Bit 0 means transfer to it with the sum of codes in the adder. The process of obtaining an intermediate code value is illustrated in FIG. When doubling the number of samples in a row from 600 to 1200, their repetition rate will be 24 MHz, the repetition period will be 41.5 ns. The addition process takes 24 ns, therefore, block 209 should delay the code by 17.5 ns / 41.5 ns - 24 ns /. Therefore, after the codes arrive in the adder 212, the code follows 41.5 ns to exit the block 209. Code No. 1 represents

. At the inputs of blocks 207 and 208 of the delay elements, the codes arrive simultaneously. Block 207 delays the code by 10 ns to agree on the time of issuing the code from the registers 203, 204 and the next code arriving at them. Block 208 delays the code by 93 ns: 83 ns to restore the even code for the odd code for the odd code / second code for the first / and 10 ns to coordinate the timing of the code from register 206 and the next code. With the arrival of the second 12 MHz pulse in trigger 202, the pulse in its second output U _vy2 gives a code No. 2 0 code from register 211 to the output of block 136. Code No. 2 follows code No. 1 after 41.5 ns, half the code storage time in the register 211/210 / out of 83 ns is accounted for by the addition process in the adder 212/24 ns / plus a delay in block 209 of 17.5 ns. Next, the pulse U _vyd2 issues 1 code from register 203 directly to fifth register 210 and through diodes to adder 212 and 0, code from register 206 to adder 212. Following the issuance of code 0, code from register 206, registers 205 and 206 are filled with code 2 code with block 208. At the same time, the adder adds 0 code + 1 code, and when issuing the sum code to block 209, the sum code is divided by two, and code No. 3 appears at the output of block 209

. With the arrival of the third 12 MHz pulse in the trigger 202, from its first output follows the signal U _out3 , which gives simultaneously from the fifth register 210 code No. 4 1 code following code No. 3 after 41.5 ns, from register 205 2 code to register 211 and through the diodes to the adder 212 and 1 code from the register 204 to the adder. Following is the filling of registers 203, 204 with the following code 3 code. The adder performs the addition of 1 code + 2 code, then division by two, and code No. 5

should exit. With the arrival of the fourth pulse of 12 MHz to the input of trigger 202, the signal U _vy4 simultaneously generates code No. 6 2 code from register 211, 2 code from register 206 to the adder, from register 203 code 3 code to register 210 and through diodes to adder 212. Fill registers 205, 206 following code 4 code. There is an addition in the adder 212 2 code + 3 code, division in half, and code No. 7

goes to the exit. With the arrival of the fifth pulse to the input of trigger 202, the signal U _vyd5 issues code 210 from register 210, code 8, code 3 from register 204, code 3 from code to adder, code 205 from register 205, code 4 into register 211 and diodes into adder 212. Addition in the adder follows. 3 code + 4 code, division by two, and code No. 9

goes to the output of block 136. With the arrival of the sixth and subsequent 12 MHz pulses, the processes repeat in the trigger. The outputs of the registers 210, 211 and the block 209 of the delay elements are bitwise combined; from their outputs, the codes with a frequency of 24 MHz arrive at block 137/148, 159 /.

The operation of the block 137/148, 159 / delay elements, Fig.19. To double the lines in the frame, a necessary condition is the delay of the codes of the current line relative to the codes of the next line by its duration / 50 μs /. This question would be solved simply with the direction of the sweep of all lines of the frame in one direction. In the inventive system, the directions for scanning lines are opposite: odd in one direction, even towards them. To obtain the codes of samples of the intermediate line in this case, it is necessary to add the 1st sample of the line with the last sample of the previous line. The first blocks 137, 148, 159 delay elements perform the delay of the codes of the current line in the opposite scan of lines in the frame. With the arrival of a pulse of 50 Hz / s of block 197 / and a horizontal SSI from block 201 to element And 246, from its output, the signal opens the key 247, which transmits 24 MHz clock pulses to the 249 pulse distributor. Clock pulses from the 249 distributor are sequentially fed to the clock / first / inputs from the 1st to the 1200th bits of eight registers 251 ₁ -251 ₈ . At 1-8, the information inputs of block 137 receive the signals of the 1st row codes from block 136: the signals of the first category of codes are fed to the second inputs of the bits of the first register 251 ₁ , the signals of the second bit of codes are fed to the second inputs of the bits of the second register 251 ₂ , etc. ., the signals of the eighth bit of the codes are fed to the second inputs of the bits of the eighth register 251 ₈ . At the end of the first line, 1200 bits of eight registers are filled with signals of 1200 codes of the 1st line. In the next 50 μs, 1200 codes from eight registers 251 _1-8 should be output to the adder 138/149, 160 / while filling the bits of the registers with the signals of the codes of the next line. Code signals are generated by the front

the front of the clock pulse, the entry of signals of the incoming code is made by the same clock pulse. Due to the fact that the second line is scanned towards the first line, codes from registers 251 _{1-8 are} issued in the reverse order: not from the 1st category of the register, but from the 1200th category. Filling the registers with codes of the second line begins with the 1200th digit. This is done by a second pulse distributor 250, the outputs of which are connected to the clock inputs of the bits of the registers 251 _1-8 in the reverse order: the first output is connected to the 1200th bits of the registers, and the 1200th output is connected to the first bits of the registers 251. the lines the issuance of codes from the registers is performed again by pulses from the distributor 249 pulses, starting from the first category of registers. Further, these processes are repeated. As a result, the code of the current line from block 136 comes to the first inputs of the adder 138/149, 160 /, and the delayed code of the desired count of the previous line comes to the second inputs of the adder. Adders 138, 149, 160 are identical, represented by K555IM6 microcircuits, perform the addition of codes of the corresponding samples of the previous and next lines. Halving the sum code in half is done by connecting the output of the adder and the inputs of the block 165/166, 167 / pulse amplifiers, as described on page 33. The second delay element blocks 139, 150, 161 delay the code signals for 24 ns of operation of the adders 138, 149, 160 so that the codes of the current line from blocks 139, 150, 161 and the intermediate line codes from the adders arrive synchronously at the inputs of their blocks 162- 167 pulse amplifiers. Blocks of pulse amplifiers are represented by 533AP6 microcircuits with a response time of 18 ns [11 p.128].

Each block 162-167 has 12 pulse amplifiers.

The radiation modulation unit 168 performs luminance modulation of the two emitters 213, 214 of three primary colors, respectively, the values of the codes of the video signals of the current and intermediate lines. The first emitter 213 modulated in brightness beam reproduces 400 lines encoded and transmitted from the transmitting side. The second emitter 214 modulates the brightness of the beam reproduces 400 intermediate lines, the sample codes of which were obtained by adders 138, 149, 160. The reproduced frame is 800 active lines with 1200 samples in each, with 960,000 elements of resolution in the frame. The emitters use HL MP LEDs manufactured by the Hewlett-Packard company [12 p. 71]. For red radiation, LEDs HL MP-AL 00 with a light intensity of 400 mcd, a wavelength of 0.59 μm and a current of 0.02 A are accepted for green radiation, LEDs HL MP-AM00 with a light intensity of 800 mcd, a wavelength of 800 μd, a wavelength of 0.526 μm and a current are adopted 0.02 A, for blue radiation, HL MP-AB00 LEDs with a light intensity of 300 μd, a wavelength of 0.475 μm and a current of 0.02 A were adopted. The distribution of LEDs of the same color by discharge weight in table 2.

table 2 Discharge number in code 1 senior rank 2 3 4 5 6 7 8 low order LEDs per discharge 4 2 1 1 1 1 1 1 Multiplicity of the filter - - - 2 ^x 4 ^x 8 ^x 16 ^x 32 ^x

The total emission of the three-color LEDs of the two emitters is mixed by the optical system 215 when focusing in two color spots located vertically on the reflector of the first piezoelectric deflector 172/10 /. The brightness modulation is performed by switching on the LEDs in the matrix according to the weight of the discharge according to Table 2. The brightness, saturation and color tone of the resulting color on the screen are determined by the total energy and the mutual ratio of the three colors R, G, B of the emitter. The resolving element on the reflector of the first piezoelectric deflector 172 adopted 0.02 × 0.02 mm, the length of the reflector adopted 2 mm / to facilitate alignment /. The resolving element on the reflector of the second piezoelectric deflector 180 adopted 0.03 × 0.03 mm / 0.0009 ^-6 m ² /. The length of the reflector of the second piezoelectric deflector should be at least 36 mm / 0.03 mm × 1200 /. Width is taken 2 mm. The projection optical system 183 / Fig. 10/ is represented by a mirror-lens system [5 p.370], which includes a spherical mirror, a flat mirror with an inclination of 45 ° relative to the optical axis of the spherical mirror and a correction lens. A flat mirror [13 c. 188] allows you to extend the path of the rays and reduce the direct distance to the screen 184. The magnification of the image by the projection optical system 83 on the screen 184 is taken 20 ^x / fold /, while the image size on the matte screen 184 is:

horizontal 20 × / 0.03 mm × 1200 / = 720 mm,

vertical 20 × / 0.03 mm × 800 / = 480,

diagonal 865 mm, 86.5 cm.

The total luminous intensity of one emitter 213/214 /, taking into account that the LEDs of all colors have a light intensity of the blue LED 300 mcd / 0.3 cd /, is:

where 3 is the number of colors in the emitter,

0.3 cd - light intensity of the blue LED,

in parentheses: in the numerator, the number of LEDs by digits,

the denominator is their binary code coefficients.

Loss of radiation from the emitter 213/214 / to the reflector of the second piezoelectric deflector 180 4 times, from the second piezoelectric deflector to the projection optical system 2 times and in the projection optical system to the screen 184 10 times, a total of 16 times.

The maximum possible brightness of one deploying element of 0.36 mm ² / 0.6 × 0.6 mm / is:

where 7.17 is the radiation power of one emitter,

16 - the frequency loss of radiation,

0,36 · 10 ^-6 m ² - the area of the deploying light element.

The piezoelectric deflector 172 according to the control voltages from the amplifier 171 produces a horizontal scan of the rays on the reflector of the second piezoelectric deflector 180, which performs a vertical scan of the beams from the control voltages from the amplifier 179. The condition for the block 201 to issue a frame sync pulse / Fig. 16/ is the simultaneous arrival at the counting inputs of the counters 231, 232, 233 of the pulses of three codes 11111111 from the shapers 133, 144, 155 pulses and the arrival of the SSI pulse from block 196. At the time of the 600th count The 400th line of an even frame emitter 186 emits an infrared pulse / frequency 12.5 Hz /. The radiation pulse is received (Fig.17) by the photodetector 240 in the block 187 for separate observation of frames and is converted into an electrical signal. The pulse generator 241 generates an electric pulse of the corresponding amplitude and duration, which is the control pulse for the piezoelectric motor 242. For each control pulse of 12.5 Hz, the motor 242 rotates frames with neutral light filters 90 °. When playing the right image on the screen 184 for 0.08 s, the right eye window in the case of 245 points is opened synchronously with it, the viewer with the right eye observes the right image, the left eye window is closed by neutral filters. When the left image is displayed on the screen 184 for 0.08 s, the left window is opened synchronously with it, the viewer sees the left image with the left eye, the right eye window is closed by neutral filters 244. The key 198 is opened by the SSI pulses, the counter 199 pulses is 9-bit, it leads pulse count 6 MHz, cycle count 300 pulses. With the arrival of a 296 line sampling pulse, the decoder 200 decrypts the binary code of the 296 pulse and, with the signal from the first output, opens the keys 188, 189 in the first and second sound reproduction channels, which pass three sound codes that enter the blocks 190, 191 of sound registers containing three 8-bit registers. In block 190, 1-8 bits of the sound code are received, in block 191, 9-16 charges of sound codes are received. From registers 190, 191, sound codes with signals _Ud 60 kHz are output to DAC 192, which convert sound codes into analog signals passing low-pass filters 193, amplified in power amplifiers 194 and reproduced by loudspeakers 195. With the arrival of the 300th pulse in the 199 counter, the 300th pulse line sampling pulse, the decoder 200 generates a signal from the second output, which closes the keys 188, 189, resets the counter 199 and closes the key 198. With the arrival of the next SSI pulse at the input of the key 198, the processes are repeated.

System operation

From the photodetectors 28, 29, 30 and 39, 40, 41, six analog video signals after amplification by the preliminary amplifiers are fed to the ADCs 45, 46, 47 and 48, 49, 50, respectively. Two audio signals are fed to the ADC inputs 51, 52. The video signals are converted to 8-bit codes with a sampling rate of 12 MHz. Sound signals are converted to 16-bit codes with a sampling rate of 60 kHz. Shapers 55, 56, 57 codes form consecutive codes from parallel codes and replace the representation of units from pulses in them with positive / odd samples of a line / half-sine wave and negative / even samples / half-sine of a 48 MHz monofrequency. The clock frequency in the system is 48 MHz. On the transmitting side, 400 lines in a frame of 600 samples in each are encoded. Line scan line by line, frequency 20 kHz, frame rate 50 Hz: 25 Hz of the right image and 25 Hz of the left image. The video signals of the right and left images follow in 0.08 alternately / 4 frames /. The distance between the optical axes of the right 2 and left 11 lenses corresponds to the optimal stereoscopic effect for human vision. The information is transmitted by three channels of the transmitter 64. The first channel transmits information of codes E _RP and E _{RL with the} upper side frequency of 528 MHz of the first carrier, the second channel transmits information of codes E _VP and E of the _{OHL with the} lower side frequency of 432 MHz of the first carrier, the third channel transmits information of codes E _GP and E _{GL with an} upper side frequency of 624 MHz of the second carrier. The total occupied band on the air is 316.8 Hz. Information transfer rate: 3 × / 48 MHz × 2 / = 288 Mbps.

The receiving side receives three radio signals in parallel with the three paths of receiving and processing video codes, amplifies them, detects them, extracts horizontal and frame sync pulses from the SRI, KSI, the frequency synthesizer reproduces two carriers, the codes of the video signals are separated by its frame processing channels, the number of samples in each doubles line, doubles the number of lines in the frame, the luminance modulation of the radiation of two emitters is performed, and the electron-optical scan of the color image on the screen 184 is performed simultaneously in two lines alternately / four frames in a row / of the right and left image, which are separately observed by the right and left eyes of the viewer. Electron-optical scanning of the frame is performed by the first 172 and second 180 piezoelectric deflectors, the projection optical system 183 performs a magnification of the image on the screen 184 by 20 times. The size of the image on the screen is 720 × 480 mm, along the diagonal of 865 mm. Stereo sound is reproduced by two sound channels. The playback frame has 800 active lines with 1200 samples per line. The frame format is 1.5: 1, the resolution elements in the frame are 960000. The system can also perform normal / two-coordinate / television broadcasting, for this the viewer does not need to wear glasses.

Table 1 Technical parameter Value Transmission side Color coding 2: 2: 2, E _R , E _G , E _B Ranges Used 430-790 MHz, 21-60 can Carrier frequencies two / option / 480 MHz, 576 MHz Transmission of video signal codes E _RP , E _RL 528 MHz upper side. f ₁ - E _VP , E _VL 432 MHz, bottom side. f ₁ - E _GP , E _GL 624 MHz upper side. f ₂ System Clock 48 MHz Occupied band on air 316.8 Hz Number of active lines / frame rate 400/50 Hz Line scan in frame Line by line The number of encoded samples per line 600, / 200 × 2 / Video Sampling Rate 12 MHz Line Scan / Line Frequency 10 kHz / 20 kHz Line length 50 μs / 1 MHz: 20 kHz / Coding method separate, linear PCM Video coding 255 levels, 8 times, 2 ⁸ Audio sampling 60 kHz / 20 kHz × 3 / Sound coding 65536 level, 16 times, 2 ¹⁶ Information transfer rate 288 Mbps, / 96 × 3 / Receiving side Color Correction 4: 4: 4 Number of active lines / frame rate 800/50 Hz The number of samples per line 1200/600 × 2 / Video Signal Code Frequency 24 MHz / 12 MHz × 2 / Information playback speed 1152 Mbps, / 384 × 3 / Frame resolution 960000 ale. / 1200 × 800 / Frame format 1.5: 1 Maximum brightness of one expanding element on the screen 1244000 cd / m ²

Used sources

1. Patent No. 2194370, cl. H 04 N 11/24, bull. 34 for 2002, a prototype.

2. P. Lindsay, D. Norman. “Processing of information in humans”, M., 1974, p.197, 277.

3. Radio transmitting devices, M. S. Shumilin and others, 1981, M., S. 234, 235.

4. Fridland M.V., Soshnikov V.G. “Automatic control systems in video recording devices”, M., p. 118, fig. 5.5, p. 122, fig. 5.10.

5. V.F. Samoilov, B.P. Khromoi. Television, M., 1975, p. 367, 370, 389.

6. “Instruments and control systems”, No. 1, 1990, p.40.

7. Ilyin V.A. Telecontrol and telemetry, M., 1982, p. 274.

8. Brodsky M.A. Color television sets, Minsk, 1988, p. 86, fig. 2.55, p. 132, fig. 4.2.

9. Radio communications, broadcasting and television. Ed. A.D. Fortushenko, M., 1981, p. 146.

10. Barkan V.F., Zhdanov V.K. Amplification and pulse technology, M., 1981, p. 209.

11. Digital integrated circuits, Minsk, 1991, S. 128, 231, 258.

12. “Radio” No. 7, 1998, p. 71.

13. E. Iceberg “Television? ... It is very simple!”, Energy, L., 1967, p. 188.

14. Shilo V.A. Popular digital circuits. Chelyabinsk, 1989, p. 222.

Claims (1)

A digital stereo television system, comprising a transmitting side including a photoelectric converter, first, second, third analog-to-digital converters (ADCs), the inputs of which are connected to the corresponding outputs of the photoelectric converter, the first and second ADCs of a sound signal, to the information inputs of which sound signals are supplied, serially connected sine oscillator and frequency synthesizer, first and second code generators, first and second information inputs of the first the code driver is connected to the outputs of the first ADC and the first ADC of the sound signal, the second information input of the second ADC is connected to the output of the second ADC of the sound signal, the first and second self-propelled pulse distributors, the outputs of the first self-propelled pulse distributor are combined and connected to the third information input of the second code generator, the outputs of the second self-propelled pulse distributor are combined and connected to the fourth information input of the second code generator, the first synthesis output the frequency generator is connected to the first control input of the second code generator, the second output is connected to the second control input of the second code generator and to the first control inputs of the first and second ADC sound signals, the third output of the frequency synthesizer is connected to the second control inputs of the first and second ADC sound signals, fourth the output is connected to the third control input of the second code generator, the fifth output is connected to the fourth control input of the second code generator and to the third control inputs of the second and second ADCs of the sound signal, and the radio signal transmitter containing two channels, the first includes a serially connected carrier frequency amplifier, the input of which is connected to the eighth output of the frequency synthesizer, an amplitude modulator and an output amplifier, the second channel includes a serially connected amplitude modulator, the input of which is connected to the output of the carrier frequency amplifier in the first channel, and the output amplifier, the second input of the amplitude modulator of the first channel is connected to the output of the first code generator, each the amplitude modulator includes a ring modulator and a bandpass filter connected in series, the photoelectric transducer comprises a first lens, a first piezoelectric deflector with an end face located in the focal plane of the first lens, a second piezoelectric deflector with an end face reflector, and a horizontal scanning unit, the input of which is connected to the seventh output frequency synthesizer, and the first amplifier, the output of which is connected to the first input of the first piezoelectric deflector, the first source is positive of the second reference voltage, the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector, the second source of negative reference voltage, the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector, connected in series to the vertical scan unit, the first and second inputs of which are connected to the fifth and sixth the outputs of the frequency synthesizer, and a second amplifier, the output of which is connected to the first input of the second piezoelectric deflector, a third source of positive reference voltage, the output to of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector, the fourth source of negative reference voltage, the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector, the first and second dichroic mirrors located one after the other and against the reflector of the second piezoelectric deflector, three micro-lenses, three photodetectors , three preamplifiers, the outputs of which are the outputs of the photoelectric converter, the input window of the first photodetector is optically connected through a the first micro-lens and the first dichroic mirror with a reflector of the second piezoelectric deflector, the input window of the second photodetector is optically connected through the second micro-lens and through both dichroic mirrors with the reflector of the second piezoelectric reflector, the input window of the third photodetector is optically connected through the third micro-lens, the second dichroic mirror and through the first dichroic mirror the second piezoelectric deflector, the frame scanning unit of the photoelectric transducer contains a series-connected element And, rear the generating oscillator and the summing amplifier, the second input of which is connected to the first input of the And element, the control input of the summing amplifier is connected to the output of the And element, the output of the summing amplifier is the output of the frame scanning unit and connected to the first input of the second amplifier, the first and second inputs of the And element are inputs of the vertical scanning unit, the summing amplifier includes a pulse counter and a decoder connected in series, the first and second keys, the first and second pulse shapers, and the output gain l, the signal inputs of the keys and the counting input of the pulse counter are combined and are the second input of the summing amplifier, the first input of which is the first input of the output amplifier, the first control input of the first key, the second control input of the second key and the control input of the pulse counter are combined and are the control input of the summing amplifier , the second control input of the first key and the first control input of the second key are combined and connected to the output of the decoder, the output of the first key is connected to the input of the first pulse shaper, the output of the second key is connected to the input of the second pulse shaper, the outputs of the pulse shapers are combined and connected to the second input of the output amplifier, the output of which is the output of the summing amplifier, the first, second, and third ADCs are identical and each contains a serially connected amplifier and a piezoelectric reflector with a reflector on end, a source of positive reference voltage, the output of which is connected to the second inputs of the amplifier and piezoelectric deflector, a source of negative reference voltage the output of which is connected to the third inputs of the amplifier and the piezoelectric deflector, an emitter from a pulsed LED, a slit diaphragm, and a micro lens, and an encoder whose outputs are ADC outputs, the control input is a pulse LED input, the first and second ADCs of the sound signal are identical and each contains serially connected voltage divider, key block, matching amplifier, amplifier and piezoelectric deflector with a reflector at the end, a source of positive reference voltage, the output of which is connected to the second input I will give an amplifier and a piezoelectric deflector, a source of negative reference voltage, the output of which is connected to the third inputs of the amplifier and a piezoelectric deflector, an emitter of a pulsed LED, a slit diaphragm and a micro lens, the first decoder, encoder and second decoder connected in series, the outputs of which are connected to the corresponding inputs of the first decoder and inputs block of keys, contains a pulse counter connected in series, a third decoder and a block of registers, the information inputs of which are connected to the output the encoder and the first three control inputs are connected to the outputs of the third decoder, the ADC input is the input of the voltage divider, the first control input is the counter input of the pulse counter, the second is the combined input of the pulse LED and the control input of the register block, the third is the control input of the pulse counter, the output is the outputs of the register block, the second code generator contains a serially connected trigger and a switching unit, the inputs of which are the first information input of the code generator c, and the three channels, the first and second channels are identical, their inputs are connected to the corresponding outputs of the switching unit, and the outputs of the three channels are combined, the first channel includes a series of AND elements, a first and second OR element, and an output switch, and a self-propelled pulse distributor, the second channel includes a series-connected block of AND elements, a third and fourth OR element, and an output switch, and a self-propelled pulse distributor, the first inputs of the blocks of AND elements are connected to the corresponding outputs of the switching unit and, the second inputs of the blocks of AND elements are connected to the outputs of the self-propelled pulse distributor of their channel, the outputs of the output keys are combined and are the first output of the second code generator, the third channel includes two blocks of AND elements, the inputs of which are the second information input, the fifth and sixth elements OR, the output the fifth OR element is connected to the second input of the second OR element in the first channel, the output of the sixth OR element is connected to the second input of the fourth OR element in the second channel, and two self-propelled valves pulses, the outputs of which are connected to the second inputs of the respective blocks of AND elements, and include the first and second keys, and series-connected pulse counter and decoder, two outputs of which are connected respectively to the first and second control inputs of the first and second keys, the third output of the decoder is the second output the second shaper codes connected to the input of the first self-propelled pulse distributor, the output of the first key is connected to the inputs of the self-propelled pulse distributors in the first and second channel the output of the second key is connected to the inputs of the self-propelled pulse distributors in the third channel, the first control input is the trigger input, the second is the combined key input and the counting input of the pulse counter, the third is the combined input of the signal inputs of the output keys, the fourth is the control input of the pulse counter, and comprising a receiving side including an antenna, a touch control unit, first and second paths for receiving and processing video signal codes, the inputs of which are connected to the antenna, six pulse amplifier units th, a channel for generating control signals, two channels for reproducing sound, the first path for receiving and processing codes of video signals contains a serially connected radio signal receiving unit, the first input of which is connected to the antenna, the second inputs are connected to the first group of outputs of the touch control unit, a radio frequency amplifier, and a bipolar amplitude detector , the first and second pulse shapers connected respectively to the first and second outputs of the bipolar amplitude detector, and the video signal channel E _R containing the video signal register E _R , the input of which is connected to the output of the first shaper of its path, series-connected code processing unit, the inputs of which are connected to the outputs of the video signal register E _R , the first block of delay elements and the adder, and the second block of delay elements, whose inputs are connected to the outputs of the code processing unit, the first inputs of the adder are connected to the outputs of the code processing unit, its second inputs are connected to the outputs of the first block of delay elements, the outputs of the second block of delay elements and the adder is connected to the inputs of the respective blocks of pulse amplifiers, the second path for receiving and processing codes of video signals contains a series-connected block for receiving a radio signal, the first input of which is connected n to antenna, second inputs connected to the first group of sensory outputs of the control unit, a radio frequency amplifier and a bipolar amplitude detector, the first and second pulse shapers are connected respectively to the first and second outputs of the bipolar amplitude detector, and a video channel E _IN including the first and second registers of the video signal E _IN , the information inputs of which are connected to the outputs of the first and second pulse shapers of their path, the first block of delay elements, the adder and the second block of delay elements, the first inputs of the adder are connected to the inputs of the second block of delay elements, and the second inputs of the adder are connected to the outputs of the first block of delay elements , the outputs of the second block of delay elements and the adder are connected to the inputs of the corresponding blocks of pulse amplifiers, the radiation modulation unit, the inputs of which are connected to the outputs of There are blocks of pulse amplifiers, a series-connected frequency divider, a horizontal scanning unit, a first amplifier and a first piezoelectric deflector with a reflector at the end, a first source of positive reference voltage, the output of which is connected to the second inputs of the first amplifier and first piezoelectric deflector, and a second source of negative reference voltage, the output of which connected to the third inputs of the first amplifier and the first piezoelectric deflector, connected in series frame scan unit, the second amplifier and the second piezode a reflector at the end, a third source of positive reference voltage, the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector, a fourth source of negative reference voltage, the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector, and an opaque screen, the reflector of the second piezoelectric deflector connected to the reflector of the first piezoelectric deflector, which is optically connected to the radiating side of the radiation modulation unit, the code processing unit includes a trigger p, the input of which is the control input of the block, the first to fourth registers, the first to third block of delay elements, an adder and 16 diodes, the control input of the adder is connected to the trigger input, the information inputs of the first and second registers are connected bitwise and connected to the outputs of the first block of delay elements , the information inputs of the third and fourth registers are combined bitwise and connected to the outputs of the second block of delay elements, the first output of the trigger is connected to the control inputs of the second and third registers, the second trigger output is connected to the control inputs of the first and fourth registers, the outputs of the first register are connected through diodes to the first inputs of the adder, the outputs of the second register are connected to the first inputs of the adder, the outputs of the fourth register and the outputs of the third register are connected via diodes to the second inputs of the adder, the outputs of which are connected to the inputs of the third block of delay elements, the outputs of which are the outputs of the code processing unit, each sound reproduction channel includes the first and second keys, the first and second blocks and sound registers and a series-connected digital-to-analog converter (DAC), a low-pass filter, a power amplifier and a loudspeaker, in the first sound reproduction channel, the inputs of the first and second keys are connected respectively to the outputs of the first and second pulse shapers in the first path for receiving and processing video signal codes , and the outputs of the first and second keys are connected to the information inputs of the first and second blocks of sound registers, the outputs of which are connected respectively to the DAC inputs of their channel, The first and second keys in the second channel are connected to the information inputs of the first and second blocks of the sound registers of their channel, the outputs of which are connected to the DAC inputs of the second channel, the channel for generating control signals includes a series-connected block for selecting horizontal sync pulses, a frequency synthesizer, a key, a pulse counter, and a decoder, and a frame sync selection block, two inputs of a horizontal sync selection block are connected to the outputs of the first pulse shapers in the first and second path receiving and processing codes of video signals, the output of the unit is connected to the first input of the synthesizer, to the first control input of the key, to the frequency divider, to the first input of the frame scan unit and to the corresponding input of the frame sync selection block, the input of which is connected to the output of the second pulse shaper in the second path receiving and processing codes of video signals, and the output is connected to the second input of the frame scanning unit, the second inputs of the frequency synthesizer are connected to the second group of outputs of the touch control unit, vy output is connected to the signal input of the key to the first control inputs of the video registers E _R , E _IN , the first output of the decoder is connected to the first control inputs of the first and second keys in both sound reproduction channels, the second output of the decoder is connected to the second control inputs of the first and second keys in both sound reproduction channels, to the control input of the pulse counter and to the second control input of the key, block frame scan and the summing amplifier in it on the receiving side are identical to the frame scan unit and the summing amplifier in it on the transmitting side, the radiation modulation unit contains optical system, the first and second emitters of three primary colors, each of which includes the corresponding number of LEDs of each color, the emitters of three primary colors are located in the rear focal plane of the optical system, and their inputs are connected to the outputs of the respective six blocks of pulse amplifiers, the output of the radiation modulation unit through an optical system it is connected to the reflector of the first piezoelectric deflector, the horizontal sync pulse extraction unit includes three pulse counters, three NOT elements, two AND elements and a diode, input The odes of the first, second, third elements are NOT connected to the inputs of the first, second, third pulse counters, the outputs of the elements are NOT combined and connected to the control inputs of the pulse counters, the output of the unit through the diode is also connected to the control inputs of the pulse counters, the outputs of the first and second pulse counters are connected to the inputs of the first element And, the output of which and the output of the third pulse counter are connected to the inputs of the second element And, the inputs of the pulse counters are the first, second and third inputs of the block, the block is highlighted The frame synchronization pulse includes one pulse counter, the AND element and the NOT element, the counting input of the pulse counter is the input of the block, the input of the element is NOT connected to the input of the pulse counter, the output of the element is NOT connected to the control input of the pulse counter, the output of the pulse counter is connected to the first input of the AND element , the second input of which is also the input of the frame sync pulse extraction unit, characterized in that on the transmitting side a line of a multi-element photodetector is introduced into the first, second, third ADCs, input the windows of which are optically connected through the reflector of the piezoelectric deflector to the emitter, and its outputs are connected to the encoder inputs, the fourth, fifth and sixth ADCs identical to the first, second and third ADCs, the third code driver, the trigger, the first and second keys and the pulse counter, the trigger input is connected to the sixth input of the frequency synthesizer, the first trigger output is connected to the first control input of the first key and to the second control input of the second key, the second trigger output is connected to the second control input of the first key and to the first control input of the second key, the signal inputs of the keys are connected in parallel to the first output of the frequency synthesizer, the output of the first key is connected in parallel to the clock inputs of the first, second, third ADCs, the output of the second key is connected in parallel to the clock inputs of the fourth, fifth, sixth ADCs, output the first and fourth ADCs are combined and connected to the first information input of the first code generator, the third and fourth information inputs of which are connected respectively to the outputs of the first and second one pulse distributor, the output of the second and fifth ADCs are combined and connected to the first information input of the second code generator, the output of the third and sixth ADCs are combined and connected to the first information input of the third code generator, the second and third information inputs of which are connected respectively to the outputs of the first and second self-propelled pulse distributors, the first to fourth control inputs of the first code generator are connected respectively to the first, second, fourth and fifth outputs frequency synthesizer, the first code generator is identical to the second code generator, the second output of which is connected to the counting input of the pulse counter, and the first code generator has one output, the control input of the pulse counter is connected to the sixth input of the frequency synthesizer, the output of the second discharge of the pulse counter is connected to the input of the second a self-propelled pulse distributor, a line of a multi-element photodetector is introduced into each of the first and second ADCs of the sound signal, the input windows of which are optically connected through a piezoelectric deflector with a radiator, and its outputs are connected to the inputs of the first decoder, in the photoelectric converter, the free end of the second piezoelectric deflector is made of two faces at an appropriate angle to each other, each face of which has a reflector, the first reflector of the second piezoelectric deflector is optically connected to the reflector of the first piezoelectric deflector, in a photoelectric converter introduced a second lens located to the left of the first lens at an appropriate distance and whose optical axis parallel to the optical axis of the first object, the third piezoelectric deflector with a reflector at the end, the reflector is located in the focal plane of the second lens and is optically connected to the second reflector of the second piezoelectric deflector, the third amplifier, the first input of which is connected to the output of the horizontal scanning unit, the output is connected to the first input of the third piezoelectric deflector, the fifth source of positive reference voltage, the output of which is connected to the second inputs of the third amplifier and the third piezoelectric deflector, the sixth source of negative op voltage, the output of which is connected to the third inputs of the third amplifier and the third piezoelectric deflector, introduced the third and fourth dichroic mirrors located one after the other and against the second reflector of the second piezoelectric deflector, fourth, fifth, sixth micro lenses, fourth, fifth, sixth photodetectors, fourth, fifth the sixth preamplifier, the outputs of which are the outputs of the photovoltaic converter, the input window of the fourth photodetector is optically connected through the fourth micro lens and the third an ichroic mirror with a second reflector of the second piezoelectric deflector, the input window of the fifth photodetector is optically connected through the fifth micro-lens and through both dichroic mirrors with a second reflector of the second piezoelectric reflector, the input window of the sixth photodetector is optically connected through the sixth micro-lens, the fourth dichroic mirror and the second second reflector piezoelectric deflector, the outputs of the fourth, fifth, sixth photodetectors are connected respectively to the inputs of the fourth, fifth and sixth pr digestive amplifiers, the outputs of which are connected respectively to the inputs of the fourth, fifth and sixth ADCs, a third channel is introduced into the radio signal transmitter, including a second carrier frequency amplifier connected in series, the input of which is connected to the ninth output of the frequency synthesizer, an amplitude modulator, the second input of which is connected to the first output the second code generator, and the output amplifier, the second input of the amplitude modulator of the second channel is connected to the output of the third code generator, which contains after A trigger and a switching unit, and two identical channels, the channel inputs are connected to the outputs of the switching unit and their outputs are combined and are the output of the third code generator, the first channel includes a series of AND elements, a first and second OR element, and an output key, and a self-propelled pulse distributor, the second channel includes a block of AND elements connected in series, the third and fourth OR elements and an output key, and a self-propelled pulse distributor, the first inputs of the AND blocks the second inputs of the elements And these blocks are connected to the outputs of the self-propelled pulse distributor of their channel, the first information input is the inputs of the switching unit, the second and third information inputs are the second inputs of the second and fourth elements OR, the first control input is the trigger input , the second - the combined inputs of the self-propelled pulse distributors, the third - the combined signal inputs of the output keys, the combined output of which is by the third code generator, the first, second, third control inputs of which are connected respectively to the first, second and fourth outputs of the frequency synthesizer, a third path for receiving and processing codes of video signals is introduced on the receiving side, including a series-connected radio signal receiving unit, the first input of which is connected to the antenna , the second group of inputs is connected to the first group of outputs of the touch control unit, a radio frequency amplifier and a bipolar amplitude detector, the first and second impulse drivers pulses and video channel E _G containing the first and second registers of the video signal E _G the information inputs of which are connected to the outputs of the first and second pulse shapers, respectively, and the first control inputs are connected to the first output of the frequency synthesizer, a series-connected code processing unit whose inputs are connected to the outputs of the first and second video signal registers E _G , the first block of delay elements and the adder, and the second block of delay elements, the inputs of which are connected to the outputs of the code processing unit, the first inputs of the adder are connected to the inputs of the second block of delay elements, the second inputs of the adder are connected to the outputs of the first block of delay elements, the outputs of the second block of delay elements and the adder are connected to the inputs of the corresponding blocks of pulse amplifiers in the channel of the video signal E _R entered the second register of the video signal E _R the information input of which is connected to the output of the second pulse shaper in the first path for receiving and processing video codes, and the first control input is connected to the first output of the frequency synthesizer, the outputs of the second video signal register E _R connected to the second inputs of the channel code processing unit in the channel of the video signal E _IN a code processing unit has been introduced, the inputs of which are connected to the outputs of the first and second video signal registers E _IN and the outputs are connected to the inputs of the first and second blocks of delay elements and to the first inputs of the adder, a projection optical system is introduced on the receiving side, including a spherical mirror in series, in the focal plane of which there is a reflector of the second piezoelectric deflector, a flat mirror with an inclination of 45 ° relative to the optical axis a spherical mirror and a corrective lens, in the external focal plane of the projection optical system there is a matte screen, which through the projection optical istemu, first and second reflectors optically connected to pezodeflektorov radiating side light modulation unit, entered the second frequency divider, the emitter unit and the separate observation of frames, the second output frequency synthesis is connected to the second (clock) inputs of the control registers of video signals E _R , E _G , E _IN and to the second (clock) control inputs of the blocks of sound registers, to the first control inputs of which the third output of the frequency synthesizer is connected, the fourth output is connected to the control inputs of the code processing blocks, the fifth output is connected to the third inputs of the radio signal reception blocks in the first and second reception paths and processing of video signal codes, the sixth output is connected to the third input of the radio signal receiving unit in the third path of receiving and processing video signal codes, the seventh output is connected to the third control inputs of the first blocks delay elements and to the control inputs of adders, the eighth output is connected to the first control inputs of the first blocks of delay elements, the fifth and sixth registers are entered in the code processing blocks, the inputs of the fifth register are connected to the outputs of the first register, the control input is connected to the first output of the trigger, the inputs of the sixth register connected to the outputs of the third register, the control input is connected to the second output of the trigger, the outputs of the fifth and sixth register are bitwise combined with the outputs of the third block of delay elements and are the outputs of the code processing unit, the first and second information inputs of which are the inputs of the first and second blocks of delay elements, the third input of the horizontal sync selection block is connected to the output of the first pulse shaper in the third path for receiving and processing video signal codes, the second and third are inserted into the frame sync selection block pulse counters, the second and third elements are NOT, the second and third elements AND, the counting inputs of the first, second and third pulse counters are the inputs of the block and connect are connected to the outputs of the second pulse shapers, respectively, in the first, second, third paths for receiving and processing video codes, the inputs of the elements are NOT connected respectively to the counting inputs of the first, second, third pulse counters, the control inputs of the pulse counters are combined and connected to the combined outputs of the elements NOT, the outputs the first and second pulse counters are connected to the inputs of the first AND element, the output of which and the output of the third pulse counter are connected to the inputs of the second AND element, the output of which is even the fourth input of the frame pulses extraction unit is connected to the inputs of the third AND element, the output of which is the output of the unit and which is connected through the diode to the control inputs of the pulse counters, the emitter contains a pulsed infrared LED, the output window of which is the output of the emitter, the input of the emitter is connected to the output of the second frequency divider (2: 1), the input of which is connected to the output of the frame sync pulse extraction unit, the separate frame monitoring unit includes a series-connected photodetector infra of red radiation, a pulse shaper and a piezoelectric motor, on the shaft of which there are fixed right and left cylindrical frames, in each of which two neutral filters of the corresponding density are fixed, each neutral filter occupies one fourth of the cylindrical surface of the frame, neutral filters are arranged in a cylindrical frame against each other through 180 °, the position of the neutral filters in the right cylindrical frame is offset by 90 ° relative to them in the left cylindrical the rim, an infrared photodetector, a pulse shaper and a piezoelectric motor with a shaft and cylindrical frames mounted thereon on the outside of the spectacle case having right and left eye windows, against which the right and left cylindrical frames are respectively located on the outside.

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