RU2248103C1 - Digital television system - Google Patents

Abstract

FIELD: radio communications.

SUBSTANCE: system, at transferring side, additionally has third code generator, in transceiver - third channel, at receiving side - third receiving line for processing video signals codes, including block for receiving radio signal, frequency amplifier, bipolar amplitude detector and codes processing channel, in each code processing channel for video signals E_R, E_G, E_B block for processing codes and codes accumulator are inserted, radiation modulation block is made with three hundred channels, into channel for forming control pulses frequency synthesizer and doubling device for frame synchronous pulses are inserted.

EFFECT: higher efficiency.

18 dwg, 2 tbl

Description

The invention relates to radio communications technology, can be used for digital television in the UHF range reserved for analog television.

The prototype adopted a digital television system [1], containing on the transmitting side a photoelectric converter, three ADCs, the inputs of which are connected to the outputs of the photoelectric converter, a fourth and fifth ADCs of a sound signal, a sine wave oscillator, a frequency synthesizer, the first and second code generators, the first and a second self-propelled pulse distributor, a two-channel transmitter, each channel of which includes a carrier frequency generator, a single-band signal shaper and an output amplifier, on on the receiving side, which contains an antenna, a touch control unit, two paths for receiving and processing video codes, two sound channels, a channel for generating control signals, three pulse amplifier units, a radiation modulation unit, a frequency divider, horizontal and vertical scanning units, a first amplifier and a first piezoelectric deflector , a second amplifier and a second piezoelectric deflector and a matte screen. According to a first channel of video signals transmitted codes E _R and E _B, a second channel - E _G. On the receiving side, two radio signals are received, amplified, detected, and without converting the codes into analog video signals, a color image of the frame with a single-line scan of it is reproduced on the matte screen. Clock frequency 54 MHz, occupied band 213 Hz, active lines 625, samples in line 854, line scan interlaced. The disadvantage of the prototype: the scan image on a matte screen that does not have afterglow, one line leads to a low average brightness of the reproduced image, leading to poor visual perception of the expanded image.

The purpose of the invention is to increase the average brightness reproduced on the receiving side of the image.

The technical result is to increase the average brightness of the reproduced image by 90 · 10 ³ times against the prototype. The technical result is achieved by scanning each field of the frame simultaneously with 300 lines and repeating their sweep over the time of the field of the frame 300 times. The transmitting side generates three streams of video signal codes. Two carrier frequencies are used. Information on the color tone is carried by the side frequency of the carrier, and on the color brightness is the code of the amplitude of the video signal. The color saturation is set by the spectral band of the LEDs used in the radiation modulation unit. The frequency of the lines is 15 kHz, the number of active lines in the frame is 600, the samples in the line on the transmitting side 500, and in the reception in the reproduced image 1000. The receiving side receives three radio signals with three paths for receiving and processing codes of video signals, detects them, doubles the number of samples in a line in two times, the code stores accumulate codes of line samples per field of the frame, the radiation modulation unit performs luminance modulation of radiation simultaneously by 300 emitters of all lines of the field of the frame, the image of the field of the frame is scanned and the matte screen simultaneously with all the lines of the frame field / 300 / and the repetition of their sweep over the frame field time 300 times. System specifications in table 1.

The essence of the claimed system is that in a digital television system containing a photoelectric converter on the transmitting side, three ADCs, the inputs of which are connected to the outputs of the photoelectric converter, a fourth and fifth ADCs, the inputs of which are fed with sound signals, a sinusoidal oscillation generator, a frequency synthesizer, the first and a second code shaper, two self-propelled pulse distributors, a two-channel transmitter, a sensor control unit on the transmitting side, two video signal reception and processing paths there are three pulsed amplifier units, a radiation modulation unit, a horizontal scanning unit, a first amplifier and a first piezoelectric deflector, a second amplifier and a second piezoelectric deflector, two sound channels and a control signal generation channel, a third code generator is introduced on the transmitting side, a third channel is inserted into the transmitter, on the receiving side, a third path for receiving and processing codes of video signals, a projection optical system, is introduced into the first and second paths for receiving and processing codes of video signals, each processing unit heel codes and codes the drive in channel generating control signals introduced synthesizer frequency and vertical sync frequency doubler, light modulation unit is made of three hundred channels.

The block diagram of the transmitting side in figure 1, the interlaced scan of the frame and the shape of the control voltage in figure 2, the structure of digital streams from the transmitting side in figure 3, the ADC of the video signal in figure 4, the design of the piezoelectric deflector in figure 5, the ADC of the sound signal on Fig.6, the first and second code generators in Fig.7, the third code generator in Fig.8, the summing amplifier in Fig.9, the structural diagram of the receiving side in Fig.10, the circuit diagram of the bipolar amplitude detector in Fig.11, the modulation unit radiation in FIG. 12, code processing unit in Fig. 13, the code accumulator in Fig. 14, the functional block diagram of the register block in Figs. 15 and 16, the horizontal / frame / clock pulse extracting unit in Fig. 17, the frequency spectrum of the output signals of the transmitter in Fig. 18.

The transmitting side includes / Fig. 1 / a photoelectric transducer 1, which is a sensor of signals of three primary colors R, G, B, comprising a lens 2, a first piezoelectric reflector 3 with a reflector at the end, a first source of positive reference voltage 4, a second source of negative reference voltage 5, the first amplifier 6, the horizontal scanning unit 7 from the master oscillator 8 and the output stage 9, the second piezoelectric deflector 10 with a reflector at the end, the third source 11 of the positive reference voltage, the fourth source 12 of negative supports oh voltage, the second amplifier 13, the block 14 frame scan of the element And 15, the master oscillator 16 and the summing amplifier 17, the first 18 and second 19 dichroic mirrors, the first 20, second 21, third 22 micro lenses, the first 23, second 24, third 25 photodetectors, first 26, second 27, third 28 preamplifiers. The photoelectric converter 1 is part of the transmitting television camera, which includes the first ADC 29 / video signal E _R /, the second ADC 30 / video signal E _G /, the third ADC 31 / video signal E _B /. The transmitting side includes a fourth ADC 32, a fifth ADC 33 of a sound signal, serially connected a master oscillator 34 of a sine wave and a frequency synthesizer 35, a first driver 36 codes / video signal E _R /, a second driver 37 codes / video signal E _G /, a third driver 38 codes / video signal E _B /, the first self-propelled distributor of 39 pulses, the second self-propelled distributor of 40 pulses. The transmitter 41 has three channels. The first channel includes a serially connected carrier frequency generator 42, a single-band signal generator 43 and an output amplifier 44, the second channel includes a second carrier frequency generator 45, a single-band signal generator 46 and an output amplifier 47, and a third channel includes a single-band signal generator 48 and an output amplifier 49 Each of the formers 43, 46, 48 of a single-band signal consists of a series-connected ring modulator and a band-pass filter [2, p.234]. The first carrier frequency is suppressed in the shaper 43 of the single-band signal, the lower side frequency is filtered out with a band-pass filter, the upper side frequency is amplified and radiated into the air. The first carrier frequency is suppressed in the single-band signal generator 48, the upper side frequency is filtered out, and the lower side frequency is amplified and radiated. The second carrier frequency is suppressed in the shaper 46 of the single-band signal, the lower side frequency is filtered out with a band-pass filter, the upper side frequency is amplified and radiated into the air (Fig. 18/).

ADCs 29, 30, 31 are identical (Fig. 4/), each contains a video amplifier 50, a piezoelectric deflector 51 with a reflector at the end, a source of positive reference voltage 52, a source of negative reference voltage 53, an emitter from a pulsed LED 54, a slit diaphragm 55, and a micro lens 56, a multi-element photodetector line 57 and an encoder 58. The ADCs 32, 33 are identical (Fig. 6/), each includes a voltage divider 66, a key block 67, a matching amplifier 68, an amplifier 69, a piezoelectric deflector 70 with a reflector at the end, a source of positive reference voltage, a source 72 to a negative reference voltage, the emitter of a pulsed LED 73, the slit diaphragm 74 and the microlens 75, line multielement photodetector 76, the first decoder 77, encoder 78, the second decoder 79, serially connected pulse counter 80, a third decoder 81 and the block 82 registers. All piezoelectric deflectors are structurally made the same (Fig. 5/), each includes [3, p.118] the first 59 and the second 60 piezoelectric plates, the inner electrode 61, the first 62 and the second 63 outer electrodes, one end of the piezoelectric plates is fixed in the holder 64, on the free end a light reflector 65 is fixed. The first 36 and second 37 code generators are identical, each includes / Fig. 7/ trigger switch 83 and switching unit 84 and four channels connected in series. The first and second channels are identical. The first includes series-connected the first block of 85 AND elements, the first 86 and second 87 OR elements and the first output switch 88, and the first self-propelled pulse distributor 89, the second channel includes the second block 90 of AND elements, the third 91 and fourth 92 OR elements and the second output key 93, and a second self-propelled pulse distributor 94. The third channel includes a third block of 95 AND elements and a fifth OR element 96, and a third self-propelled pulse distributor 97, the fourth channel includes a fourth block 98 of And elements and a sixth OR 99 element, and a fourth self-propelled pulse distributor 100. The code generator includes the first 101 and second 102 keys, a pulse counter 103 and a decoder 104. The information inputs are: the first are the inputs of the switching unit, the second are the inputs of the blocks 95, 98 of AND elements, the third and fourth are the third inputs of the second and fourth elements of OR 87, 92 connected to the outputs of blocks 39, 40. The output is the combined outputs of the output keys 88 and 93. The control inputs are: the first is the input of the trigger 83, the second is the combined inputs of the keys 101, 102 and the counter 103 pulses, the third are the signal inputs of the output keys 88 and 93, fourth - the control input of the counter 103 pulses. In the first code generator 36, the decoder 104 has a third output, which is the second output of the code generator 36, connected to the input of the self-propelled pulse distributor 39. The third code generator 38 (Fig. 8/) includes a flip-flop trigger 105 and a switching unit 106 and two channels, the first includes an AND element block 107, a first 108, a second 109 OR element, and an output switch 110, and a self-propelled pulse distributor 111, the second channel includes block 112 of AND elements, third 113, fourth 114 OR elements, output switch 115 and self-propelled pulse distributor 116. The first information input is the input of the switching unit 106, the second and third information inputs are the second inputs of the OR elements 109, 114. The output is the combined outputs of the output keys 110, 115. The control inputs are: the first is the input of the trigger 105, the second is the combined inputs of the self-propelled valves 111 , 116 pulses, the third - signal inputs of output keys 110, 115.

The summing amplifier 17 / Fig. 9/ contains a pulse counter 117, a decoder 118, a first 119, a second 120, a third 121, a fourth 122 pulse shapers and an output amplifier 123. The inputs are: the first is the first input of the output amplifier 123, the second is the counter input of the counter 117 pulses, the output is the output of the amplifier 123, the control input is the control input of the counter 117 pulses U ₀ .

The receiving side / digital television receiver / contains / figure 10/ antenna, the unit 124 of the touch control, the first, second and third paths for receiving and processing codes of video signals, two sound channels and a channel for generating control signals. The first path for the reception and processing of codes of video signals receives and processes the codes of video signal E _R , contains a series-connected block 125 for receiving a radio signal, an amplifier 126 of a radio frequency and a bipolar amplitude detector 127 and a channel for processing video codes E _R , including a first 128, a second 129 pulse shaper, the first 130 and second 131 registers the video signal E _R, the code processing unit 132 and the accumulator 133 codes. The second path for the reception and processing of codes of video signals receives and processes the codes of video signal E _G , comprises a radio signal reception unit 134, a radio frequency amplifier 135 and a bipolar amplitude detector 136, and a channel for processing video signals E _G , including the first 137, the second 138 pulse shapers, the first 139 , the second 140 video signal registers E _G , the processing unit 141 codes and the drive 142 codes. The third path for receiving and processing produces the reception and code processing codes video signals the video signal E _B comprises a unit 143 radio reception amplifier 144 RF, bipolar amplitude detector 145, and code channel for processing a video signal _EV which includes the first 146, second 147 pulse shapers, the first 148 , the second 149 registers of the video signal E _In , the block 150 code processing and drive 151 codes. The receiving side includes the first 152, second 153, third 154 pulse amplifier units, each of which contains 2100 pulse amplifiers / by the number of LEDs of the same color /, radiation modulation unit 155, frequency divider 156/2: 1 /, horizontal scanning unit 157, identical to the horizontal scanning unit 7 on the transmitting side, the first amplifier 158 and the first piezoelectric deflector 159 with an end reflector, the first positive reference voltage source 160, the second negative reference voltage source 161, the second amplifier 162 and the second piezoelectric deflector 163 sec reflector at the end, the third source of positive reference voltage 164, the fourth source of negative reference voltage 165, a projection optical system 166, which is a mirror-lens system [4, p. 370], including a spherical mirror arranged in series, a flat mirror with an inclination of 45 ° relative to the optical axis of the spherical mirror and corrective lens. A flat mirror allows you to reduce the distance in a straight line [5, p.188] to the matte screen 167. The sound channels are identical, each includes a first key 168 and a first block of sound registers connected in series, a second key 169 and a second block of sound registers 171 connected in series DAC 172, low-pass filter 173, power amplifier 174 and loudspeaker 175. The control signal generating channel includes serially connected horizontal sync pulses allocation blocks (SSI), a frequency synthesizer 177, a key 178, a counter 179 and pulses and a decoder 180, block 181 allocation of frame clock / CSI / and a frequency doubler 182 frame clock. Blocks 132, 141, 150 of the code processing / FIG. 13/ are identical, each includes trigger 183, first 184, second 185, third 186, fourth 187 registers, first 188, second 189, third 190 delay element blocks, fifth 191 and sixth 192 registers, adder 193 and 16 diodes. Block 188 delays the codes by 10 ns, block 189 by 276 ns, block 190 by 109 ns / 133-24 /. Registers 191, 192 receive, store 266 ns and issue codes in parallel. The first, second information inputs are the inputs of blocks 188, 189. The output is the bitwise combined outputs of block 190 and registers 191, 192. The control input is the trigger input 183 and the control input of the adder 193. The drives 133, 142, 151 of the codes are identical / Fig. 14/ each includes three hundred blocks 194 ₁ -194 ₃₀₀ . The inputs of the codes store are 1-7 inputs of blocks 194 registers, the outputs are 1-7 outputs of blocks 194 _1-300 registers. The first control input is the first control input of block 194 ₁ , the second is the combined third control inputs of blocks 194 _1-300 . Blocks 194 _{1-300 are} identical (Fig. 15, 16), each contains the first 195, second 196, third 197, fourth 198 keys, first 199, second 200, third 201, fourth 202 pulse distributors, the first seven registers 203 _1-7 1000 bits each, the first counter 204 pulses, the first decoder 205, the second seven registers 206 _1-7 each 1000 bits, the second counter 207 pulses and the second decoder 208.

The radiation modulation unit 155 (Fig. 12/) is made up of three hundred channels, each channel includes an emitter 209/209 ₁ -209 ₃₀₀ / of three primary colors, a micro lens 210/210 ₁ -210 ₃₀₀ /, a focusing cone of the optical fiber / focon / 211/211 ₁ -211 ₃₀₀ / [6, p.77]. The inputs of block 15 are the inputs of emitters 209 _1-300 connected to the corresponding outputs of the blocks of pulse amplifiers 152, 153, 154, the outputs are the radiation of three hundred output windows of the focusing cones of the optical fibers 211 _1-300 . Lenses 210 _1-300 collect radiation from the LEDs of their emitter 209 and enter them into the input windows of the foci 211 corresponding to the conditions for inputting radiation. The output windows 1-300 of the focusing cones of the optical fibers 211 _1-300 correspond to obtaining 163 color spots on the piezoelectric reflector, each with a diameter of 0.02 mm, the length of the reflector 12 mm / 0.02 mm × 600 /.

The emitting plane of the emitter 209 is located in the rear focal plane of the lens 210, in the front focal plane of which there is an input window of the focusing cone of the optical fiber 211. The radiating sides of the emitters 209 through the lenses 210, foci 211, reflectors of the piezoelectric deflectors 163, 159 and the projection optical system 166 are optically connected to the matte the screen 167. The block 176 allocation of horizontal sync pulses and the block 181 selection of frame sync pulses are identical, each includes / Fig.17/ first 212, second 213, third 214 pulse counters, first 2 15, second 216 elements AND, first 217, second 218, third 219 elements NOT and a diode. The inputs of the block are the counting inputs of the pulse counters, the output is the output of the second element And 216.

The clock frequency in the system is:

where: 600 × 25 Hz = 15 kHz line frequency,

- число пар кодируемых отсчетов в строке,

- the number of pairs of encoded samples in a row,

8 _times - the number of bits in the code.

, чтобы четные строки четного поля кадра /с 600 по 2 строки/ пошли точно между нечетными строками первого поля кадра, начинается развертка четного поля /второго/ кадра, при котором с третьего выхода дешифратора 299 импульсов с 301 по 599 /строки с 600-й по 4/ поступают в формирователь 121 импульсов, выдающий 299 импульсов положительной полярности и полной амплитуды U, а в момент 2-й строки с четвертого выхода дешифратора 118 следует один /600-й/ импульс в формирователь 122 импульсов, который выдает один импульс положительной полярности, но половиной амплитуды

. Затем следует обнуление счетчика 117 импульсов, и процесс повторяется. Объектив 2 создает цветное изображение в фокальной плоскости, в которой расположен отражатель пьезодефлектора 3. Отраженный от пьезодефлектора 10 смешанный цветной луч направляется: красного цвета отражается от первого дихроичного зеркала 18, объектив 20 собирает излучение красного цвета в фотоприемник 23, синего цвета проходит первое дихроичное зеркало 18, отражается от второго 19 и объективом 22 собирается в фотоприемник 25, зеленого цвета проходит сквозь оба зеркала 18, 19, и объектив 21 собирает в фотоприемник 24. С фотоприемника аналоговые видеосигналы поступают в соответствующие предварительные усилители 26, 27, 28. АЦП 29, 30, 31 имеют один принцип преобразования, заключающийся в развертке луча /фиг.4/ от светодиода 54 отражателем пьезодефлектора 51 по плоскости входных зрачков фотоприемников линейки 57 многоэлементного фотоприемника, в которой световой импульс преобразуется в электрический сигнал, возбуждающий соответствующую входную шину шифратора 58, который и выдает 8-разрядный код мгновенного значения входного сигнала. Преобразование выполняется с дискретизацией 3,75 МГц. Импульсы дискретизации поступают на вход светодиода 54 с синтезатора 35 частот. Источником излучения принят светодиод АЛ402А с временем срабатывания 25 нс, с запасом, удовлетворяющим дискретизации 3,75 МГц /266 нс/. Линейка 57 содержит 255 фотоприемников для кодирования видеосигнала 8-разрядным кодом. Фотоприемниками являются лавинные фотодиоды ЛФД с временем срабатывания 10 нс. Шифратор представляется микросхемой К155ИВ1 с временем срабатывания 20 нс [7, с.231]. Время преобразования 30 нс /10 нс + 20 нс/, 33· 10⁶ преоб/с. Скорость создания информации в АПЦ: 3,75 МГц· 8_раз=390 Мбит/с. Шифратор 58 формирует коды с 00000001 по 11111111.The photoelectric converter 1 generates three analog video signals of the three main packages R, G, B, which are fed to the inputs of the ADC 29, 30, 31. The photoelectric converter 1 and three ADCs are placed in the transmitting chamber, the output of which are three binary codes of the video signals Е _R , Е _G , E. _In . The ADC converts analog video signals into 8-bit codes, ^2-8 . The code generators 36, 37, 38 convert the parallel codes into sequential ones and replace the representation of units from pulses in them with positive lines in odd samples and negative lines in even samples of a half-sine wave of a single frequency of 30 MHz from a 35 frequency synthesizer. The master oscillator 34 generates sinusoidal oscillations with a stability of 10 ^-7 . A frequency synthesizer 35 generates from the frequency of the master oscillator 34 frequencies and issues: from the first output, 3.75 MHz pulses for the clock inputs of the ADC 29, 30, 31 and the first control inputs of the drivers 36, 37, 38 codes, from the second output 1.875 MHz pulses for the second the control inputs of the shapers 36, 37, 38 codes and the first control ADCs 32, 33, the third - pulses of 45 kHz for the second control inputs of the ADC 32, 33, the fourth - sinusoidal oscillations of 30 MHz for the third control inputs of the shapers 36, 37, 38 codes , from the fifth - 15 kHz pulses for the first input of block 14 scan, for the third control inputs of the ADC 32, 33 and the fourth control inputs of the drivers 36 and 37 codes, from the sixth - 25 Hz pulses for the second input of block 14 and the self-propelled distributor of 40 pulses, from the seventh - 7.5 kHz pulses for block 7 lowercase sweep, from the eighth - sinusoidal oscillations of 3.75 MHz for generators 42 and 45 carrier frequencies. The ADCs 32, 33 convert two audio signals into 16-bit binary codes, 2 ¹⁶ , which are fed to the second information inputs of the code generators 36 and 37. A self-propelled distributor of 39 pulses with the arrival of a start signal U _P from the second output of the code generator 36 produces an eight-unit code 11111111, which is the horizontal sync pulse code / 499 counts in each line /, to the third information inputs of the shapers 36, 37 codes and to the second information input of the third shaper 38 codes. Camohodny distributor 40 pulse arrival signal U _U start 25 Hz from the sixth output synthesizer 35 frequency outputs code 11111111, which is the code frame pulse CSI / 500th count in the last block row /, to the fourth information inputs of the formers 36, 37 and the third information input shaper 38 codes. Shapers 43, 46, 48 of single-band signals each contain a series-connected ring modulator and a band-pass filter that filters out one of the side frequencies in the spectrum of the amplitude-modulated signal. Shaper 43 single-band signal outputs to the input of the output amplifier 44 the upper side frequency of 480 MHz from the first carrier 450 MHz, shaper 46 outputs to the input of the output amplifier 47 the upper side frequency of 570 MHz from the second carrier 540 MHz, the shaper 48 of the single-band signal outputs to the input of the output amplifier 49 the lower side frequency of 420 MHz from the first carrier 450 MHz. Block 7 gives the control voltage of a triangular isosceles shape (Fig. 2/) to the amplifier 6 and puts the piezoelectric deflector 3 into oscillatory motion with a frequency of 7.5 kHz, line scanning is with a frequency of 15 kHz. The signal from the amplifier 6 is supplied to the internal electrode 61 / Fig. 5/, the voltage from the source 4 is applied to the external electrode 62, and the voltage of the negative reference voltage source 5 is applied to the external electrode 63. When a control voltage is applied to the internal electrode 61, the piezoelectric plates are deformed [3, p.122]: one lengthens, the other shortens, the end face with the light reflector 65 rotates and deflects the vertical image strip, the line scan is carried out on the reflector of the piezoelectric deflector 10. The piezoelectric deflector 10 performs a scan vertical images by performing a vertical scan. The piezoelectric deflector 10 is oscillating at a frequency of 25 Hz, 50 fields per second. The width of the reflector of the piezoelectric deflector 3 is 0.01 mm, its length is not less than 6 mm / 0.01 mm × 600 /. The width of the reflector of the piezoelectric deflector 10 is also 0.01 mm, the length is at least 5 mm / 0.01 mm × 500 counts /. Both line and frame sweeps are without reverse moves / Fig. 2/. The output of the summing amplifier 17 gives a linearly varying step voltage, amplified by the amplifier 13. In the first / odd / field of the frame, the reflector of the piezoelectric deflector 10 deflects the image down, in the second / even / field of the frame, the scan goes up. The summing amplifier 17 sums the triangular voltage from the master oscillator 16 with 15 kHz pulses, which gives a linear step voltage for the amplifier 13. Each pulse of the line moves the line at the end of its stroke a step in the width of one line at the time of the ray entry beyond the frame edge with one and the other side. It turns out two fields of 300 lines, a total of 600 active lines of 500 samples in each. The purpose of the shapers 119, 120, 121, 122 pulses (Fig. 9) is to feed negative and positive pulses of the corresponding amplitude and duration to the second input of the output amplifier 123 at the right time. The signal U ₀ 25 Hz from the And 15 element resets the counter 117 pulses, the counter is 10-bit, counts pulses 15 kHz, the cycle counts 600 pulses / lines in the frame /. When scanning an odd field of the frame from the first output of the decoder 118, pulses 1 through 299 / odd lines 1 through 597 / are output, which are supplied to the shaper 119, which gives 299 pulses of negative polarity and full amplitude U to the second input of the amplifier 123 in a row, and in the moment 599 of the line from the second output of the decoder 118 leaves one 300th pulse to the input of the pulse shaper 120, which gives one pulse of negative polarity but half amplitude

so that even lines of the even field of the frame / from 600 to 2 lines / go exactly between the odd lines of the first field of the frame, the even field / second / frame scan starts, in which from the third output of the decoder 299 pulses from 301 to 599 / lines from the 600th by 4 / enter the pulse generator 121, issuing 299 pulses of positive polarity and full amplitude U, and at the moment of the 2nd line from the fourth output of the decoder 118, one / 600th / pulse is transmitted to the pulse shaper 122, which gives one pulse of positive polarity but half amplitude

. Then follows the zeroing of the counter 117 pulses, and the process repeats. The lens 2 creates a color image in the focal plane in which the reflector of the piezoelectric deflector 3 is located. The mixed color beam reflected from the piezoelectric deflector 10 is directed: red is reflected from the first dichroic mirror 18, the lens 20 collects red radiation into the photodetector 23, the first dichroic mirror passes in blue. 18 is reflected from the second 19 and the lens 22 is collected in the photodetector 25, the green color passes through both mirrors 18, 19, and the lens 21 collects in the photodetector 24. From the photodetector, the analog form the signals are fed to the corresponding preamplifiers 26, 27, 28. The ADCs 29, 30, 31 have one conversion principle, which consists in scanning the beam (Fig. 4/) from the LED 54 by the piezoelectric reflector 51 along the plane of the entrance pupils of the photodetector line 57 of the multi-element photodetector, in which the light pulse is converted into an electrical signal that excites the corresponding input bus of the encoder 58, which produces an 8-bit code of the instantaneous value of the input signal. The conversion is performed with a sampling of 3.75 MHz. The sampling pulses are fed to the input of the LED 54 from the synthesizer 35 frequencies. The source of radiation is an AL402A LED with a response time of 25 ns, with a margin satisfying a sampling rate of 3.75 MHz / 266 ns /. Line 57 contains 255 photodetectors for encoding a video signal with an 8-bit code. Photodetectors are avalanche photodiodes of the APD with a response time of 10 ns. The encoder is represented by the K155IV1 chip with a response time of 20 ns [7, p.231]. Conversion time 30 ns / 10 ns + 20 ns /, 33 · 10 ⁶ prev / s. APC information creation speed: 3.75 MHz · 8 _times = 390 Mbit / s. The encoder 58 generates codes from 00000001 to 11111111.

The first photodetector of line 57 corresponds to the code 00000001, the second to the code 00000010, the third to 00000011, etc., the 255th code 11111111. The ADCs 32, 33 convert two sound signals _Ezv1 , _Ezv2 into 16-bit codes. During one line, three codes are each formed, sampling 45 kHz / 15 kHz × 3 /. To obtain codes 16-bit changes the gear ratio of the voltage divider 66/6 /. Divider 66 seven-step resistive. Block 67 has seven keys for connecting the corresponding stage of the divider to the matching amplifier 68. The line 76 of the multi-element photodetector contains 1024 photodetectors, which provides the conversion of the sound signal with a ruler into a 10-bit code 2 ¹⁰ . The resolution is 10 μV, the coding range of the 76 line is 0-0.01024 V. Converting signals exceeding 2 ¹⁰ into the code is performed by the first decoder 77, the encoder 78, the second decoder 79 and the key block 67. Using them, the coding range is 0- 0.65536 V, i.e. 2 ¹⁶ . If there is no signal at the input of the divider 66, the code from one zeros comes to the input of the second decoder 79, the signal from the first output of the decoder 79 holds the first key open, determining the transmission coefficient 1.0 of the divider 66. When the sound signal reaches a value of 2 ¹⁰ , a signal appears at the second output of the decoder 79, which closes the first key in block 67 and opens the second key, the transfer coefficient becomes 0.5. With code 2 ^{11, the} coefficient is 0.25, with code 2 ¹² - 0.125, code 2 ¹³ - 0.0625, with code 2 ¹⁴ - 0.03125, with code 2 ¹⁵ - 0.015625, which remains until code 2 ¹⁶ . With a decrease in the amplitude of the input signal, the reverse process occurs with increasing transmission coefficient. Units in codes are represented by the presence of an impulse, zeros by their absence. Over the course of one line, the encoder 78 issues three codes entering the block 82 of registers, which contains three registers of 16 bits. In the process of receipt, the codes are shifted from register to register by signals U _LED shift. In block 82, three codes are accumulated, which at the end of the line at the moments of discrete pulses of line 247, 248, 249/3 / are issued to the second information inputs of the code generators 36, 37. The U _OUT signals come from outputs 1-3 of the decoder 81. The 8-bit counter 80 counts 1.875 MHz, the counting cycle is 250 pulses. With the arrival in the counter 80 247, 248, 249th pulses, the decoder 81 gives three consecutive signals U _OUT . The counter 80 pulses is reset to the leading edge of the pulse U _{about the} frequency of the lines. The first code generator 36 and the second code generator 37 are identical (Fig. 7/). The code generator 36 provides video signal codes E _R , the units of which in odd samples are represented by positive half-sine waves of a single frequency of 30 MHz, and in even samples are represented by negative half-sines of the same frequency 30 MHz. Shaper 37 codes gives the codes of the video signal E _G. In the 36/37 / code generator from ADC encoder 58, the codes in parallel with a frequency of 3.75 MHz are fed to the inputs of the switching unit 84, which branches the 3.75 MHz code stream into two at 1.875 MHz. Block 84 includes four K176KT1 microcircuits, which are four-channel switches with a response time of 25 ns [8, p. 222]. The outputs of the first two microcircuits are connected to the first inputs of the elements And block 85 of the first channel, the outputs of the other two microcircuits are connected to the first inputs of the elements And block 90 of the second channel. Alternate connection of the channels to the outputs of block 84 is performed by trigger 83, to the input of which pulses of 3.75 MHz are received. The second inputs of the elements And blocks 85, 90 receive sequentially pulses from self-propelled distributors 89, 94 pulses having eight discharges. Starting pulses U _P for them are pulses of 1.875 MHz. From the outputs of the elements AND blocks 85, 90, the pulses of the codes sequentially through the elements OR 86, 87 in the first channel and 91, 92 in the second channel open 33 ns / 10 ⁹ : 30 · 10 ⁶ / output keys 88, 93 for the duration of their duration. the signal inputs of the output keys 88, 93 receive a sinusoidal oscillation of a monofrequency of 30 MHz. The first output switch 88 in the open state passes the positive half-sine wave, the second output key 93 in the open state passes the negative half-sine wave. At the output of the shaper 36/37 / units in the codes of odd samples of the line are represented by positive half-sine waves, in the codes of even samples of the line by negative half-sines. The output signal from the generator 36/37 / codes is a full and incomplete sinusoid with a frequency of 30 MHz, which modulate the corresponding carrier frequency in block 43/48 /. The video signal codes E _R / E _G / represent from 1 to 490 line samples. In the 493-498 samples, there are three codes of the sound signal that come from the ADC 32/33 / to the first inputs of the I 95, 98 elements. The samples 491/492 go to switch the keys 101, 102. In the 499 sample, the horizontal sync pulse code / CCI / , which comes from block 39 to the third input of the second element OR 87, in the 500th sample of the 600th line there is a frame clock / KSI / coming from block 40 to the third input of the fourth element OR 92. The keys 101, 102 perform the separation of the video signal codes and sound codes.

The key 101 is opened by the signal from the first output of the decoder 104 at the time of resetting the pulse counter 103 and remains open until 246 sampling pulses / up to 491 counts / figure 3. At a 246 sampling pulse, the signal from the second output of the decoder 104 closes the first key 101 and opens the second key 102. Three sound codes are received at the second inputs of the OR elements 87, 92, which at the moments 247, 248, 249 of the sampling pulses pass to the output keys 88, 93 At the moment 249 pulses from the third output of the decoder 104, the signal U _{П is} fed to the input of the first self-propelled pulse distributor 39, which gives the SSI code 11111111 to the third input of the second OR element 87/499 line count /. At the moment of 250 sampling pulses at the last line of the frame / 600th line / second self-propelled distributor of 40 pulses gives the CSI code 11111111, which goes to the third input of the fourth element OR 92 and is the 500th sample of the line. In the second shaper 37, the decoder 104 does not have a third output, and the shaper 37 of the codes does not have a second output, as the shaper 36. The third shaper 38 of the codes works similarly to the first, its operation is simpler, it generates the codes of the video signal Е _В , the SSI code and the CSI code, but does not generate sound codes.

The oscillator 42 and 45 of the first and second carrier frequencies are frequency multipliers, sine waves of 3.75 MHz are supplied to their inputs. In the generator 42, the 3.75 MHz frequency is multiplied by 120 times, the first carrier frequency is 450 MHz. In the generator 45, the 3.75 MHz frequency is multiplied by 144 times, the second carrier frequency is 540 MHz. Spectra of amplitude-modulated signals in Fig. 18. In the first channel of the transmitter, the information of the video signal codes E _R is transmitted by the upper side frequency of 480 MHz from the first carrier, the occupied band on the air is ± 48 Hz or 96 Hz. In the second channel, the information of the video signal codes Е _В is transmitted by the upper side frequency of 570 MHz from the second carrier, the occupied band on the air ± 57 Hz or 114 Hz, in the third channel, the information of the codes of the video signal Е _{G is} transmitted by the lower side frequency of 420 MHz from the first carrier frequency, the occupied band ± 42 Hz or 84 Hz. The total occupied band is 294 Hz.

Three radio signals are fed into the antenna of the receiving side / 10 /. The radio signals are received by the blocks 125, 134, 143 receiving the radio signal. The blocks are decimetric channel selectors / ACS / with electronic tuning and receive radio signals in the range 420-790 MHz. Each block represents the first half of SKD-24 [9, p.132] and includes an input circuit, a radio frequency amplifier, and a mixer is used from the frequency converter [9, Fig. 4.2]. The band-pass filter of the radio frequency amplifier in each range is tuned by applying bias voltage to the varicaps from the electronic switch of the touch control unit 124, which is a program selection unit. The amplified radio frequency signal through the communication loop [9, p.132] is fed to the mixer emitter, here also / to the mixer emitter / from the synthesizer 177 frequencies the frequency corresponding to the carrier frequency and necessary for the detection of a single-band signal [10, p.146], circuit a local oscillator and an intermediate-frequency filter, available in SKD-24 [9, Fig. 4.2] are not needed. The signal from the mixer manifold, which is the output signal of block 125/134, 143 /, enters the radio frequency amplifier 126/135, 144 /, where it is amplified to the required value and fed to the input of the bipolar amplitude detector 127/136, 145 /. The second inputs of the synthesizer 177 frequencies are connected to the second group of outputs of block 124. When you turn on the desired program guide, the signal from the corresponding diode in block 124 determines the output of two carrier frequencies from the fifth and sixth outputs of the synthesizer 177 frequencies to the third inputs of blocks 125, 134, and 143. Bipolar amplitude the detectors 127, 136, 145 are made according to the circuit diagram in Fig.11. Diode D1 selects the positive envelope of the modulating sinusoidal signal. The diode D2 from the modulating one selects the envelopes of the positive half sine / units of odd samples /, the diode D3 from the modulating one selects the envelopes of the negative half sine / units of even samples /. From the first output of the detector, the projected half-sine waves / 30 MHz / enter the input of the first shaper 128/137, 146 / pulses, from the second output, the detected negative half-sine waves go to the input of the second shaper 129/138, 147 / pulses. The pulse shapers are made according to the scheme of an asymmetric trigger with emitter coupling [11, p.209], which forms rectangular pulses from harmonically changing signals. The pulses from the formers have one polarity and a duration equal to the pulse duration in the codes on the transmitting side. After turning on the power, the keys of the receiving side are in the closed state. The order of operation of the receiving side is determined by the control signals generated by the channel for generating control signals. The decisive role belongs to block 176 for selecting horizontal sync pulses / SSI /, the condition for which is the simultaneous arrival from three formers 128, 137, 146 pulses of codes 11111111 to the inputs of block 176. At least one code will always be present in all codes of the line, except for the 499th zero, especially at the same time in the codes of three lines. For each zero in the code, the elements NOT / Fig.17/ will reset the counters 212, 213, 214 pulses. With the arrival of three SSI codes, block 176 provides an output pulse, which is a horizontal sync pulse. SSI opens the key 178 and enters the frequency divider 156/2: 1 /, SSI frequency 15 KHz. The same pulse is supplied to the first input of the frequency synthesizer 177 and is a frequency and phase synchronization pulse in the frequency synthesizer 177. Own frequency stability of the synthesizer 177 frequencies 10 ^-6 , tuning the frequency of the synthesizer 177 to the frequency and phase of the master oscillator 34 of the transmitting side is performed on the leading edge of the SSI from block 176. The synthesizer 177 generates 3.75 MHz of video signals from the first output, pulses from the second output 1.875 MHz, from the third - clock pulses of 30 MHz, from the fourth - signals issuing sound codes 45 kHz, from the fifth - sinusoidal oscillations of the first carrier frequency, from the sixth - sinusoidal oscillations of the second carrier frequency, from the seventh - pulses 7.5 MHz. Codes of the video signal E _R from the output of the first shaper 128 pulses are fed in serial form to the information input of the first 130 register of the video signal E _R , filling in the bits of which takes on a parallel form, the codes from the output of the shaper 129 pulses are fed to the information input of the second register 131 of the video signal E _R , filling which discharges takes a parallel form. The video signal codes E _{R are} issued from the registers 130, 131 to the block 132 at the same time with a pulse U _OUT 3.75 MHz, supplied to the first control inputs of the registers 130, 131. The video signal codes E _G and E _B go through the same process. The code processing units 132, 141, 150 double the samples in the line from 500 to 1000. The double the samples in the line by obtaining the codes of intermediate / average / samples between each passed sample and each subsequent one. In blocks 132, 141, 150, the two / previous and subsequent / codes are added and the sum code is divided into bits. From the output of blocks 132, 141, 150, codes with a frequency of 7.5 MHz should go to drives 133, 142, 151 codes, respectively. Each drive 133, 142, 151 codes for the first / odd / field of the frame fills with the codes of the samples of the odd lines the digits of three hundred registers / by the number of lines in the field of the frame /. When 300 registers are filled in, the first field of the frame is scanned on screen 167. The odd field of the frame is scanned simultaneously with 300 lines / from 1 to 599 / and is repeated 300 times during the field duration. At the same time, the code stores fill three hundred registers with the codes of samples of the second field of the frame / even /, after filling in which the second / even / field of the frame is scanned also with 300 lines / s 600 to 2 / s, 300 times repeated. These processes are repeated alternately.

The operation of the block 132/141, 150 / code processing, Fig.13. The codes of the odd samples in the registers 130 through the block 188 delay elements / 10 ns / go to the registers 184, 185. The codes of the even samples from the register 131 through the block 189 delay elements / 276 ns / go to the registers 186, 187. Each code is used twice: the first once as the previous, second time as the next, therefore, the block 132 has four registers 184, 185, 186, 187. With the arrival of the first pulse of 3.75 MHz to the input of the trigger 183, the pulse U _OUT1 from the first output of the trigger simultaneously generates a code from the register 185 0 and from the register 186 0 code and resets them. The code from register 185 goes to the first inputs of the adder 193, the code from register 186 goes through diodes to the second inputs of the adder 193 and to the inputs of the register 192, which stores the code 266 ns. 10 ns after the issuance of the code from the register 185, the bits of the registers 184, 185 are filled with the following code 1 code. Block 188 delays the codes by 10 ns to prevent overlapping of the incoming code issued from the register 185. Adder 193 performs the addition of codes; K555IM6 microcircuits are used as an adder [7, p. 258] with an addition time of 24 ns. Upon completion of the addition, the adder circuits 193 are reset to zero by a pulse of U _about 3.75 MHz; it also issues the sum code to block 190. The division of the sum code is performed simply by shifting the code by one bit so that the least significant bit of the sum code is discarded. A shift by one bit is performed by the corresponding connection of the outputs of the adder 193 to the inputs of block 190:

adder outputs 0 1 2 3 4 5 6 7 8 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ block inputs 190 1 2 3 4 5 6 7 8

Код №2 идет за кодом №1 через 133 нс, он поступает с регистра 192. Это 0 код, который был выдан с регистра 186 в регистр192 и хранится в нем 266 нс. Из регистра 192 код выдается сигналом U_ВЫД2, половина времени хранения из 266 нс приходится на время сложения кодов 24 нс плюс задержка 109 нс в блоке 190, поэтому код №2 следует за кодом №1 через 133 нс. С приходом на вход триггера 183 второго импульса импульс U_ВЫД2 со второго выхода триггера выдает из регистра 192 код №2 0 код, из регистра 184 код 1 код, который поступает в регистр 191, хранящий его 266 нс, и через диоды поступает в сумматор 193 и выдает из регистра 187 код 0 код в сумматор 193. Идет сложение 1 код + 0 код, и с выхода блока 190 следует код №3

через 133 нс за ним с регистра 191 выдается сигналом U_ВЫД1 код №4 1 код. Сразу после выдачи кода с регистра 187 регистры 186, 187 заполняются кодом 2 код. Блок 189 задерживает коды на 276 нс: 266 нс для восстановления следования четных отсчетов за нечетными и 10 нс для исключения наложения поступающего кода на выдаваемый из регистра 187. С приходом в триггер 183 третьего импульса сигнал U_ВЫД3 с первого выхода триггера выдает с регистра 186 2 код и из регистра 185 1 код, следует заполнение регистров 184, 185 кодом 3 код, сумматор 193 производит сложение 2 код + 1 код, и с блока 190 следует код №5

Через 133 нс за ним с регистра 192 следует код №6 2 код. С приходом четвертого импульса в триггер 183 сигнал U_ВЫД4 выдает в сумматор 193 из регистра 184 3 код, из регистра 187 2 код. Следует заполнение регистров 186, 187 кодом 4 код, с блока 190 на выход следует код №7

и с регистра 191 выдается код №8 3 код. С приходом пятого импульса в триггер 183 сигнал U_ВЫД5 с первого выхода триггера выдает из регистра 185 3 код, из регистра 186 4 код, сумматор 193 выполняет сложение 4 код + 3 код, с блока 190 на выход следует код №9

Через 133 нс с регистра 192 следует на выход и код №10 4 код. Далее эти процессы повторяются. Выходы блока 190 и регистров 191, 192 объединены поразрядно /1-7 разряды/ и являются выходом блока 132 /141, 150/. Выходы 8-х разрядов /младших/ не используются, а опускаются ввиду их низкого удельного веса в коде, который составляет

значения кода, т.е. 0,39%

Это позволяет уменьшить в каждом из накопителей /133, 142, 151/ кодов на 600 регистров, в трех накопителях 1800 штук, и в блоке 155 модуляции излучения сократить 900 светодиодов.Bit 0 means transfer to the high bit when the sum of codes. The process of obtaining the intermediate / average / code value is illustrated in Fig.13. When doubling the samples in the line / 7.5 MHz /, the code repetition period is 133 ns. The addition process takes 24 ns; therefore, block 190 must still delay the code by 109 ns / 133-24 /. After 133 ns from block 190, code No. 1, which is

Code No. 2 follows code No. 1 after 133 ns, it arrives from register 192. This is the 0 code that was issued from register 186 to register 192 and is stored in it 266 ns. From register 192, the code is issued by signal U _EXT2 , half of the storage time of 266 ns falls on the time of adding codes 24 ns plus a delay of 109 ns in block 190, so code No. 2 follows code No. 1 after 133 ns. With the arrival of the second pulse at the input of the trigger 183, the pulse U _OUT2 from the second output of the trigger generates from the register 192 code No. 2 0 code, from the register 184 code 1 code, which enters the register 191, which stores it 266 ns, and through the diodes enters the adder 193 and generates code 0 code from register 187 into adder 193. Addition is 1 code + 0 code, and code No. 3 follows from the output of block 190

after 133 ns after it, from the register 191 is issued a signal U _EXT1 code No. 4 1 code. Immediately after issuing a code from register 187, registers 186, 187 are filled with code 2 code. Block 189 delays the codes by 276 ns: 266 ns for restoring the even-numbered and odd-numbered samples, and 10 ns to prevent the incoming code from being superimposed on the register 187. When the third pulse _arrives in trigger 183, the signal U _OUT3 from the first output of the trigger generates from the register 186 2 code and from register 185 1 code, followed by filling in registers 184, 185 with code 3 code, adder 193 adds 2 code + 1 code, and code No. 5 follows from block 190

After 133 ns, it is followed by register No. 6, code 2, from register 192. With the arrival of the fourth pulse in the trigger 183, the signal U _EXIT4 gives the adder 193 from the register 184 3 code, from the register 187 2 code. It follows the filling of registers 186, 187 with code 4 code, from block 190 to output code No. 7 follows

and from register 191 issued code number 8 3 code. With the arrival of the fifth pulse in trigger 183, signal U _OUT5 from the first output of the trigger generates a code from register 185 3, code 4 from register 186, adder 193 performs addition 4 code + 3 code, code No. 9 follows from block 190 to the output

After 133 ns, register 192 is followed by output and code No. 10 4 code. Further, these processes are repeated. The outputs of block 190 and registers 191, 192 are combined bitwise / 1-7 bits / and are the output of block 132/141, 150 /. The outputs of 8 bits / low / are not used, but are omitted due to their low specific gravity in the code, which is

code values, i.e. 0.39%

This allows to reduce in each of the drives / 133, 142, 151 / codes by 600 registers, in three drives 1800 pieces, and in the block 155 radiation modulation to reduce 900 LEDs.

The operation of the drive 133/142, 151 / codes, Fig.14.

In the initial state, the keys in the code store are closed.

The process of accumulation of codes begins with the first odd field of the frame. After filling in the codes of three hundred lines of the first field of the frame of three hundred registers of blocks 194 _1-300, it is necessary to issue these codes in parallel to 300 lines in the corresponding block of pulse amplifiers, the first field of the frame is scanned on screen 167 / simultaneously with all lines from 1 to 300 fields /. In parallel with the issuance of codes from the drive _133/142 , 151 / there is an accumulation in the registers of blocks 194 _1-300 codes of three hundred lines of the second / even / field of the frame. Each drive 133, 142, 151 codes contains / Fig.14/ three hundred blocks 194 registers, each line has its own block 194. The process of accumulating codes begins block 194 _{1 /} Fig.15/. The first key 195 / input 1 / is opened by a 50 Hz pulse from block 182. The public key 195 passes 7.5 kHz pulses from a synthesizer 177 frequencies (output 7) to the input of the pulse distributor 199, which generates U _T clock pulses from 1000 outputs. Seven paired registers 203 and seven second registers 206 in block 194 contain 1000 bits each. For odd fields of a frame, codes 203 _1-7 are filled with codes; for even fields of a frame, registers 206 _1-7 are filled with row codes. The first bits of codes are entered into the registers 203 ₁ and 206 ₁ , the second bits of the codes are entered into the registers 203 ₂ , 206 ₂ ... the seventh bits of the row codes are entered into the registers 203 ₇ , 206 ₇ . The number of bits in each register is 1000, according to the number of samples in a row. In total, 2.1 Mbps / 1000 × 7 × 300 / is entered into the drive 133/142, 151 / - the amount of digital information of one field of the frame, and 4.2 Mbps in the frame. The first pulse U _T from the first output of block 199 is supplied in parallel to the first / clock / inputs of the first bits of the seven registers 203 _1-7 , according to which the signals 1-7 bits of the code of the first count of the first line are entered in bits No. 1 of the registers 203 _1-7 . The second U _T from the second output of the distributor 199 stores the signals of 1-7 bits of the code of the second count of the first line in the bits No. 2 of the registers 203 _1-7 , etc. The 1000th U _T from the distributor 199 enters the signals of 1-7 bits of the code of the 1000th count of the first line into the bits No. 1000 of the registers 203 _1-7 . The signal from the 1000th output of the distributor 199 closes the key 195 in its block 194 ₁ and opens / the output 1 of the block 194 ₁ / key 195 in the second block 194 ₂ , in which the second row count codes are entered in its registers 203 _1-7 . The signal from the 1000th output of the pulse distributor 199 closes the key 195 in block 194 ₂ and / the output 1 of block 194 ₂ / opens the key 195 in the third block 194 ₃ , the same process of filling the registers in block 194 ₃ is going _on . Similarly, the codes of samples from the next 4-300 lines are filled with registers 203 in the remaining blocks 194 _4-300 . Upon filling out the registers 203 in block 194 _{300, the} signal from the 1000th output from its pulse distributor 199 closes its key 195 and opens / output 1 of Fig. 14 / second key 196 and third 197 in block 194 of ₁ registers / Fig. 15/ and only the second key 196 in blocks 194 _2-300 / _Fig.16 /. The pulses of 7.5 MHz are fed to the second 200 pulse distributors, which give the U _OUT signals to the second inputs of the bits of the registers 203 _1-7 and simultaneously give three hundred codes from the registers 203 _{1-7 of} all blocks 194 _1-300 to the inputs of the blocks 152, 153 , 154 pulse amplifiers, from the outputs of which the power supply signals of the LEDs are fed to 300 emitters in block 155. The output of the codes of the samples of the lines of the first field of the frame for the field duration is repeated 300 times. At the same time, the codes of the samples of 300 lines of the second / even / frame field are entered into the registers 206 _{1-7 of} blocks 194 _1-300 .

The order of entry is the same as the first field. After filling in the registers 206 _{1-7 with} codes 301-600 lines, the parallel issuing of codes 301-600 lines to the inputs of the pulse amplifier blocks and the scanning of the image of the second field of the frame on the screen 167. After three hundred scanning / 301-600 / lines of the second field of the frame, the process of three hundred sweep 1-300 lines of the odd field of the frame, etc. Playback on the screen 167 of the first field of the first frame is delayed by the duration of the frame field, 0.02 s, since at this time there is an accumulation of codes of the lines of the first field of the frame in the registers of block 194 ₁ . Blocks 152, 153, 154 of pulse amplifiers are represented by 533AP6 microcircuits with a response time of 18 ns [7, p.128]. Pulse amplifiers in each block for 2100 pieces / 300 × 7 /, a total of 6300 pieces. Block 155 radiation modulation / 12 / performs luminance modulation of the three colors R, G, B at the same time 300 lines, respectively, the values of the codes of the video signals. To do this, 300 emitters of 209 are used in three primary colors, each of which includes seven LEDs of red, green and blue radiation. Each emitter 209 _1-300 contains 21 LEDs. In 300 emitters of 6300 LEDs of the HL MP type of the Hewlett-Packard company [12, p. 71]. For red radiation, HL MP-AL00 LEDs with a light intensity of 0.4 cd, a wavelength of 0.59 μm and a current of 0.02 A were adopted, for green radiation, HL MP-AM00 LEDs with a light intensity of 0.8 cd, a wavelength of 0.526 were adopted μm and a current of 0.02 A, for blue radiation - HL MP-AB00 LEDs with a light intensity of 0.3 cd, a wavelength of 0.475 μm and a light intensity of 0.02 A. The brightness modulation is carried out by switching on the radiation of the LEDs according to the discharge weight according to table 2 .

table 2
Distribution of LEDs of the same color according to the discharge weights Bit number in code 1 senior rank 2 3 4 5 6 7 low order LEDs in code 1 1 1 1 1 1 1 Multiplicity of the filter - 2 ^x 4 ^x 8 ^x 16 ^x 32 ^x 64 ^x

The brightness, saturation and hue of the resulting color on the screen 167 is determined by the total energy and the mutual ratio of the three colors R, G, B in each emitter 209. The image scan on the matte screen 167 is performed by piezo-deflectors 163, 159 according to the control voltages from blocks 162, 158. So as the scan of the frame field is performed simultaneously by all the lines of the field, the classical frame scan does not take place. When the frame field is odd, the piezoelectric reflector 163 reflector from block 155 receives radiation from 300 emitters simultaneously. When scanning the next even field of the frame, to position the even lines between the odd lines of the odd field, the piezoelectric reflector 163 needs to be slightly tilted in the vertical plane. The control pulse for this comes from the frequency doubler 182 frame sync pulses. The KSI frequency doubler 182 generates pulses with a frequency of 50 Hz and a duration of 0.02 s, which are amplified by an amplifier 162, the control signal, acting on the internal electrode 61 (Fig. 5/), tilts the end of the piezoelectric deflector 163 so that lines of an even frame unfold between the lines odd field of the frame / Fig.2/. The width of the reflector of the piezoelectric deflector 163 corresponds to the diameter of the beam / not less than / coming from the output of the focusing cone of the optical fiber 211, which is 0.02 mm. The length of the reflector corresponds to the number of lines in the frame and is 12 mm / 0.02 mm × 600 /. The piezoelectric deflector 159 performs a horizontal scan of the rays according to the control voltage from the amplifier 158. The horizontal scan voltage has a triangular isosceles shape with a frequency of 7.5 kHz and is set by the horizontal scan block 157, identical to block 7 on the transmitting side. The amplifier 158 amplifies the control voltage and drives the piezoelectric deflector 159 in an oscillatory motion with a frequency of 7.5 kHz, which corresponds to a line frequency of 15 kHz. The width of the reflector of the piezoelectric deflector 159 is taken to be 0.03 mm, the length of the reflector at 600 lines in the frame corresponds to 18 mm / 0.03 mm × 600 /. The image of the fields is projected by the projection optical system 166 onto the matte screen 167, the dimensions of which correspond to the magnification factor of the system 166. With a 20x magnification of the image, the screen 167 is:

horizontal 20 × / 1000 _count × 0.03 mm / = 600 mm,

vertical 20 × / 600 _lines × 0.03 mm / = 360 mm,

diagonally 700 mm.

The total luminous intensity of one emitter 209, taking into account that all the LEDs have a light intensity of 0.3 cd blue LEDs, is:

where: 3 - the number of colors in the emitter,

0.3 cd - light intensity of the blue LED,

- коэффициенты двоичного кода с второго по 7 разряды. Потеря силы излучения от излучателя 209 до отражателя пьезодефлектора 163 принимается в 8 раз. Потери силы излучения от отражателя пьезодефлектора 163 до отражателя пьезодефлектора 159 принимаются в 2 раза. Потери силы излучения при проекции зеркально-линзовой оптической системой принимаются в 10 раз [4, с.370]. При потерях силы излучения от излучателя до экрана 167 в 20 раз /8+2+10/ максимальная яркость развертывающего светового элемента от одного излучателя 209 на экране 167 составляет:

- the coefficients of the binary code from the second to 7 digits. The loss of radiation from the emitter 209 to the reflector of the piezoelectric deflector 163 is taken 8 times. Losses of radiation from the reflector of the piezoelectric deflector 163 to the reflector of the piezoelectric deflector 159 are taken in 2 times. Losses of radiation power during projection by a mirror-lens optical system are accepted 10 times [4, p.370]. If the radiation intensity from the emitter to the screen 167 is lost 20 times / 8 + 2 + 10 /, the maximum brightness of the developing light element from one emitter 209 on the screen 167 is:

where: 1.79 cd - the light intensity of one emitter 209,

20 - the frequency loss of radiation from the emitter 209 to the screen 167,

0.36 · 10 ^-6 m ² - the area of the resolution element on the screen from one emitter, 0.6 × 0.6 mm ² .

The average brightness on the matte screen 167 when scanning the field of the frame with 300 lines and repeating the sweep for a field duration of 300 times is 90,000 times higher than in the prototype / 300 × 300 /. The key 178 is opened by the SSI pulse from block 176 and passes 1.875 MHz pulses into the counter 179, the counting cycle is 250 pulses. With the arrival of 245 pulses, the decoder 180, with a signal from the first output, opens keys 168, 169 in the sound channels. Three sound codes at moments 247, 248, 249 pulses pass into blocks 170, 171 of sound registers, from which signals U _VY 45 kHz are output to DAC 172. With the arrival of counter 249 pulses 249 pulses, the signal from the second output of decoder 180 closes the keys 168, 169, zeroes the counter 179 and closes the key 178. DAC 172 converts the codes into analog sound signals, which are amplified in blocks 174 and reproduced by loudspeakers 175. The LEDs of 300 emitters can consume a maximum of: 6300 _pieces × / 3 V × 0.02 A / = 378 VA.

System operation.

From the photodetectors 26, 27, 28, three analog video signals after amplification by the preamplifiers are fed to the ADC 29, 30, 31. Two audio signals are fed to the ADC inputs 32, 33. The video signals are converted by the ADC into 8-bit codes with a sampling rate of 3.75 MHz, sound signals are converted to 16-bit codes with a sampling rate of 45 kHz. Shapers 36, 37, 38 codes form sequential codes from parallel codes and slow down the presentation of units from pulses to positive and negative half-sinusoids of the 30 MHz monofrequency. The clock frequency in the system is 30 MHz. The data transfer rate is 180 Mbps. On the transmitting side, 600 lines of 500 samples in each are encoded, the line scan is interlaced. The information of the video signal codes E _R is transmitted by the upper side frequency of 480 MHz from the first carrier / 450 MHz /, the information of the codes of the video signal E _G is transmitted by the lower side frequency of 420 MHz from the first carrier. The information of the video signal codes E _B is transmitted by the upper side frequency of 570 MHz from the second carrier / 540 MHz /. The occupied band on the air in three channels is 294 Hz. The receiving side receives three radio signals in parallel, performs radio frequency amplification, bipolar amplitude detection, selects horizontal and frame sync pulses, restores two carrier frequencies, doubles the number of samples in each line / 1000 lines /. The radiation modulation unit 155 performs luminance modulation of 300 lines simultaneously. The piezoelectric deflector 163 arranges 300 even lines of the second field of the frame between 300 odd lines of the first field of the frame. The piezoelectric deflector 159 performs a horizontal scan of the frame field at the same time with 300 lines and repeating them 300 times during the frame field time. The image is projected onto a matte screen by a projection mirror-lens system 166, increasing it by 20 times.

The technical and economic effect of the claimed system consists in increasing the average brightness of the reproduced image by 9 · 10 ⁴ times against the prototype. The system can be used for digital television broadcasting on existing terrestrial TV networks in the UHF range reserved for analog television.

Table 1 Technical specifications Values Transmission side
Color coding 2: 2: 2 / E _R , E _G , E _in / Usable Terrestrial Network Ranges 420-790 MHz Carrier frequencies / option / 1st 450 MHz, 2nd 540 MHz Transmission of video codes E _R top side. 480 MHz E _G lower side. 420 MHz E _B top. side. 570 MHz. System Clock 30 MHz / 600 · 25 · 250 · 8 / Occupied bandwidth 294 Hz Number of encoded and transmitted strings 600 The number of encoded samples per line 500 Video Sampling Rate 3.75 MHz Frame rate - / field frequency 25 Hz / 50 Hz Line Scan / Line Frequency 7.5 kHz / 15 kHz Horizontal Scan Period / Line Length 133 μs / 66.6 μs Horizontal scan voltage waveform isosceles triangle, without backward strokes Coding method separate, linear PCM Video coding 255 level, 8 bits, 2 ⁸ Code duration 266 ns Sound resolution 45 kHz / 15 kHz × 3 / Sound coding 65536 level, 2 ¹⁶ , 16 bits. Information transfer rate 180 Mbps Receiving system Color coding 4: 4: 4 The number of lines in the frame 600 The number of samples per line 1000/500 × 2 / Video Sampling Rate 7.5 MHz The number of emitters 300 Frame format 1.67: 1 Frame Resolution Elements 600,000 ale / 600 × 1000 / Instantaneous maximum brightness of one emitter 248600 cd / m ²

Used sources.

1. Patent No. 2165681, cl. H 04 N 11/04, bull. 11 from 04/20/01, prototype.

2. Radio transmitting devices. M.S. Shumilin et al. 1981, M., p. 234, 235.

3. Fridland M.V., Soshnikov V.G. Automatic control systems in video recording devices. M., 1988, p.118 fig.5.5, p.122 fig.5.10.

4. Samoilov V.F., Lame B.P. TV. M., 1975, p. 370, 367.

5. E. Iceberg. TV? It is very easy! L., 1967, p. 188.

6. L.M. Kuchekyan. Light guides. M., 1973, p.77.

7. Digital integrated circuits. Minsk, 1991, p. 128, 231, 258.

8. Shilo V.A. Popular digital circuits. Chelyabinsk, 1989, p. 222.

9. Brodsky M.A. TVs color image. Minsk, 1988, p. 86 fig. 2.55, p. 132 fig. 4.2.

10. Radio communications, broadcasting, television, ed. HELL. Fortushenko. M., 1981, p. 146.

11. Barkan V.F., Zhdanov V.K. Amplification and impulse technology. M., 1981, p. 209.

12. “Radio” No. 7, 1998, p. 71.

Claims (1)

A digital television system containing a transmitting side, including a photoelectric converter, a first, second, third ADC, the inputs of which are connected to the corresponding outputs of the photoelectric converter, a fourth and fifth ADC, the information inputs of which are accompanied by sound signals, serially connected sine wave generator and frequency synthesizer , the first and second code shapers, the first information input of the first code shaper is connected to the output of the first ADC, the first and The information inputs of the second code generator are connected to the outputs of the second and fifth ADCs, the first and second self-propelled pulse distributors, the outputs of the first self-propelled pulse distributor are connected and connected to the third information input of the second code generator, the outputs of the second self-propelled pulse distributor are connected and connected to the fourth information input of the second code generator, the input of the second self-propelled pulse distributor is connected to the sixth output of the frequency synthesizer, the first the output of which is connected to the clock input of the third ADC and to the first control input of the second code generator, the second output of the frequency synthesizer is connected to the second control input of the second code generator, the third output is connected to the second control inputs of the fourth and fifth ADCs, the fourth output is connected to the third control input of the second code generator, the fifth output is connected to the fourth control input of the second code generator and to the third control inputs of the fourth and fifth ADCs, and the radio transmitter a channel containing the first and second channels, the inputs of which are connected to the eighth output of the frequency synthesizer, each channel of the transmitter includes a carrier frequency generator, a single-band signal shaper, and an output amplifier; the second input of the shaper of the single-band signal of the first channel is connected to the output of the first shaper of codes, the photoelectric transducer contains a lens, a first piezoelectric reflector at the end, which is located in the focal plane of the lens, a second piezoelectric reflector with a reflector at the end, optically coupled to the reflector of the first piezoelectric deflector, connected in series horizontal scan, the input of which is connected to the seventh output of the frequency synthesizer, and the first amplifier, the output of which is connected to the first the first input of the piezoelectric deflector, the first source of positive reference voltage, the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector, the second source of negative reference voltage, the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector, serially connected frame scan unit, the first and second the inputs of which are connected respectively to the fifth and sixth outputs of the frequency synthesizer, and a second amplifier, the output of which is connected to the first input of the second o piezoelectric deflector, a third source of positive reference voltage, the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector, a fourth source of negative reference voltage, the output of which is connected to the third inputs of the second amplifier and second piezoelectric deflector, the first and second dichroic mirrors, three micro lenses, three photodetectors , three pre-amplifiers, the outputs of which are the outputs of the photoelectric transducer, the frame scan unit contains serially connected the And element, the master oscillator and the summing amplifier, the second input of which is connected to the first input of the And element, the control input of the summing amplifier is connected to the output of the And element, the summing amplifier contains a pulse counter and a decoder connected in series, the first and second pulse shapers and the output amplifier, the first input which is the first input of the summing amplifier, the counting input of the pulse counter is the second input of the summing amplifier, the control input of the pulse counter is The input input of the summing amplifier, the first, second, and third ADCs are identical and each contains a video amplifier and a piezoelectric deflector with a reflector at the end, a source of positive reference voltage, an emitter from a pulsed LED, a slit aperture, and a micro lens, a multi-element photodetector line, and an encoder, the outputs of which are ADC outputs, the control input is the pulse LED input, the fourth and fifth ADCs are identical, each includes a series-connected voltage divider, a block of keys, matching the first amplifier, amplifier and piezoelectric deflector with a reflector at the end, a source of positive reference voltage, a source of negative reference voltage, a radiator from a pulsed LED, a slit aperture, and a micro lens, a series array of a multi-element photodetector, a first decoder, an encoder and a second decoder connected in series with a pulse counter, the third decoder and the block of registers, the outputs of which are the outputs of the ADC, the first control input is the counting input of the pulse counter, the second is the combined input of the pulsed LED and the fourth control input of the register block, the third is the control input of the pulse counter, the second code generator contains serially connected trigger and switching block and four channels, the inputs of the first and second channels are connected to the corresponding outputs of the switching block, and the outputs of four channels combined, the first channel includes series-connected the first block of AND elements, the first and second OR elements and the first output key, and the first self-propelled distributor pulses, the second channel includes a second block of AND elements connected in series, a third and fourth OR element, and a second output switch, and a second self-propelled pulse distributor, the first inputs of the first and second blocks of AND elements connected to the corresponding outputs of the switching unit, the second inputs of the first block of AND elements connected to the outputs of the first self-propelled pulse distributor, the second inputs of the second block of elements AND are connected to the outputs of the second self-propelled pulse distributor, the third channel includes a follower If the third block of AND elements and the fifth OR element and the third self-propelled pulse distributor are connected, the output of the fifth OR element is connected to the second input of the second OR element, the fourth channel includes the fourth block of AND elements and the sixth OR element, and the fourth self-propelled pulse distributor, output of the sixth OR element is connected to the second input of the fourth OR element, the second inputs of the third and fourth blocks of AND elements are connected to the outputs of the third and fourth self-propelled pulse dividers, the code generator also includes the first and second keys and a pulse counter and a decoder connected in series, two outputs of which are connected respectively to the first and second inputs of the first and second keys, the output of the first key is connected to the inputs of the first and second self-propelled pulse distributors, the output of the second key connected to the inputs of the third and fourth self-propelled pulse distributors, the output of the second code generator is the combined output of the output keys, the first and second inform The input inputs are the inputs of the switching unit and the inputs of the third and fourth blocks of AND elements, the third and fourth information inputs are the third inputs of the second and fourth OR elements, respectively, the first control input is the trigger input, the second is the combined key inputs and the counting input of the pulse counter, and the third the combined inputs of the signal inputs of the first and second output keys, the fourth is the control input of the pulse counter, and containing the receiving side, including the antenna, the touch control unit the first path for receiving and processing codes of video signals, the second path for receiving and processing codes of video signals whose inputs are connected to the antenna, the first, second, third blocks of pulse amplifiers, the modulation block of radiation, the corresponding inputs of which are connected to the corresponding outputs of the blocks of pulse amplifiers, connected in series divider / 2: 1 / frequency, horizontal scanning unit, the first amplifier and the first piezoelectric deflector with a reflector at the end, the first source of positive reference voltage, the output of which is connected n to the second inputs of the first amplifier and the first piezoelectric deflector, the second source of negative reference voltage, the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector, the second amplifier and the second piezoelectric deflector with a reflector at the end, the third source of positive reference voltage, the output of which is connected to the second inputs the second amplifier and the second piezoelectric deflector, the fourth source of negative reference voltage, the output of which is connected to the third inputs of the second amplifier and the second piezo the reflector, and the matte screen, the reflector of the first piezoelectric deflector is optically connected to the reflector of the second piezoelectric deflector, the first path for receiving and processing video signal codes contains serially connected radio signal receiving unit, the first input of which is connected to the antenna, the second group of inputs is connected to the first group of outputs of the touch control unit, amplifier radio frequencies and a bipolar amplitude detector, and a channel for processing video signal codes E _R including the first and second pulse shapers, the inputs of which are connected to the first and second outputs of the bipolar amplitude detector, and the first register of the video signal E _R the information input of which is connected to the output of the first pulse shaper, the second path for the reception and processing of video signal codes contains a serially connected radio signal receiving unit, the first input of which is connected to the antenna, the second group of inputs is connected to the first group of outputs of the touch control unit, the radio frequency amplifier, and a bipolar amplitude detector , and the channel for processing video signal codes E _G including the first and second pulse shapers, the inputs of which are connected to the first and second outputs of a bipolar amplitude detector, the first and second video signal registers E _G , the receiving side includes two identical sound channels, each contains a first key and a first block of sound registers connected in series, a second key and a second block of sound registers connected in series and a DAC in series, the inputs of which are connected to the outputs of the first and second blocks of sound registers, the filter is low frequency, power amplifier and loudspeaker, and includes a channel for generating control signals, comprising a block for selecting horizontal sync pulses, connected in series the key, pulse counter and decoder, and the frame sync pulse extraction unit, the first decoder output is connected to the first control inputs of the first and second keys in the sound channels, the second decoder output is connected to the second control inputs of the first and second keys in the sound channels, to the control the input of the pulse counter and to the second control input of the key, the block for selecting horizontal sync pulses and the block for selecting frame sync pulses are identical and each includes two impulse counters xy, two NOT elements, one AND element and a diode, the inputs of the first and second elements are NOT connected to the inputs of the first and second pulse counters, the outputs of the elements and the output of the AND element through a diode are combined and connected to the control inputs of the pulse counters, the outputs of the first and second counters pulses are connected to the inputs of the And element, the inputs of the pulse counters are connected: the block selection of horizontal sync pulses to the outputs of the first pulse shapers in the first and second paths of the reception and processing of codes of video signals, block selection frame new clock pulses to the outputs of the second pulse shapers in the first and second paths for receiving and processing video codes, characterized in that on the transmitting side the clock inputs of the first and second ADCs are connected to the first output of the frequency synthesizer, the first shaper is identical to the second shaper, second, third, the fourth information inputs of the first code generator are connected respectively to the outputs of the fourth ADC, the output of the first self-propelled pulse distributor, and the output of the second self-propelled race pulse changer, the first, second, third and fourth control inputs of the first code generator are connected respectively to the first, second, fourth and fifth outputs of the frequency synthesizer, the decoder in the first code generator has a third output, which is the second output of the first code generator and is connected to the input of the first self-propelled pulse distributor, the first control / clock / inputs of the fourth and fifth ADCs are connected to the second output of the frequency synthesizer, on the transmitting side a third driver The first, second, third information inputs of which are connected respectively to the outputs of the third ADC, the first self-propelled pulse distributor and the second self-propelled pulse distributor, the first, second, third control inputs are connected respectively to the first, second, fourth outputs of the frequency synthesizer, the third code generator includes sequentially a connected trigger and a switching unit and two identical channels, the first channel contains a series-connected block of AND elements, the first and second OR elements and the output key, and the first self-propelled pulse distributor, the second channel contains a series of AND elements, the third and fourth OR elements, and the output key, and the second self-propelled pulse distributor, the first inputs of the And blocks connected to the corresponding outputs of the switching unit, the second inputs of And connected to the outputs of the self-propelled pulse distributor of its channel, the outputs of the output keys are combined and are the output of the third code generator, the first, second, third information inputs which are the inputs of the switching unit, the second inputs of the second and fourth elements OR, the first, second, third control inputs are: the first is the trigger input, the second are the combined inputs of the first and second self-propelled pulse distributors, the third are the combined signal inputs of the output keys to the transmitter a third channel is introduced of the radio signal, including a serially connected single-band signal shaper, the first input of which is connected to the output of the carrier frequency generator in the first channel, the second input is connected is connected to the output of the second code generator, and the output amplifier, the second input of the first-band signal generator of the first channel is connected to the first output in the first code generator, the second input of the second-channel signal generator of the second channel is connected to the output of the third code generator, the third and the fourth pulse shaper, and from the first to the 299th outputs of the decoder are combined and connected to the input of the first pulse shaper, the 300th output of the decoder is connected the input of the second pulse shaper, from 301 to 599 the outputs are combined and connected to the input of the third pulse shaper and the 600th output of the decoder is connected to the input of the fourth pulse shaper, the outputs of all pulse shapers are combined and connected to the second input of the output amplifier, the third path is introduced receiving and processing codes of video signals, containing a series-connected block for receiving a radio signal, the input of which is connected to the antenna, the second group of inputs is connected to the first group of outputs of the bl Single touch control, the radio frequency amplifier and a bipolar amplitude detector and a video signal processing channel codes E _IN comprising first and second pulse shapers whose inputs are connected respectively to the first and second outputs of a bipolar amplitude detector, the first and second video signal registers E _IN , information input of the first register of the video signal E _IN connected to the output of the first pulse shaper, the information input of the second register of the video signal is connected to the output of the second pulse shaper, the code processing unit and the code store connected in series, the corresponding outputs of which are connected to the corresponding inputs of the third block of pulse amplifiers, the first and second information inputs of the code processing unit are connected to the outputs, respectively, of the first and second registers of the video signal E _IN into the channel for processing video signal codes E _R the first path of the reception and processing of codes of video signals entered the second register of the video signal E _R the information input of which is connected to the output of the second pulse shaper of its channel, the code processing unit and the code store are connected in series, the first and second information inputs of the code processing unit are connected respectively to the outputs of the first and second video signal registers E _R , the outputs of the code storage device are connected to the corresponding inputs of the first block of pulse amplifiers, in the channel for processing video signal codes E _G the second path of the reception and processing of codes of video signals, a series-connected code processing unit and a code storage device are introduced, the outputs of which are connected to the corresponding inputs of the second block of pulse amplifiers, the information input of the first video signal register E _G connected to the output of the first pulse shaper, the information input of the second register of the video signal E _G connected to the output of the second pulse shaper of its channel, a projection optical system is introduced containing sequentially spherical mirrors, a flat mirror with an angle of 45 ° relative to the optical axis of the spherical mirror and a correction lens, a frequency synthesizer and a frequency doubler of frame sync pulses are introduced into the channel for generating control signals, the first the input of the frequency synthesizer is connected to the output of the horizontal sync pulse allocation unit, the second group of inputs is connected to the second group of outputs sensor control unit, the first output of the frequency synthesizer is connected to the first control inputs of the first and second video signal registers E _R , E _G , E _IN and to the control inputs of the code processing blocks, the second output is connected to the key input, the third output is connected to the second control / clock / inputs of the first and second video signal registers E _R , E _G , E _IN and to the second control / clock / inputs of the first and second blocks of sound registers, the fourth output is connected to the first control inputs of the first and second blocks of sound registers, the fifth output is connected to the third inputs and blocks of the reception of the radio signal in the first and second paths of the reception and processing of video signal codes, the sixth output is connected to the third input of the radio signal receiving unit in the third path for receiving and processing video signal codes, the seventh output is connected to the second control inputs of the code storage devices, the output of the frame sync allocation block pulses are connected to the input of the frequency doubler of the frame clock pulses, the output of which is connected to the first control inputs of the code storage devices and to the input of the second amplifier, the code processing units are identical, each includes the first, second, third, fourth registers, the first, second, third blocks of delay elements, the fifth and the sixth registers, the adder and the corresponding number of diodes, the information inputs of the first and second registers are connected to the outputs of the first block of delay elements, the outputs of the first register are connected to the inputs of the fifth reg tra and through the diodes connected to the first inputs of the adder; the outputs of the second register are connected to the first inputs of the adder, the information inputs of the third and fourth registers are connected to the outputs of the second block of delay elements, the outputs of the third register are connected to the inputs of the sixth register and through diodes to the second inputs of the adder, the outputs of the fourth register are connected to the second inputs of the adder, the outputs of which connected to the inputs of the third block of delay elements, the outputs of the fifth, sixth registers and the third block of delay elements are bitwise combined and are the output of the processing unit an ode, the first and second information inputs of which are the inputs of the first and second blocks of delay elements, the control input is the combined inputs of the trigger and the control input of the adder, the first output of the trigger is connected to the control inputs of the second, third and fifth registers, the second output of the trigger is connected to the control inputs of the first of the fourth and sixth registers, the code stores are identical and each includes three hundred identical blocks of registers, 1-7 information inputs of which are bitwise combined and are inf the code drive memory inputs, the outputs of 1-300 register blocks are bitwise combined and are the code drive outputs, the first control input of the first register block is the first control input of the code drive, the second control input is the combined third control inputs of 1-300 register blocks, each first output of the previous block of registers is connected to the first control input of the subsequent block of registers, the first output of the 300th block of registers is connected in parallel to the fourth control inputs of 1-300 blocks registers, every second output of the previous block of registers is connected to the second control input of the subsequent block of registers, the second output of the 300th block of registers is connected in parallel to the fifth control inputs of the 2-300th block of registers and to the second, and through the diode to the first control inputs of the first block of registers, each block of registers includes the first, second, third, fourth keys, first, second, third and fourth pulse distributors, serially connected to the first pulse counter and the first decoder, the output of which connected to the second control input of the second key, a second counter and a second decoder connected in series, the output of which is connected to the second control input of the fourth key, includes the first seven registers and the second seven registers, each of which contains bits in the number of samples in a row, the first control input of the first key is the first control input of the register block, the signal inputs of the four keys of the register block are combined and are the third control input of the register block, the output of the first key under is connected to the input of the first pulse distributor, the outputs of which are connected in series to the first control inputs of each bit of the first seven registers, the last output is connected to the first control inputs of the last bits of the first seven registers and to the second control input of the first key, in the first block of registers the first control input of the second key and the first control input of the third key are combined and are the fourth control input of the first block of registers, in the 2-300th blocks of registers the first control input of the second Lucha is the fourth control input, the output of the second key in the 1-300th register blocks is connected to the input of the second pulse distributor, the outputs of which are connected in series to the second control inputs of each bit of the first seven registers, the last output is connected to the second control inputs of the last seven in the first seven registers and to the input of the first pulse counter, the third control inputs of each bit of the first seven registers are connected to the output of the first decoder, the information inputs of the bits of the first seven p registers are combined by registers and are 1-7 information inputs of the register block, the outputs of all bits in each register are combined and are 1-7 outputs of the register block, the output of the third key is connected to the input of the third pulse distributor, the outputs of which are connected in series to the first control inputs in each the discharge of the second seven registers, the last output is connected to the first control inputs of the last bits of the second seven registers and to the second control input of the third key, in the first block of registers the first the control input of the fourth key is the second control input of the register block, in the 2-300th register blocks, the first control input of the fourth key is the fifth control input of the register block, in 1-300 register blocks the output of the fourth key is connected to the input of the fourth pulse distributor, the outputs of which are connected sequentially to the second control inputs in each category of the second seven registers, the last output is connected to the second control inputs of the last bits of the second seven registers and to the input of the second counter and pulses, the third control inputs of each bit of the second seven registers are connected to the output of the second decoder, the information inputs of the bits of the second seven registers are combined by registers and connected to 1-7 information inputs of the register block, the outputs of the bits of each of the second seven registers are combined and connected to 1- 7 outputs of the block of registers, in the first block of registers the second control input of the block through the diode is combined with the first control input, the control outputs in each block of registers are: the first is the last output the first pulse distributor, the second - the last output of the third pulse distributor, the pulse amplifier blocks are identical, each includes pulse amplifiers in the number of register blocks in the code store and the number of bits in the code, the radiation modulation block contains 300 channels, each of which includes three emitter in series primary colors, containing the corresponding number of LEDs, the lens and the focusing cone of the fiber, the inputs of the block are the inputs of the emitters connected to the outputs respectively of the existing pulsed amplifier units, the emitting planes of the emitters are located in the rear focal plane of the lenses, in the front focal plane of which are the input windows of the focusing cones of the optical fibers, the radiators are optically connected to the reflector of the first piezoelectric deflector, which is located in the focal plane, through the lenses focusing the cones of the optical fibers a spherical mirror of the projection optical system, in the outer focal plane of which is located a matte screen, a third pulse counter, a third element AND a second element AND, the input of the third element is NOT connected to the input of the third pulse counter, and the output of the third element is NOT combined with the outputs of the first and second elements NOT, the first input of the second element And is connected to the output of the first element And, the second input of the second element And is connected to the output of the third pulse counter, the output of the second element And is the output of the unit and connected through a diode to by the outputs of the NOT elements, the input of the third pulse counter in the block for selecting horizontal sync pulses is connected to the output of the first pulse shaper in the third path for receiving and processing codes of video signals, the input of the third pulse counter in the block for extracting frame sync pulses is connected to the output of the second pulse shaper in the third path for receiving and processing codes video signals.

Images