RU2214693C2 - Digital high-definition tv system - Google Patents

Abstract

FIELD: radio communication, TV broadcasting in decimeter range of ground TV networks and over satellite communication systems. SUBSTANCE: transmission side of known system is supplemented with third code former, transmitter is complemented with third channel, receiving side is added with third path of reception and processing codes of video signal that incorporates unit receiving radio signal, radio frequency amplifier, double- pole amplitude detector and channel processing codes of video signal E_v, including first and second pulse formers, first and second registers, code processing unit, first and second units of delay elements and adder. First and second paths are supplemented with code processing units, first and second units of delay elements, adder, fourth, fifth and sixth units of pulse amplifiers. Channel forming controlling signals is complemented with frequency synthesizer, radiation modulation unit is added with second radiator of three key colors. Occupied frequency band is 363 Hz, number of definition elements in frame amounts to 2,2•10⁶.. EFFECT: increased definition capability of TV picture. 17 dwg, 2 tbl

Description

 The invention relates to radio communications technology and can be used for television broadcasting in the decimeter range of terrestrial TV networks and via satellite communication lines.

 An analogue is the digital television system [1], the disadvantages of which are the transmission of information over four radio channels and the insufficient resolution of the image in the frame of 625 lines with the number of samples 854 in each, 533,750 elements in the frame.

 The digital television system [2] was adopted as a prototype, it contains a photoelectric converter, three ADCs of a video signal, two ADCs of a sound signal, a sinusoidal oscillation generator and a frequency synthesizer, the first and second video signal shapers, the first and second self-propelled pulse distributors, a two-channel radio signal transmitter , on the receiving side, an antenna, a touch control unit, two paths for receiving and processing video signal codes, a channel for generating control signals, two audio channels with Activity three block pulse amplifiers radiation modulation unit horizontal and unit pezodeflektor first unit and a second frame scanning pezodeflektor four reference voltage source and a matte screen.

[3,с.46], занимаемая полоса в эфире 213 Гц.The information is transmitted via two radio channels: the first codes of the video signals E _R and E _B are transmitted, the second - the codes of video signal E _G. Two radio signals are received at the receiving side, amplified, detected, unit symbols in the codes are converted from half-sine waves to pulses, video signal codes are distributed over their channels and a color image is reproduced on the matte screen without conversion to analog video signals, audio signal codes are converted to analog signals. The clock frequency in the system is 54 MHz, the active lines in the frame are 625, the number of samples is 864, the resolution elements in the frame

[3, p. 46], the occupied band in the air is 213 Hz.

 The disadvantage of the prototype is the lack of resolution of the television image.

 The aim of the invention is to increase the resolution of the television image.

The technical result of the claimed system is to increase by 4 times the resolution of the image from 540,000 elements in the frame to 2.2 • 10 ⁶ . Image playback is performed by 1100 active lines in the frame with the number of samples in each 2000. The occupied band on the air during 363 Hz transmission. The clock frequency in the system is 55 MHz.

 Technical characteristics of the system are given in table. 1.

The transmitting side generates three code stream: the first - video codes E _R, the second - E _G, the third - E _B. Two carrier frequencies are used. The receiving side receives three radio signals with three paths for receiving and processing codes, selects lowercase / SSI / and frame / CSI / clock pulses, doubles the frequency of the video signal codes per line / 27.5 MHz /, doubles the number of lines in the frame / 1100 /, converts the codes electronically Optical scan in color image on a matte screen.

The essence of the claimed system is that in a digital high-definition television system containing a photoelectric converter, five ADCs, a sine wave generator, a frequency synthesizer, the first and second code generators, the first and second self-propelled pulse distributors, a radio signal transmitter including the first and the second channel, containing on the receiving side an antenna, a touch control unit, a first path for receiving and processing a video signal, including a radio signal receiving unit, a radio amplifier frequencies, a bipolar amplitude detector and a channel for processing video signal codes E _R , including two pulse shapers, first and second video signal registers E _R , a second path for receiving and processing video signal codes, comprising a radio signal receiving unit, a radio frequency amplifier, a bipolar amplitude detector, and a channel for processing video signal codes E _G , including two pulse shapers, first and second video signal registers E _G , a channel for generating a signal control, including a block for selecting a horizontal sync pulse, self-propelled pulse distributor, key, pulse counter, decoder and frame sync extractor, two sound impedance channels, frequency divider, horizontal scan unit, first amplifier and first piezoelectric deflector, vertical scan unit, second amplifier and second piezoelectric deflector, four voltage sources, three a block of pulse amplifiers, a modulation block and a matte screen, a third code generator is introduced on the transmitting side, a third channel, including a carrier frequency amplifier, a driver Rinse signal and an output amplifier on the receiving side is entered a third channel for receiving and processing video codes, comprising a reception unit of radio signal power radio frequency bipolar amplitude detector and code channel for processing a video signal _EV which includes two of the pulse, the first and second registers video signal _EV, a code processing unit, the first and second blocks of delay elements and an adder, a code processing unit, the first and second blocks of delay elements and an adder, are entered into the channel Ia control signals enter the frequency synthesizer entered fourth, fifth and sixth blocks in the amplifiers and pulse modulation of the radiation unit entered the second emitter three primary colors.

The block diagram of the transmitting side is shown in figure 1; the formation of the solution and the types of control voltages in figure 2; functional diagram of the ADC video signal - figure 3; functional diagram of the ADC of the sound signal - figure 4; the design of the piezoelectric deflector - figure 5; the structure of the digital streams from the transmitting side - in Fig.6; functional diagram of the third code generator - Fig.7; functional diagram of the first and second code / video signal conditioners E _R , E _G / - in Fig. 8; block diagram of the receiving side - in Fig.9; Schematic diagram of a bipolar amplitude detector - figure 10; functional diagram of the block selection line / frame / clock pulse - figure 11; functional block diagram of the code processing - in FIG. 12; summing amplifier - in Fig.13; radiation modulation unit - in FIG. 14; spectra at the output of the transmitter - in Fig.15; timing diagrams of the system - in Fig.16; block delays in Fig.17.

 The transmitting side includes / Fig. 1 / a photoelectric transducer 1, which is a sensor of three primary colors and containing a lens 2, a first piezoelectric reflector 3 with a reflector at the end, the first source of positive reference voltage 4, the second source 5 of negative reference voltage, the first amplifier 6, block 7 horizontal scan from the master oscillator 9 and the output stage 9, the second piezoelectric deflector 10 with a reflector at the end, the third source 11 of the positive reference voltage, the fourth source 12 of the negative reference voltage Iya, the second amplifier 13, the frame scan unit 14 from the And element 15, the master oscillator 16 and the summing amplifier 17, the first 18 and second 19 dichroic mirrors, the first 20, the second 21, the third 22 micro lenses, the first 23, the second 24, the third 25 photodetectors first 26, second 27, third 28 preamplifiers.

The photoelectric converter 1 is part of the transmitting television camera, which includes the first ADC 29 / video signal E _R /, the second ADC 30 / video signal E _G /, the third ADC 31 / video signal E _B /. The transmitting side includes a fourth ADC 32 and a fifth ADC 33 of a sound signal, serially connected a master oscillator 34 of a sinusoidal oscillation and a synthesizer 35 frequencies, a first driver 36 codes / video signal E _R /, a second driver 37 codes / video signal E _G /, a third driver 38 codes / video signal E _B /, the first self-propelled distributor of pulses 39, forming the horizontal sync pulse code of the SSI, the second self-propelled distributor 40 pulses, generating the code of the frame sync pulse of the CSI. The transmitter 41 has three channels. The first channel contains a series-connected amplifier of the first carrier frequency 42, the first driver of a single-band signal and an output amplifier 44, the second channel contains a second driver of a single-band signal and an output amplifier 46, the third channel contains an amplifier 47 of a second carrier, a third driver of a 48 single-signal signal and output amplifier 49.

 Each shaper of a single-band signal consists of a series-connected ring modulator and a band-pass filter [4, p.234]. The first carrier frequency is suppressed in the first single-band signal driver 43, the lower side frequency is filtered out with a band-pass filter, and the upper modulated side frequency is broadcast. In the second driver 45, the first carrier frequency is suppressed, the upper side frequency is filtered out with a band-pass filter, and the lower modulated side frequency is broadcast. In the third driver 48, the second carrier frequency is suppressed, the lower side frequency is filtered out, the upper modulated side frequency is broadcasted (Fig. 15/). The ADCs 29, 30, 31 are identical (Fig. 3/), each contains an amplifier 50, a piezoelectric deflector 51 with a reflector at the end, a first source of positive voltage reference 52, a second source of negative voltage reference 53, emitter 54 including a pulsed LED 55, aperture diaphragm 56 and a micro lens 57, line 58 of the multi-element photodetector and encoder 59. The ADCs 32, 33 are identical and each includes a voltage / voltage divider 60, a key block 61, a matching amplifier 62, an amplifier 63, and a piezoelectric deflector 64 with a reflector at the end, the first source 65 will put reference voltage, a second source of negative reference voltage 66, an emitter 67 of a pulsed LED 68, a slit aperture 69 and a micro-array 70, a multi-element photodetector line 71, a first decoder 72, an encoder 73, a second decoder 74 and a pulse counter 75 connected in series, a third decoder 76 and block of 77 registers.

 All piezoelectric deflectors are structurally identical (Fig. 5/), each includes [5, p. 118] the first 78 and the second 79 piezoelectric plates, the internal electrode 80, the first 81 and the second 82 external electrodes, one end of the piezoelectric plates is fixed in the holder 83, at the free end fixed light reflector 84.

The first 36 and second 37 code generators are identical and each includes / Fig. 8 / serially connected trigger 85 and switching unit 86 and four channels, the first and second channels are identical. The first includes series-connected the first block of 87 AND elements, the first 88 and second 89 OR elements, the first output switch 90 and the first self-propelled pulse distributor 91, the second channel includes the second block 92 of AND elements, the third 93 and fourth 94 OR elements, the second output a key 95 and a second self-propelled distributor 96 pulses. The third channel includes a third block of AND elements 97, a fifth OR element 98 and a third self-propelled pulse distributor 99, a fourth channel includes a fourth block 100 of AND elements, a sixth OR 101 element and a fourth self-propelled pulse distributor 102. Shapers 36 and 37 include the first 103, the second 104 keys, and a pulse counter 105 and a decoder 106 connected in series. The information inputs of the shapers 36, 37 are: the first are the inputs of the switching unit 86, the second are the inputs of the blocks 97, 100 of the elements of the third and fourth channels, the third and fourth - the third inputs of the second and fourth elements OR 89, 94 connected to the outputs of blocks 39, 40. The output is the combined outputs of the output keys 90, 95 connected to the formers 43, 45 of a single-band signal. In the first shaper 36 codes, the decoder 106 has a third output, which is the second output of the shaper 36 codes, which is connected to the input of the self-propelled pulse distributor 39, supplying its output signal U _p start. The control inputs of the shapers 36, 37 are: the first is the trigger input 85 connected to the first output of the 35 / 13.75 MHz / block, the second is the combined inputs of the keys 103, 104 and the counter 105 connected to the second output of the 35 / 6.875 MHz / block the third is the signal inputs of the output keys 90, 95 connected to the fourth output of the 35/55 MHz unit /, the fourth is the control input of the pulse counter 105 connected to the fifth output of the 35 / 13.75 kHz / unit.

 The third code generator 38 includes (Fig. 7) a serially connected trigger 107 and a switching unit 108 and two identical channels, each of which includes a block of 109 AND elements, a first 110, a second 111 OR elements, and an output key 112 in the first channel and 113 in the second channel and the self-propelled distributor of 114 pulses in the first channel and 115 in the second channel. The first information input of block 38 is the inputs of switching unit 108, the second and third information inputs are second inputs of second elements OR 111 in the first and second channels. The output of block 38 is the combined outputs of the output keys 112, 113. The control inputs are: the first is the input of the trigger 107 connected to the first output of the frequency synthesizer 35, the second is the inputs of the self-propelled pulse distributors 114, 115 connected to the second output of the block 35, and the third are signal the inputs of the output keys 112, 113 connected to the fourth output of block 35.

The receiving side / digital television receiver / contains / FIG. 9/ antenna, sensor control unit 116, first, second and third paths for receiving and processing video signal codes, a channel for generating control signals and two audio channels. The first path of the reception and processing of video signal codes receives and processes the video signal codes E _R and comprises a radio signal receiving unit 117, a radio frequency amplifier 118, a bipolar amplitude detector 119, and a video signal code processing channel E _R , which includes a first 120, a second 121 pulse shapers, the first 122 , the second 123 video signal registers E _R , the series-connected code processing unit 124, the first delay element block 125, the adder 126 and the second delay element block 127. The second path for receiving and processing codes receives and processes video signal codes E _G and comprises a radio signal reception unit 128, a radio frequency amplifier 129, a bipolar amplitude detector 130, and a video signal code processing channel E _G , including a first 131, a second 132 pulse shapers, a first 133, a second 134 video signal registers E _G , series-connected code processing unit 135, first delay element block 136, adder 137 and second delay element block 138.

The third path for receiving and processing video signal codes receives and processes video signal codes Е _В and comprises a radio signal receiving unit 139, a radio frequency amplifier 140, a bipolar amplitude detector 141, and a video signal code processing channel Е _В , which includes a first 142, a second 143 pulse shaper, and the first 144 second 145 registers the video signal _EV serially connected code processing unit 146, a first unit delay elements 147 and the adder 148 and the second block 149 delay elements. The control signal generating channel includes a serially connected horizontal sync pulse allocation unit / CCI /, a frequency synthesizer 151 and a self-propelled pulse distributor 152, a key 153 connected in series, a pulse counter 154, a decoder 155 and a frame sync pulse allocation unit 156. The sound channels are identical and each includes a first key 157 and a first block 158 of sound registers, a second key 159 and a second block 160 of sound registers connected in series by the DAC 161, a low-pass filter 162, a power amplifier 163 and a loudspeaker 164.

 The receiving side includes the first 165, second 167, third 169, fourth 166, fifth 168 and sixth 170 blocks of pulse amplifiers, a radiation modulation unit 171, a 2: 1 frequency divider 172, a horizontal scanning unit 173, a first amplifier 174, a first piezoelectric deflector 175 with a reflector at the end, the first source of positive reference voltage 176, the second source of negative reference voltage 177, the frame scanning unit 178 from the element And 179, the master oscillator 180 and the summing amplifier 181, the second amplifier 182, the second piezoelectric deflector 183 with the reflector at the end, third th source 184 positive reference voltage, the fourth source 185 negative reference voltage, frosted screen 186.

 Blocks 124, 135, 146 of the processing of video signal codes are identical and each includes / Fig. 12/ trigger 187, first 188, second 189, third 190, fourth 191 registers, first 192, second 194, third 196 delay element blocks, fifth 193 and sixth 195 registers, adder 197 and 16 diodes. Block 192 delays the codes by 10 ns, block 194 by 82, 72 ns, block 196 by 12, 36 ns. Registers 193, 195 receive, store for 72, 72 ns and issue codes in parallel. The first and second information inputs of block 124 are the inputs of block 192, 194, the output is the outputs of the third block 196 of delay elements, the control input is the input of trigger 187 and the control input of adder 197.

 The horizontal sync pulse allocation unit 150 and the frame sync pulse allocation unit 156 are identical and each contains / Fig. 11/ first 198, second 199, third 200 pulse counters, first 201, second 202 AND elements, first 203, second 204, third 205 NOT elements and diode. The inputs of the block are the counting inputs of the pulse counters, the output is the output of the second element And 202.

где 550_строк•25 Гц=13,75 кГц частота строк;

- число пар кодируемых отсчетов в строке на передающей стороне;
8_раз - число разрядов в коде.The summing amplifiers 17 and 181 / FIG. 13/ are identical and each includes a pulse counter 206, a decoder 207, a first 208, a second 209 keys, a first 210, a second 211 pulse shapers and an output amplifier 212. The inputs are the counter input of the counter 206 and the first input of the output amplifier 212, the output is the output of the output amplifier. The control input is the combined inputs of the second control input of the key 209, the first control input of the key 208 and the control input of the pulse counter 206. The radiation modulation unit 171 (Fig. 14) includes a first emitter 213 of three primary colors, a second emitter 214 of three primary colors and an optical system 215. The emitting plane of the emitters is located in the rear focal plane of the optical system, in the front focal plane of which there is a reflector of the first piezoelectric deflector 175 / Fig.9 /. The radiating sides of the emitters 213, 214 through the optical system 215, the reflectors of the piezoelectric deflectors 175, 183 are optically connected to the matte screen 198. The inputs of the first emitter are connected to the outputs of the pulse amplifier units 165, 167, 169, the inputs of the second emitter are connected to the outputs of the units 166, 168, 170 pulse amplifiers. Blocks 125, 136, 147 are identical and each includes the element And 216 / FIG. 17/, the first 217, the second 218 keys, the first 219, the second 220 pulse distributors, eight registers 221 ₁ -221 ₈ . Each of blocks 125, 136, 147 delays the codes of samples for a duration of 72, 72 μs. The clock frequency in the system is

where 550 _lines • 25 Hz = 13.75 kHz line frequency;

- the number of pairs of encoded samples in a row on the transmitting side;
8 _times - the number of bits in the code.

Photoelectric converter 1 generates three analog video signals supplied to the inputs of the ADC 29, 30, 31. Photoelectric converter 1 and three ADCs are structurally placed in a television transmitting camera, the output of which is three digital code of video signals E _R. E _G , E _B.

ADCs 29, 30, 31 convert analog video signals into eight-bit codes. The code generators 36, 37, 38 convert the parallel codes of video signals and sound into sequential ones and replace the representation of units from the pulse with positive half-sine waves in odd samples of the line and with negative half-sinusoids in even samples of mono frequency 55 MHz. The master oscillator 34 generates sinusoidal oscillations with a stability of 10 ^-7 . A frequency synthesizer 35 generates 13.75 MHz pulses from the frequency of the master oscillator 34 and outputs 13.75 MHz pulses to the ADC clock inputs 29, 30, 31 and to the first control inputs of the code shapers 36, 37, 39, and 6.875 MHz pulses from the second output to the first control inputs of the ADC 32, 33, to the second control inputs of the drivers 36, 37, 38 codes, from the third output pulses 55 kHz to the second control inputs of the ADC 32, 33, from the fourth sinusoidal oscillations 55 MHz to the third inputs of the drivers 36, 37, 38 codes , from the fifth, 13.75 kHz pulses to the fourth control inputs f riders 36, 37, to the third control inputs of the ADC 32, 33 and to the first input of block 15 of the And element, from the sixth output pulses of 25 Hz to the second input of block 15 and to the input of block 40, from the seventh output pulses of 6.875 kHz to the input of block 7 lowercase sweep, from the eighth sine wave 550 MHz of the first carrier frequency to the first input of the transmitter 41, from the ninth - second carrier frequency of 660 MHz to the second input of the transmitter 41.

The ADC 32, 33 converts two sound signals into sixteen-bit codes, which come from the ADC 32 to the second information input of block 36, from the ADC 33 to the second information input of the second code generator 37. A self-propelled distributor of 39 pulses with the arrival of a start signal U _p / from the second output of the shaper 36 / generates a code of eight units 11111111, which is the SSI horizontal sync pulse code, to the third inputs of the first and second shapers 36, 37 codes and to the second input of the third shaper 38 codes. The second self-propelled distributor of 40 pulses with the arrival of a starting pulse U _p 25 Hz gives a code of eight units 11111111, which is the frame sync pulse code of the CSI, to the fourth information inputs of the first 36 and second 37 code shapers and to the third information input of the third code shaper 38.

 Block 7 consists of a master oscillator 8 and an output stage 9. The control voltage of a triangular isosceles form (Fig. 2/) from block 7 is amplified in the amplifier 6 and brings the piezo deflector 3 into oscillatory motion with a frequency of 6.875 kHz, line scanning is with a frequency of 13.75 kHz . The signal from the amplifier 6 is supplied to the internal electrode 80 / Fig. 5/, the voltage from the source 4 is applied to the external electrode 81, the voltage of the source 5 is applied to the external electrode 82. When a control voltage is applied to the internal electrode, deformation occurs [5, p. 122] piezoelectric plates: one lengthens, the second is shortened, a bending moment of forces arises, the end face with light reflector 84 rotates and deflects the vertical strip of the image, and the line scan is in progress. The image of the vertical strip enters the reflector of the second piezoelectric deflector 10, which produces a vertical scan of the image, performing a frame scan.

 The process of operation of the piezoelectric deflector 10 is the same as the piezoelectric deflector 3, but it oscillates with a frequency of 25 Hz, 50 fields per second. The reflector width of this piezoelectric deflector is 0.01 mm. The width of the reflector of the piezoelectric deflector 10 is also 0.01 mm, the length is 10 mm / 0.01 mm • 1000 /. Both line and frame scans go without reverse moves / Fig. 2 / according to the control voltages from the amplifiers 6 and 13. From the output of the summing amplifier 17, a ramp voltage is amplified, amplified by the amplifier 13. In the first half of the scan period, the piezoelectric reflector 10 deflects the image down, in the second half of the period / second field of the frame / scan is up . The summing amplifier 17 sums the triangular voltage from the master oscillator 16 with 13.75 kHz pulses, which gives a linear step voltage for the amplifier 13. Each pulse of the line moves the line at the end of its stroke a step in the width of two lines at the time of the ray entry over the edge with one and on the other side of the frame. Obtained on the transmitting side of 550 lines per frame / for two fields /.

The purpose of the blocks 206-211 / FIG. 13/ in the summing amplifier 17 is to send negative / positive / pulses of the corresponding amplitude and duration to the second input of the amplifier 212 at the right time. Before the frame scan, the zeroing signal U _{0 of} 25 Hz from the And 15 element resets the bits of the counter 206. The ten-digit counter counts 13.75 kHz pulses, the count cycle 550. At the end of the scan of the first field of the frame with the arrival of 275 pulses / 549th line from odd lines / counter 206 generates a binary code that is decoded by the decoder 207 into a signal, leading edge closing the first key 208 and opening the second key 209, transmitting 13.75 kHz pulses to the second pulse shaper 211, which provides positive pulses to the second input of the amplifier 21 2. Follows the sweep of the second field of the frame. With the arrival of the leading edge of the next frame pulse to the input of AND element 15, the counter 206 is reset to zero, followed by a downward scan / first field of the frame /. The reflected rays from the reflector of the piezoelectric deflector 10 arrive: red are reflected from the first dichroic mirror 18 and are collected by a micro-lens 20 into a photodetector 23, blue are transmitted from the second dichroic mirror 18, reflected from a second dichroic mirror 18 and collected by a micro-lens 22 are collected into a photodetector 25, both mirrors 18, 19, pass through green with a micro-lens 21, they are assembled into a photodetector 24. From the photodetectors, analog video signals are fed to their pre-amplifiers 26, 27, 28.

 The ADCs 29, 30, 31 have one conversion principle, which consists in scanning the beam (Fig. 3/) from the LED by the piezoelectric reflector along the plane of the entrance pupils of the line 58 of the multi-element photodetector. The light pulse is converted by the photodetector in line 58 into an electrical signal that excites one of the input buses of the encoder 59, which provides a code for the instantaneous value of the input video signal. The conversion frequency is 13.75 MHz.

The slit aperture 56 and the micro-lens 57 form a beam with an aperture equal to the size of the input window of one photodetector in line 58. A pulsed LED AL402A with a pulse rise time of 25 ns is accepted as a radiation source, which with a margin satisfies 13.75 MHz / 72.72 ns / sampling. Line 58 includes 255 photodetectors for encoding video signals with an eight-bit code 2 ⁸ . Photodetectors are avalanche photodiodes of the APD with a response time of 10 ns. The outputs of each photodetector are connected to the corresponding inputs of the encoder 59, which represents the K155IV1 microcircuit [6, p. 231] with a response time of 20 ns. The encoder generates codes from 00000001 to 11111111. Moreover, the first photodetector in line 59 corresponds to the code 00000001, the second to 00000010, the third to 00000011, etc., 255 to 11111111.

АЦП 32, 33 преобразуют два звуковых сигнала в шестнадцатиразрядные коды. За время одной строки каждый АЦП формирует четыре кода, частота дискретизации 55 кГц /13,75 кГц•4/. Импульсы дискретизации поступают как сигналы на излучение светодиода 68 /фиг.4/. Линейка 71 многоэлементного фотоприемника содержит 1024 фотоприемника и осуществляет преобразование звукового сигнала в десятиразрядный код 2¹⁰. Разрешающая способность принята в 10 мкВ, диапазон кодирования линейкой 0-0,01024 В. Преобразование в код сигналов, превышающих 2¹⁰, выполняют дешифратор 72, второй дешифратор 74, делитель 60 напряжения и блок 61 ключей. С их применением диапазон кодирования составляет 0-0,65536 В, т.е. 2¹⁶. За время одной строки шифратор 73 выдает четыре кода, поступающих в блок 77 регистров, включающий четыре регистра по 16 разрядов. В процессе поступления коды сдвигаются из регистра в регистр импульсами U_СД сдвига. Затем коды друг за другом выдаются в формирователь 36 /37/ в моменты дискретных импульсов 496 /отсчеты 991/992/, 497 /отсчеты 993/994/, 498 и 499 /отсчеты 997/998/, фиг. 6. Сигналы выдачи формируют счетчик 75 импульсов и третий дешифратор 76. Счетчик 75 девятиразрядный ведет счет импульсов 6,875 МГц, цикл счета 500 импульсов, обнуляется передним фронтом импульса частоты строк 13,75 кГц в момент 550-го импульса дискретизации /отсчеты 999/1000/.The conversion time consists of the response time of the photodiode 10 ns plus the response of the encoder 20 ns, in the amount of 30 ns or 33 • 10 ⁶ prev / s, satisfying 13.75 MHz sampling. Codes with ADC 29 enter the first generator 36 codes, codes with ADC 30 enter the second generator 37 codes, codes with ADC 31 enter the third generator 38 codes with a frequency of 13.75 MHz. The speed of creating information by each ADC is

The ADC 32, 33 converts two audio signals into sixteen-bit codes. During one line, each ADC generates four codes, the sampling frequency is 55 kHz / 13.75 kHz • 4 /. The sampling pulses arrive as signals to the radiation of the LED 68/4 /. The line 71 multi-element photodetector contains 1024 photodetector and converts the audio signal into a ten-digit code 2 ¹⁰ . The resolution is adopted at 10 μV, the coding range is 0-0.01024 V. The conversion of signals exceeding 2 ¹⁰ into a code is performed by a decoder 72, a second decoder 74, a voltage divider 60, and a key block 61. With their application, the coding range is 0-0.65536 V, i.e. 2 ¹⁶ . During the time of one line, the encoder 73 provides four codes entering the block 77 of the registers, including four registers of 16 bits. In the process of receipt, the codes are shifted from register to register by pulses U _SD shift. Then the codes are transmitted one after another to the driver 36/37 / at the moments of discrete pulses 496 / samples 991/992 /, 497 / samples 993/994 /, 498 and 499 / samples 997/998 /, FIG. 6. The output signals form a counter of 75 pulses and a third decoder 76. A counter of 75 nine-bit counts 6.875 MHz pulses, a cycle of counting 500 pulses, is reset by the leading edge of the pulse of the line frequency of 13.75 kHz at the time of the 550th sampling pulse / samples 999/1000 / .

The first generator 36 codes generates signal codes E _{R /} Fig. 8/ from 1 to 988, four codes of the first audio signal 991, 993, 995, 997, the code of the horizontal sync pulse is the 999th count, and with the last line of the frame, the code of the frame sync pulse is the 1000th row report. Only 500 pairs of codes. The second code generator 37 generates the video signal codes E _{G /} Fig. 8/ from 1 to 988, four codes of the second audio signal 991, 993, 995, 997, the horizontal sync pulse code is the 999th count, and the frame sync pulse code is the 1000th frame in the last line of the frame line count. Only 500 pairs of codes. The third code generator 38 generates the video signal codes E _{B /} Fig. 7/ from 1 to 998, there are no sound codes, the horizontal sync pulse code is the 999th sample and the CSI code in the last line of the frame is the 1000th sample of the line. Only 500 pairs of codes.

 The operation of the shaper 36/37 / codes / Fig. 8/.

Codes from the encoder 59 of the ADC 29 / Е _R / arrive at a frequency of 13.75 MHz at the first information input of the code generator — the inputs of the switching unit 86 in parallel. From the output of block 86, the codes in parallel form are alternately fed to the first inputs of the block of 87 I elements and the block of 92 elements I. The second inputs of these blocks receive pulses from their self-propelled distributors of 91.96 pulses, each with eight bits and made according to the scheme [7, c. 274]. From the outputs of the AND elements, the pulses of the codes already arrive sequentially on the first 88 / third 93 /, second 89 / fourth 94 / OR elements. From the elements OR 89, 94 pulses are fed to the control inputs of the output keys 90, 95, opening them for a duration of 18.18 ns. An open output switch 90 passes one positive half-wave of a 55 MHz monofrequency sine wave, output switch 95 passes one negative half-wave of a 55 MHz mono-frequency sine wave. At the output of the shaper 36/37 / codes, the units in the codes were represented by pulses, at the output of the shaper units in the codes of odd samples are represented by positive half-sine waves, in codes of even samples represented by negative half-sines. Zeros appear to be the absence of both. Timing diagrams of the operation of the formers are shown in FIG. 16. The outputs of the output keys 90, 95 are combined and are the output of the driver 36/37 /. The output signal is represented by full and incomplete sinusoids of the 55 MHz monofrequency with a stability of 10 ^-7 , which are modulating signals for the carrier frequency in the first 43 and second 45 shapers of the single-band counter / Fig. 1/. The time 495 of the sampling pulse / samples 989/990 / is used to switch keys 103, 104.

The sound code is divided into two packages: the first half of the code is from 1 to 8 bits through the block of 97 AND elements and the fifth element of OR 98 is fed to the second input of the second element OR 89 and fed to the control input of the output key 90, the second half of the code (bits from 9 to 16) enters from block 100 through the sixth 101th element OR to the second input of the fourth element OR 94, from it to the control input of the second output key 95. In the sound code, the units of bits 1 to 8 are represented by positive half-sine waves, bits from 9 to 16 - negative half-sine / Fig. 6/. The keys 103, 104 are designed to separate the codes of the video signals from the sound codes. The key 103 is opened from the first output of the decoder 106 at the time of resetting the counter 105 and remains open for 989 counts, with the signal from the second output of the decoder 106, the key 103 is closed, the key 104 is opened, which, after passing four sound codes, is closed by the signal from the first output of the decoder 106/999 /. Counting cycle with a counter of 105,500 pulses with a frequency of 6.875 MHz. The horizontal sync pulse code forms a self-propelled distributor of 39 pulses, which is fed to the third input of the second 89 OR element, the 999th line count. The start signal U _p for the distributor 39 is the pulse from the third output of the decoder 106, which appears at the moment 499 of the sampling pulse / 997 counting /. The frame sync pulse code forms a self-propelled pulse distributor 40, which is fed to the third input of the fourth 94 OR element, the 1000th row count. In the shaper 37 codes, the decoder 106 does not have a third output, therefore, the shaper 37 does not have a second output.

 The operation of the shaper 38 codes / 7 /.

Codes from the encoder 59 ADC 31 / signal E _B / arrive at a frequency of 13.75 MHz at the first information input - the inputs of the switching unit 108 in parallel. Further, the operation of the driver 38 is similar to the operation of the driver 36 codes, but it does not receive sound codes. The switching unit is designed to split the code stream at 13.75 MHz into two at 6.875 MHz. The alternate connection of the outputs of block 108 to the inputs of blocks of 109 AND elements is performed by control signals from trigger 107, to the input of which 13.75 MHz pulses are received. The output signal from the shaper 38 codes represents the full and incomplete sinusoids of the monofrequency 55 MHz, which is the modulating signal of the second carrier frequency in the shaper 48 of a single-band signal.

The first carrier frequency of 550 MHz is supplied to the input of amplifier 42 from the eighth output of the frequency synthesizer 35 to the transmitter 41; the second carrier frequency of 660 MHz is supplied to the input of amplifier 47 from the ninth output of block 35. From the output of block 42, the first carrier frequency is supplied to the first inputs of the formers 43 and 45 single-band signals. In the first driver 43 of a single-band signal, the carrier frequency is suppressed and the lower side frequency of 495 MHz / 550-55 / is filtered. The upper modulated lateral frequency of 605 MHz is amplified in block 44 and is transmitted into the air, occupying the band with oscillator stability 34 at 10 ^-7 ± 60.5 Hz or 121 Hz. The second carrier frequency is suppressed in the second single-band signal generator 45, the upper side frequency is filtered out, the modulated lower side frequency of 495 MHz is amplified by the output amplifier 46 and radiated into the air, occupying the band of ± 49.5 Hz or 99 Hz. In the third single-band signal driver 48, a second carrier frequency of 660 MHz is suppressed, a lower side frequency is filtered out, and a modulated upper side frequency of 715 MHz is amplified and radiated, occupying a band of ± 71.5 Hz or 143 Hz. The occupied band in the amount of 363 Hz. The spectra of the output signals are shown in Fig. 15.

 Three radio signals are received by the radio signal receiving units 117, 128, 139, which are selectors of the decimeter band / ACS / with electronic tuning, and perform radio signal reception in the range of 495-790 MHz. Each represents the first half of SKD-24 [8, p.132] and includes an input circuit, a radio frequency amplifier, and a mixer / transistor VT2 is used from the frequency converter [8, Fig. 4.2] /. The band-pass filter of the radio frequency amplifier in each range is tuned by applying bias voltage to the varicaps from the electronic switch of the touch control unit 116, which is the program selection unit, for example, USU-I-15 [8, p. 86]. The amplified radio frequency signal through the communication loop L11 [8, p. 132] is fed to the mixer emitter / transistor VT2 /, and here / to the mixer emitter / from the frequency synthesizer 151, the corresponding carrier frequency is needed to detect a single-band signal [9, p. 146] / carrier frequency of the included program /. The local oscillator circuit and the IF filter, available in SKD-24 [8, Fig. 4.2], are not needed.

 The signal from the VT2 collector, which is the output signal of the block 117 / 128,139 /, is fed to the input of the amplifier 118/129, 140 / of the radio frequency, where it is amplified to the required value and fed to the input of the bipolar amplitude detector 119/130, 141 /. The second inputs of the frequency synthesizer 151 are connected to the second group of outputs of the block 116 / after the diodes VD11-VD18 [8, p. 86] /. When you turn on the program guide, the voltage from the corresponding diode determines the output of two frequencies to the third inputs of blocks 117, 128 / first frequency /, 139 / second frequency /. With the transition to another program of transmissions to the third inputs of blocks 117, 128, 139, sinusoidal oscillations of two other corresponding frequencies will arrive, equal in frequency to the carriers of the transmitter of the transmitting side.

 Bipolar amplitude detectors 119, 130, 140 are made / Fig. 10/ according to the scheme [10, p. 112]. The diode D1 selects the positive envelope of the modulating sinusoidal signal of Fig.16. The diode D2 from the modulator selects the envelope of the positive half-sine wave / symbols of units of odd samples /, the diode D3 from the modulating selects the envelope of the negative half-sinusoid / symbols of units of even samples /. From the first output of the bipolar amplitude detector, the detected half-sine waves with a frequency of 55 MHz are fed to the input of the first driver 120/131, 142 / pulses, from the second output, the detected negative half-sine waves of 55 MHz are fed to the input of the second driver 121/132, 143 / pulses. Shapers 120, 121, 131, 132, 142, 143 pulses made according to the scheme of an asymmetric trigger with emitter coupling [11, p. 209], forming rectangular pulses from harmonically varying signals. The pulses from the formers have one polarity and a duration equal to the pulse duration in the codes on the transmitting side. Units in codes are represented by the presence of an impulse, zeros by their absence. After turning on the power, the keys of the receiving side are in the closed state.

The order of operation of the receiving side is determined by the control signals generated by the channel for generating control signals. The decisive role is played by the block 150 for extracting the horizontal sync pulse, the condition for issuing the SSI is the simultaneous arrival from three formers 120, 131, 142 pulses of codes from eight units 11111111 to the inputs of block 150. In all codes of the line, except for the 999th, one or more will always be present zeros, especially at the same time in the codes of three lines. For each zero in the code, the elements NOT / 11/11 will reset the counters in block 150. With the arrival of three codes 11111111, block 150 generates a pulse at the output, which is a 13.75 kHz SSI pulse. The SSI opens the key 153, enters the input of the frame scanning unit 178 and the first input of the frequency synthesizer 151, being a frequency synchronization pulse in the frequency synthesizer 151. Own frequency stability of the synthesizer 151 frequencies 10 ^-6 .

The frequency of the synthesizer 151 frequencies is adjusted for the frequency and phase of the master oscillator 34 of the transmitting side along the leading edge of the SSI from block 150. The frequency synthesizer 151 generates 6.875 MHz sampling pulses from the first output, 55 kHz sound sampling pulses from the second output, from the third and fourth outputs sinusoidal oscillations required first and second carrier frequencies from the fifth output pulses of 13.75 MHz for the blocks 124, 135, 146 processing codes, with the sixth output pulses of 27.5 MHz / U _vyd / to the adders 126, 137, 148 and blocks 125, 136, 147. Impu 6.875 MHz frequencies for the 152 self-propelled pulse distributor are trigger U _p signals. The self-propelled distributor 152 generates a clock frequency of 55 MHz, multiplying the frequency of 6.875 MHz by 8. The video signal codes E _R from the output of the first pulse shaper 120 are fed in series to the input of the first register 122 of the video signal E _R , filling in the bits of which take a parallel form, and in parallel form give a pulse U _iss 6.875 MHz to the first inputs of the block 124 code processing. The video signal codes E _R from the output of the second pulse shaper 121 are fed to the input of the second register 123 of the video signal E _R , fill in the bits and acquire a parallel form. In parallel, the code from register 123 is issued by a pulse U _{output of} 6.875 MHz to the second inputs of the code processing unit 124.

Block 124/135, 146 / doubles the code repetition rate from 13.75 MHz to 27.5 MHz by obtaining intermediate / middle / codes between each transmitted code and the next one. Block 124/135, 146 / performs the addition of two / previous and subsequent / codes and dividing the amount in half. From the output of block 124/135, 146 / codes E _R / Е _G , E _B / are followed with a frequency of 27.5 MHz to block 125/136, 147 / of delay elements, adder 126, / 137, 148 / and to block 127 / 138, 149 / delay elements. Block 125/136, 147 / delays each code by a line duration of 72.72 μs. The first inputs of adder 126 receive the code of the current line from block 124, the second inputs receive the code of the same line count after a delay of 72.72 μs by block 125, i.e. past line. The adder 126/137, 148 / adds the codes, the amount is divided in half by the corresponding connection of the outputs of the adder and the inputs of the block 166 pulse amplifiers.

Each code received is an intermediate line code. Thus, adders 126, 137, 148 double the lines, forming another 550 lines with the number of 2000 samples in each. Codes of the current line from blocks 127, 138, 149 delay elements are received at the inputs of blocks 165, 167, 169 pulse amplifiers. Since the adder delays the code during addition by 24 ns, the blocks 127, 138, 149 delay the codes for exactly the same 24 ns so that the codes from the adders 126, 137, 148 and from the delay blocks 127, 138, 149 synchronously arrive at the inputs of the pulse blocks Amplifiers 165-170. The video signal codes E _G from the first driver 131 of the pulses arrive in the first register 133 of the video signal E _G , the codes from the second driver 132 come in the second register 134 of the video signal E _G and are issued from them in parallel by the signals U _vy 6.875 MHz to the code processing unit 135. The further process is similar to the process of processing E _R codes. The video signal codes E _B from the first pulse shaper 142 and from the second pulse shaper 143 are supplied to the first 144 and second 145 video signal registers Е _B , converted into parallel codes and issued by the signals U _output to the inputs of the code processing unit 146. The further process is similar to the process of processing E _R codes. Codes of the current lines of the signal E _G arrive through the block 138 of the delay elements in the block 167 of the pulse amplifiers, the codes of the intermediate lines are received from the adder 137 in the block 168 of the pulse amplifiers. Codes of the current row signal _E fed through unit delay element 149 to block 169 of pulse amplifiers, intermediate rows codes received from the adder 148 to block 170 of pulse amplifiers. The signals from blocks 165, 167, 169 pulse amplifiers are fed to the inputs of the first emitter 213 of three primary colors in block 171 / FIG. 14/, the beam of which reproduces 550 lines encoded and transmitted from the transmitting side. The signals from blocks 166,168, 170 pulse amplifiers are fed to the inputs of the second emitter 214 of three primary colors in block 171, the beam of which reproduces 550 intermediate lines. The playback frame is 1100 active lines with 2000 samples in each.

 The operation of the block 124/135, 146 / code processing / Fig.12/.

Разряд 0 означает перенос при сумме кодов. Процесс получения промежуточного кода /среднего/ поясняется фиг.12. При удвоении частоты следования кодов в 27,5 МГц период их следования составляет 36,36 нс. Процесс сложения занимает 24 нс, следовательно, блок 196 должен выдержать код еще на 12,36 нс. По истечении 36,36 нс с блока 196 на выход поступает код 1

Следующий код 2 идет через 36,36 нс с регистра 195, это код "0_к, который был выдан с регистра 190 в регистр 195, а из регистра 195 выдается сигналом U_выд2.The odd codes from the first register 122 through the block 192 delay elements / 10 ns / arrive in parallel to the registers 188, 189. The even codes from the second register 123 through the block 194 delay elements / 82.72 ns / go in parallel to the registers 190, 191. Each code it is used twice: the first time as the previous one, the second time as the next, so block 124 has four registers 188, 189, 190, 191. With the arrival of the first 13.75 MHz pulse to the input of the trigger 187, the pulse U _vy1 from the first output of the trigger simultaneously outputs register 189 code "0 _k and from register 190 code" 0 _k and resets them. The code from register 189 enters the first inputs of adder 197, the code from register 190 through diodes enters the second inputs of adder 197 and the inputs of register 195, which has eight bits and stores a code of 72.72 ns. 10 ns after issuing the code from the register 189, the registers 188, 189 are filled with the 1- _k code. Block 192 delays the code by 10 ns to prevent the incoming code from superimposing on the code issued from the registers 188, 189. The adder 197 performs the addition of codes as an adder K555IM6 microcircuits were used [6, p. 258] with an addition time of 24 ns. Upon completion of addition, the corresponding adder circuits are reset to U _{0 by a} pulse of 13.75 MHz, it issues the sum code to block 196. Code division is performed by shifting the sum code by one bit so, that the least significant bit of the sum code is discarded. g per discharge is performed by the corresponding connection of the outputs of the adder 197 to the inputs of block 196:

Digit 0 means carry with the sum of codes. The process of obtaining the intermediate code / middle / is illustrated in Fig.12. When doubling the repetition rate of codes in 27.5 MHz, the repetition period is 36.36 ns. The addition process takes 24 ns, therefore, block 196 must withstand the code for another 12.36 ns. After 36.36 ns, code 1 is output from block 196

The following code 2 goes through 36.36 ns from register 195, this is the code "0 _k , which was issued from register 190 to register 195, and from register 195 it is issued by a signal U _iss2 .

Через 10 нс после выдачи кода регистры 190, 191 заполняются кодом "2_к". Сумматор формирует код 3

выдаваемый с блока 196. Через 36,36 нс с регистра 193 сигналом U_выд1 выдается код 4 "1_к. С приходом 3-го импульса в триггер 187 сигнал U_выд3 с первого выхода триггера выдает с регистра 190 код "2_к" и из регистра 189 код "1_к. Через 10 нс следует заполнение регистров 188, 189 кодом "3_к". Сумматор формирует код 5

выдаваемый с блока 196, через 36,36 нс за ним выдается сигналом U_выд2 код 6 "2_к" из регистра 195. Блок 194 элементов задержек производит задержку кода на 82,72 нс: 72,72 нс воспроизводят следование четных кодов за нечетными и 10 нс для исключения наложения поступающего кода на выдаваемый из регистра 191. С приходом 4-го импульса в триггер 187 сигнал U_выд4 со второго выхода триггера выдает из регистра 188 код "3_к", из регистра 191 код "2_к". Через 10 нс следует заполнение регистров 190, 191 кодом "4_к". Сумматор 197 формирует код 7

который выдается с блока 196.Register 195 stores a code of 72.72 ns, with half of the delay 36, 36 ns occurring at the time of addition of the codes 24 ns plus a delay in block 196 of 12.36 ns. With the arrival of the 2nd pulse at the input of trigger 187, the pulse U _vy2 from the second output of the trigger gives code 2 from register 195, from code 188 a 1- _k code, which through diodes goes to the inputs of adder 197 and to the inputs of register 193, which stores code 72, 72 ns. The signal U _vyd2 generates from the register 191 the code "0 _k to the adder 197. Addition, division of the amount in half

10 ns after the issuance of the code, the registers 190, 191 are filled with the “2 _k ” code. The adder generates code 3

issued from block 196. After 36.36 ns from register 193, the signal U _{vyd1 gives} a code 4 "1 _k . With the arrival of the third pulse in trigger 187, the signal U _vyd3 from the first output of the trigger gives a code" 2 _k "from register 190 and from register 189 code "1 _to . After 10 ns, the registers 188, 189 should be filled with the “3 _k ” code. The adder generates code 5

issued from block 196, after 36.36 ns, it is followed by a signal U _vy2 code 6 "2 _k " from register 195. Block 194 delay elements produces a delay code 82.72 ns: 72.72 ns follow the sequence of even codes for odd and 10 ns to prevent overlapping of the incoming code issued from the register 191. With the arrival of the 4th pulse in the trigger 187, the signal U _iss4 from the second output of the trigger generates a 3- _k code from register 188, a 2- _k code from register 191. After 10 ns, the registers 190, 191 should be filled with the “4 _k ” code. Adder 197 generates code 7

which is issued from block 196.

выдаваемый с блока 196. Через 36,36 нс с регистра 195 выдается код 10 "4_к". Далее эти процессы повторяются.From register 193 issued code 8 "3 _to ". With the arrival of the 5th pulse in the trigger 187, the signal U _vyd5 from the first output of the trigger generates a “5 _k ” code from the register 189. The adder generates code 9

issued from block 196. After 36.36 ns from register 195, code 10 "4 _k " is issued. Further, these processes are repeated.

 The operation of the block 125/136, 147 / delay elements / Fig.17/.

With the arrival of the frame CSI and horizontal SSI of the clock pulses, the signal of the I216 element opens the key 217, which transmits 27.5 MHz clock pulses to the pulse distributor 219. From the distributor 219 pulses are sequentially supplied to the clock / first / inputs from the 1st to the 2000th bits of eight registers 221 ₁ -221 ₈ . Signals of the first line from block 124/135, 146 / are received at 1-8 information inputs of block 125: the signals of the first category of codes are fed to the second inputs of the bits of the first register 221 _{1, the} signals of the second bit of codes are fed to the second inputs of the bits of the second register 221 ₂ etc., the signals of the eighth digit of the codes are fed to the second inputs of the bits of the eighth register 221 ₈ . At the end of the first line, all 2000 bits of eight registers are filled with signals of 2000 codes of the 1st line. In the next 72.72 μs, 2000 codes from these eight registers 221 _1-8 are output to the adder 126/137, 148 / with the simultaneous filling of the register bits with signals of 2000 codes of the next / third / line. Due to the fact that the scan of 3 lines goes counter to the 1st line / Fig. 2 /, the beginning of the 3rd line is located against the end of the 1st line; codes from the registers 221 _{1-8 are} issued in the reverse order: not from the 1st category of the registers, but from the 2000th category. This is done by the second pulse distributor 220, the outputs of which are connected to the clock inputs of the bits of the registers 221 _1-8 in the reverse order: the first output of the distributor 220 is connected to the 2000th bits of the registers, and the 2000th output is connected to the first bits of the registers 221. With a scan of 5 lines, codes are issued from registers 221 _1-8 by the distributor 219, starting from the first bits of the registers; when scanning 7 lines, codes are issued by the distributor 220, starting from the last bits of the registers. Further, these processes, alternating, are repeated.

 Thus, the first inputs of the adder 126/137, 148 / receive the code of the current line from block 124, the second inputs of the adder receive a delayed code of the same count, but of the previous line, after delaying it in block 125/136, 147 / by 72, 72 μs. Adders 126, 137, 148 are identical, represented by K555IM6 microcircuits, add codes of the same samples of the previous and subsequent lines, divide the sum code in half by connecting the outputs of the adder and the inputs of the pulse amplifier 166, 168, 170 as described on page. 28. The blocks of pulse amplifiers are represented by 533AP6 microcircuits with a response time of 18 ns [6, p. 128].

The radiation modulation unit 171 performs luminance modulation of the three colors R, G, B of two lines at the same time according to the values of the video signal codes. The first emitter 213 modulated in brightness beam reproduces 550 lines encoded and transmitted from the transmitting side. The second emitter 214 modulates the brightness of the beam reproduces 550 intermediate lines, the sample codes of which were obtained by adders 126, 137, 148. The reproduced frame is 110 active lines with 2000 samples in a line, which corresponds to 2.2 • 10 ⁶ resolution elements in the frame. Key 153 is opened by SSI pulses, a nine-digit counter 154 pulses counts 6.875 MHz discrete pulses, and a cycle of counting 500 pulses. With the arrival of 495 pulses, the decoder 155 decodes the binary code of the 495th pulse and generates a signal U _{from the} first output, opening the keys 157, 159 in the first and second sound channels, passing four sound codes during 496, 497, 498, 499 discrete pulses . Time 495 pulse goes to the opening of the keys. Sound codes are received in blocks 158, 160 sound registers, each of which includes four eight-bit register. The registers are filled up as codes are received, and issued by signals U _output 55 kHz from the 2nd output of block 151 to the DAC 161, which converts the codes into analog signals passing through a low-pass filter 162, amplified in a power amplifier 163 and reproduced by loudspeakers 164. With the arrival of into the counter 154 of the 499th pulse, the decoder 155 by the signal U ₃ from the second output closes the keys 157, 159, resets the counter 154 and closes the key 153.

 The emitters 213, 214 include each LEDs of red radiation 12 pcs, green radiation 12 pcs, blue radiation 12 pcs type NLMP, manufactured by Hewlett-Packard company [12, p. 71].

 The distribution of LEDs of the same color by the weight of the discharges is presented in table. 2.

 The emitting windows of the LEDs are located in the rear focal plane of the optical system 215. The total emission of the three-color LEDs in the emitter is mixed by the optical system 215 when focusing in two color spots on the reflector of the first piezoelectric deflector 175. For red radiation, LEDs НL MP-AL00 with a light intensity of 400 mcd are adopted, a wavelength of 0.59 μm at a current of 0.02 A. For green radiation, LEDs HL MP-AM00 with a light intensity of 800 μd are accepted, a wavelength of 0.526 μm and a current of 0.02 A. For blue radiation, LEDs HL MP-AB00 with light intensity 300 mcd, a wavelength of 0.475 μm and a current of 0.02 A. The brightness modulation is performed by switching on the LEDs according to the discharge weight according to Table 2.

где в числителе суммарная сила света от одного излучателя,
причем принято, что красный, зеленый и синий светодиоды имеют силу света синего светодиода /300 мкд/;

- коэффициент двоичного кода в 4, 5, 6, 7, 8 разрядах;
0,5•10^-6 м² - площадь разрешающего элемента на экране.The brightness, saturation and hue of the resulting color on the screen are determined by the total energy and the mutual ratio of the three colors R, G, B from each emitter. The resolving element on the screen in the line is 0.5 mm ² / 0.7 x 0.7 mm /. The maximum instantaneous brightness of the resolution element on the screen without taking into account projection losses is

where in the numerator the total light intensity from one emitter,
moreover, it is assumed that the red, green and blue LEDs have a blue light intensity of 300 LED /;

- coefficient of the binary code in 4, 5, 6, 7, 8 bits;
0,5 • 10 ^-6 m ² - the area of the resolving element on the screen.

 The red light equalization / 400 mcd / is performed by attenuating light filters / it is also possible by the number of LEDs /.

The maximum brightness of the resolution element on the screen, taking into account losses during projection to the screen of 50%, is 7172875 cd / m2 ^, which will be enough to create a bright color image on the screen. And since the sweep goes simultaneously with two beams, the average brightness will be twice as large. The piezoelectric deflector 175, according to the control voltage of the amplifier 174, performs an urgent scan of two beams on the reflector of the second piezoelectric deflector 183, performing a frame scan along with a lower case on the screen 186. The LEDs of one emitter consume
36 _pcs • / 5 V • 0.02 A / = 3.6 VA
Two emitters consume 7.2 VA. The piezoelectric deflectors are controlled by control voltages from the horizontal scanning unit 173 and the vertical scanning unit 178. Horizontal scan voltage has a triangular isosceles shape with a frequency of 6.875 kHz. An amplifier 174 amplifies the voltage and drives the piezoelectric deflector 175 with a line frequency of 13.75 kHz. The piezoelectric deflector 183 oscillates at a frequency of 25 Hz. The summing amplifier 181 is identical to the transmitting side amplifier 17. The width of the reflective strip of the piezoelectric deflector 183 0.04 mm, length 40 mm: 0.02 mm x 2000. The beginning of the frame scan is determined by the moment of coincidence of the leading edges of the horizontal and vertical sync pulses at the input of the And 179. The summing amplifier 181 produces a step-wise linearly increasing voltage / Fig. 2 / for one field of the frame and a stepwise decreasing voltage for another field of the frame. The condition for the block 156 to issue a frame clock is the simultaneous arrival at the inputs of block 156 (Fig. 9/) of three codes 11111111 from the outputs of the second pulse shapers 121, 132, 143.

System operation
From photodetectors 23, 24, 25, three analog video signals E _R , E _G , E _B after amplification by preliminary amplifiers are fed to the ADC inputs 29, 30, 31. Two sound signals are fed to the ADC inputs 32, 33. The video signals are converted into eight-digit codes with sampling 13.75 MHz. Sound signals are converted to sixteen-digit codes with a sampling rate of 55 kHz. Shapers 36, 37, 38 codes form consecutive codes from parallel codes and replace the representation of units from pulses with half-sinusoids of the 55 MHz monofrequency in them. The clock frequency in the system is 55 MHz. The data transfer speed is 330 Mbps. On the transmitting side, the video signals E _R , E _G , E _{B of} 550 lines are encoded in 1000 samples per line. Information of codes E _R is transmitted by the upper and side frequency of 605 MHz from the first carrier of 550 MHz, information of codes E _G is transmitted by the lower side frequency of 495 MHz of the same carrier, information of codes E _B is transmitted by the upper side frequency of 715 MHz to the second carrier of 660 MHz. The occupied frequency band along three channels is 363 Hz. The receiving side receives three radio signals in parallel, performs radio frequency amplification, bipolar amplitude detection, extracts horizontal and frame sync pulses, restores both carrier frequencies, doubles the code repetition rate to 27.5 MHz by obtaining intermediate samples in each line and doubles the lines in the raster / 1100 / obtaining samples of 550 intermediate lines. Block 171 modulation of radiation, respectively, codes of two lines produces radiation of two emitters 213, 214 of 36 LEDs each. Piezoelectric deflectors 175, 183 scan two lines of a color image on a matte screen 186.

 The volume of reproduced information is 1320 Mbit / s.

 The technical and economic effect of the claimed system consists in increasing the resolution of the reproduced image by 4 times against the prototype. The system can be applicable for digital broadcasting on existing terrestrial TV networks in the UHF band allocated for analog television, as well as on satellite communication lines.

Sources of information
1. Patent 2128890, cl. H 04 N 11/04, bull. 10 for 1999, analogue.

 2. Patent 2165681, cl. H 04 N 11/04, bull. 11 2001, prototype.

 3. Samoilov V.F., Lame B.P., "Television", M., 1975, p. 46.

 4. Radio transmitting devices. M.S. Shumilin et al., 1981, M., p. 234.

 5. Fridland M.V., Soshnikov V.G. "Automatic control systems in video recording devices", M., 1988, p.118 fig.5.5, p.122, fig.5.10.

 6. Digital integrated circuits, Minsk, 1991, S. 128, 231, 258.

 7. Ilyin V.A. "Remote control and telemetry", M, 1982, S. 269, 274.

 8. Brodsky M.A. “Color television sets”, Minsk, 1988, p. 86, fig. 2.55, p. 132, fig. 4.2.

 9. Radio communications, broadcasting, television, ed. HELL. Fortushenko, M., 1981, p. 146.

 10. Handbook of Broadcasting, ed. A.V. Coming, Kiev, 1981, p. 112, Fig. 81.

 11. Barkan V.F., Zhdanov V.K. "Amplification and pulse technology", M., 1981, p.209.

 12. Radio, 7, 1998, p. 71.

Claims (1)

A digital high-definition television system containing a transmitting side including a photoelectric converter, first, second and third analog-to-digital converters (ADCs), the inputs of which are connected to the corresponding outputs of the photoelectric converter, a fourth and fifth ADCs, to the information inputs of which sound signals are supplied, serially connected sine oscillation generator and frequency synthesizer, first and second code generators, first and second information inputs of the first the code generator is connected to the outputs of the first and fourth ADCs, the first and second information inputs of the second code generator are connected to the outputs of the second and fifth ADCs, the first and second self-propelled pulse distributors, the outputs of the first self-propelled pulse distributor are combined and connected to the third information inputs of the first and second code generators , the input of the second self-propelled pulse distributor is connected to the sixth output of the frequency synthesizer, its outputs are combined and connected to the fourth information the inputs of the first and second code generators, the first output of the frequency synthesizer is connected to the clock input of the second ADC and the first control input of the second code generator, the second output of the frequency synthesizer is connected to the second control inputs of the first and second code generators and the first control inputs of the fourth and fifth ADCs, the third output the frequency synthesizer is connected to the second control inputs of the fourth and fifth ADCs, the fourth output of the frequency synthesizer is connected to the third control inputs of the first and second form code generator, the fifth output of the frequency synthesizer is connected to the fourth control inputs of the first and second code generators and the third control inputs of the fourth and fifth ADCs, a radio signal transmitter containing the first and second channels, each of which includes a serially connected single-band signal shaper and an output amplifier, second inputs shapers of single-band signals are connected respectively to the outputs of the first and second shapers of codes, each shaper of a single-band signal includes connected annularly with a ring modulator and a band-pass filter, the photoelectric transducer comprises a lens, a first piezoelectric deflector with an end face located in the focal plane of the lens, a second piezoelectric deflector with an end face reflector optically coupled to a first piezoelectric reflector, and a horizontal scanning unit connected in series to the input the seventh output of the frequency synthesizer, and the first amplifier, the output of which is connected to the first input of the first piezoelectric deflector, the first source a positive reference voltage, the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector, a second source of negative reference voltage, the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector, connected in series to the vertical scan unit, the first and second inputs of which are connected respectively to the fifth and the sixth outputs of the frequency synthesizer, and the second amplifier, the output of which is connected to the first input of the second piezoelectric deflector, the third source of positive the reference voltage, the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector, the fourth source of the negative reference voltage, the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector, the first and second dichroic mirrors located one after the other and against the reflector of the second piezoelectric deflector, three a micro lens, three photodetectors, three pre-amplifiers, the outputs of which are the outputs of the photoelectric converter, the input window of the first photodetector about optically connected through the first micro lens and the first dichroic mirror to the reflector of the second piezoelectric deflector, the input window of the second photodetector is optically connected through the second micro lens and through both dichroic mirrors to the reflector of the second piezoelectric reflector, the input window of the third photodetector is optically connected through the third micro lens, the second dichroic mirror and through the first a mirror with a reflector of the second piezoelectric deflector, the frame scanning unit of the photoelectric transducer contains a follower but the connected element And, the master oscillator and the summing amplifier, the second input of which is connected to the first input of the And element, the control input of the summing amplifier is connected to the output of the And element, the first, second and third ADCs are identical and each is made of a series-connected amplifier and a piezoelectric reflector with a reflector on end of the first source of positive reference voltage, the output of which is connected to the second inputs of the amplifier and piezoelectric deflector, the second source of negative reference voltage, the output of which is connected is connected to the third inputs of the amplifier and the piezoelectric deflector, the emitter from the pulsed LED, the slit aperture, and the micro lens, the array of the multi-element photodetector and encoder, the input of the array of the multi-element photodetector is optically connected to the reflector of the piezo-reflector ADC, and its outputs are connected to the inputs of the encoder, the outputs are the outputs the control input is the pulse LED input, the fourth and fifth ADCs are identical and each contains a series-connected voltage divider, a block of keys, matching the first amplifier, amplifier and piezoelectric deflector with a reflector at the end, the first source of positive reference voltage, the output of which is connected to the second inputs of the amplifier and the piezoelectric deflector, the second source of negative reference voltage, the output of which is connected to the third inputs of the amplifier and the piezoelectric deflector, emitter from a pulsed LED, slit diaphragm and a micro lens, a line of a multi-element photodetector, the input of which is optically connected to the piezoelectric reflector, and the first decoder is connected in series to the odes of which are connected to the corresponding outputs of the multi-element photodetector line, the encoder and the second decoder, the outputs of which are connected to the corresponding inputs of the first decoder and the inputs of the key block, contain a pulse counter, the third decoder and the register block connected in series, the other inputs of which are connected to the encoder outputs and its first the control inputs are connected to the outputs of the third decoder, the input of the ADC is the input of the voltage divider, the first control input is the counting input of the counter pulses, the second is the combined input of the pulsed LED and the control input of the register block, the third is the control input of the pulse counter, the output is the output of the register block, the first and second code generators are identical and each contains a trigger and switching unit and four channels connected in series, the inputs of the first and the second channels are connected to the corresponding outputs of the switching unit, and the outputs of the four channels are combined, the first channel includes the first block of AND elements connected in series, the first and second electric OR elements and a first output key, and a first self-propelled pulse distributor, the second channel includes a second block of AND elements, a third and fourth OR element and a second output key, and a second self-propelled pulse distributor, the first inputs of the first and second blocks of AND elements are connected to the corresponding the outputs of the switching unit, the second inputs of the first block of elements And are connected to the outputs of the first self-propelled pulse distributor, the second inputs of the second block of elements And are connected to the outputs of the second ca a mobile pulse distributor, the third channel includes a third block of AND elements and a fifth OR element, and a third self-propelled pulse distributor, the output of the fifth OR element is connected to the second input of the second OR element, the fourth channel includes a fourth block of AND elements and a sixth OR element, connected in series and the fourth self-propelled pulse distributor, the output of the sixth OR element is connected to the second input of the fourth OR element, the second inputs of the third and fourth blocks of AND elements are connected to the outputs of the third and fourth self-propelled pulse distributors, the first and second code generators include the first and second keys and series-connected pulse counter and decoder, two outputs of which are connected respectively to the first and second control inputs of the first and second keys, the output of the first key is connected to the inputs of the first and second self-propelled pulse distributors, the output of the second key is connected to the inputs of the third and fourth self-propelled pulse distributors, the output is shaped The code reader is the combined output of the output keys, the first and second information inputs are the inputs of the switching unit and the inputs of the third and fourth blocks of AND elements, the third and fourth information inputs are the third inputs of the second and fourth OR elements, respectively, the first control input is the trigger input, the second control the input is the combined input of the keys and the counting input of the pulse counter, the third control input is the combined input of the signal inputs of the output keys, four the control input is the pulse counter control input, and contains the receiving side, which includes the antenna, the sensor control unit, the first path for receiving and processing video codes, the second path for receiving and processing video codes, the inputs of which are connected to the antenna, and the second inputs are connected to the first outputs touch control unit, first, second, third blocks of pulse amplifiers, serially connected frequency divider, horizontal scanning unit, first amplifier and first piezoelectric deflector with a reflector and the end face, the first source of positive reference voltage, the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector, the second source of negative reference voltage, the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector, connected in series to the vertical scan unit, the second amplifier and the second piezoelectric deflector with a reflector at the end, the third source of positive reference voltage, the output of which is connected to the second inputs of the second amplifier and the second piezoelectric torus, a fourth source of negative reference voltage, the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector, a radiation modulation unit containing an optical system and an emitter of three primary colors, including the corresponding number of LEDs of each color and located in the rear focal plane of the optical system, and a matte screen located opposite the reflector of the second piezoelectric deflector, which is optically connected to the reflector of the first piezoelectric deflector, which is optically coupled the radiating side of the radiation modulation unit, the corresponding inputs of which are connected to the outputs of the first, second and third blocks of pulse amplifiers, the first path for receiving and processing video signal codes contains a series-connected radio signal receiving unit, the first input of which is connected to the antenna, the second inputs are connected to the first group of outputs of the block sensor control, radio frequency amplifier, bipolar amplitude detector and channel for processing video signal codes E _R including the first and second pulse shapers, the inputs of which are connected respectively to the first and second outputs of a bipolar amplitude detector, the first and second video signal registers E _R the information inputs of which are connected respectively to the output of the first and second pulse shapers, the second path for the reception and processing of video signal codes contains serially connected radio signal receiving unit, the first input of which is connected to the antenna, the second inputs are connected to the first group of outputs of the touch control unit, radio frequency amplifier, bipolar amplitude detector and video signal processing channel E _G including the first and second pulse shapers, the inputs of which are connected respectively to the first and second outputs of a bipolar amplitude detector, the first and second video signal registers E _G the information inputs of which are connected to the output of the first and second pulse shapers, the receiving side includes two sound channels, each of which contains the first key and the first block of sound registers, the second key and the second block of sound registers, and the digital-to-analog converter (DAC) connected in series, the inputs of which are connected to the outputs of the first and second blocks of sound registers, a low-pass filter, a power amplifier and a loudspeaker, the receiving side includes a channel f control signal generator, comprising a horizontal sync pulse allocation unit, a self-propelled pulse distributor, a key, a pulse counter and a decoder connected in series, and a frame sync separation unit, the first and second inputs of a horizontal sync pulse allocation unit are connected to the outputs of the first pulse shapers in the first and second reception paths and processing of video signal codes, the first and second inputs of the frame sync pulse extraction unit are connected to the outputs of the second pulse shapers in the first ohm and the second path for receiving and processing video signal codes, the first control key input is connected to the output of the horizontal sync pulse allocation unit, the outputs of the self-propelled pulse distributor are combined and the combined output is connected to the clock inputs of the first and second video signal registers E _R , E _G and blocks of sound registers, the first output of the decoder is connected to the first control inputs of the first and second keys in the first and second sound channels, the second output of the decoder is connected in parallel to the second control inputs of the first and second keys in the first and second channels of sound, to the control input of the counter and the second control key input, the inputs of the frequency divider block and the first input of the vertical block are connected to the output of the horizontal sync pulse allocation block, the output of the cad selection block A new clock pulse is connected to the second input of the vertical scanning unit, which contains a series-connected element And, a master oscillator and a summing amplifier, the output of which is the output of the vertical scanning unit and is connected to the first input of the second amplifier, the second input of the summing amplifier is connected to the first input of the And element, controlling its input is connected to the output of the And element, the summing amplifiers in the personnel units of the receiving and transmitting sides are identical and each contains serially connected e pulse counter and decoder, first and second keys, first and second pulse shapers and output amplifier, signal inputs of the first and second keys and counting input of the pulse counter are combined and are the second input of the summing amplifier, the first input of which is the first input of the output amplifier, the first control the input of the first key, the second control input of the second key and the control input of the pulse counter are combined and are the control input of the summing amplifier, the second control input of the first key the first control input of the second key is combined and connected to the output of the decoder, the output of the first key is connected to the input of the first pulse shaper, the output of the second key is connected to the input of the second pulse shaper, the outputs of the first and second pulse shapers are combined and connected to the second input of the output amplifier, the output of which is the output of the summing amplifier, characterized in that on the transmitting side, the clock inputs of the first and third ADCs are connected to the first output of the frequency synthesizer, the first control the input input of the first code generator is connected to the first output of the frequency synthesizer, and its decoder has a third output, which is the second output of the first code generator, connected to the input of the first self-propelled pulse distributor, the third code generator is introduced, the first information input of which is connected to the output of the third ADC, the second and the third information inputs are connected respectively to the output of the first and second self-propelled pulse distributors, the first, second, third control inputs are connected respectively In relation to the first, second, and fourth outputs of the frequency synthesizer, the third code generator contains a serially connected trigger and a switching unit and two identical channels, each of which includes a series of AND elements, a first and second OR element, and an output switch, and a self-propelled pulse distributor, the first inputs of the blocks of elements And are connected to the corresponding outputs of the switching unit, the second inputs of the blocks of elements And are connected to the outputs of the self-propelled pulse distributor of their channel, the output s of the output keys are combined and are the output of the third code generator, the first information input is the inputs of the switching unit, the second and third information inputs are the second inputs of the second elements OR of the first and second channels, the first control input is the trigger input, the second control input is the combined input of self-propelled pulse distributors, the third control input is the combined signal inputs of the output keys, an amplifier is introduced into the first channel of the transmitter the first carrier frequency, the output of which is connected in parallel to the first inputs of the first and second formers of a single-band signal, the input of the amplifier of the first carrier frequency is connected to the eighth output of the frequency synthesizer, the third channel is introduced into the transmitter, including the second carrier frequency amplifier connected in series, the input of which is connected to the ninth output a frequency synthesizer, a third shaper of a single-band signal and an output amplifier, a second input of a shaper of a single-band signal is connected to the output of the third shaper Vatel codes on the reception side video codes E processing channel _R introduced in series connected block of code processing, the first block of delay elements and the adder, and the second block of delay elements, the first and second inputs of the block of code processing are connected to the outputs of the first and second video signal registers E _R , and its outputs are connected to the inputs of the first and second blocks of delay elements and to the second inputs of the adder, to the first inputs of which the outputs of the first block of delay elements are connected, into the channel for processing video signal codes E _G introduced in series connected block of code processing, the first block of delay elements and the adder, and the second block of delay elements, the first and second inputs of the block of code processing are connected to the outputs of the first and second video signal registers E _G and its outputs are connected to the inputs of the first and second blocks of delay elements and to the second inputs of the adder, to the first inputs of which the outputs of the first block of delay elements are connected, a third channel for receiving and processing video signal codes is introduced, containing a series-connected radio signal receiving unit, the first input of which is connected to the antenna, the second inputs are connected to the first group of outputs of the touch control unit, a radio frequency amplifier, a bipolar amplitude detector and a channel for processing video signal codes E _IN including the first and second pulse shapers, the inputs of which are connected respectively to the first and second outputs of a bipolar amplitude detector, the first and second video signal registers E _IN , the information inputs of which are connected respectively to the outputs of the first and second pulse shapers, sequentially connected code processing unit, the first block of delay elements and the adder, and the second block of delay elements, the first and second inputs of the code processing unit are connected to the outputs of the first and second video signal registers E _IN and its outputs are connected to the inputs of the first and second blocks of delay elements and to the second inputs of the adder, the first inputs of which are connected to the outputs of the first block of delay elements, clock inputs of the first and second registers of the video signal E _IN connected to the output of a self-propelled pulse distributor in the channel for generating control signals, into which a frequency synthesizer is inserted, the first input of which is connected to the output of the horizontal sync pulse allocation unit, its second inputs are connected to the second group of outputs of the touch control unit, the first output of the frequency synthesizer is connected to the input of the self-propelled distributor pulses and to the control inputs of the first and second registers, respectively, of the video signal E _R , E _G , E _B , the second output is connected to the control inputs of the blocks of sound registers, the third output is connected to the third inputs of the blocks of receiving the radio signal in the first and second paths of receiving and processing video codes, the fourth output is connected to the third input of the block of receiving radio signals in the third path of receiving and processing video codes, fifth the output is connected to the control inputs of the code processing units in the code processing channels, respectively, of the video signal E _R , E _G , E _B , the sixth output is connected to the control inputs of the adders and to the third control inputs of the first blocks of delay elements in the processing channels of the video signal codes E _R , E _G , E _B , the inputs of the first and second keys of the first sound channel are connected to the outputs of the first and second pulse shapers in the first path of receiving and processing video codes, the inputs of the first and second keys of the second sound channel are connected to the outputs of the first and second pulse shapers in the second path of receiving and processing video signal codes, the third input of the horizontal sync pulse allocation block is connected to the output of the first pulse shaper in the third path for receiving and processing video signal codes la, the third input vertical sync code allocation unit connected to the output of the second pulse generator in the same tract, inputs of the first, second and third blocks pulse amplifiers are connected to the outputs of the delay elements of the second block codes respectively processing video channels E _R , E _G , E _B , on the receiving side, the fourth, fifth and sixth blocks of pulse amplifiers are introduced, the inputs of which are connected to the outputs of the adders in the channels of the code processing, respectively, of the video signal E _R , E _G , E _B and their outputs are connected to the corresponding inputs of the radiation modulation unit, into which a second emitter of three primary colors is inserted, located in the same plane as the first emitter of three primary colors, the inputs of the second emitter are connected to the outputs of the fourth, fifth and sixth blocks of pulse amplifiers, code processing units identical and each includes a trigger, first, second, third and fourth registers, first, second, third blocks of delay elements, fifth and sixth registers, adder and the corresponding number of diodes, information these inputs of the first and second registers are connected to the outputs of the first block of delay elements, the outputs of the first register are connected to the inputs of the fifth register and through diodes to the first inputs of the adder, the outputs of the second register are connected to the first inputs of the adder, the information inputs of the third and fourth registers are connected to the outputs of the second block of delay elements, the outputs of the third register are connected to the inputs of the sixth register and through the diodes to the second inputs of the adder, the outputs of the fourth register are connected to the second inputs of the adder, whose moves are connected to the inputs of the third block of delay elements, the outputs of the fifth, sixth registers and the third block of delay elements are combined and are the outputs of the code processing unit, the first and second information inputs of which are the inputs of the first and second blocks of delay elements, the control input is the combined trigger input and control input of the adder, the first trigger output is connected to the control inputs of the second, third and fifth registers, the second trigger output is connected to the control inputs of the first, The Fourth and sixth registers, delay elements of the first blocks in the video signal processing channel codes E _R , E _G , E _IN are identical and each includes a first key and a first pulse distributor connected in series, a second key and a second pulse distributor connected in series, eight registers and an And element, the first and second signal inputs of an And element are the first and second control inputs of the block and are connected respectively to the output of the allocation block the frame clock and the output of the horizontal sync pulse allocation block, the signal inputs of the first and second keys are combined and are the third control input of the block, which the first is connected to the sixth output of the frequency synthesizer, the output of the And element is connected to the first control input of the first key and the second control input of the second key, the outputs of the first pulse distributor are connected in series to the clock (first) inputs of the bits of eight registers, and the first output is connected to the clock inputs of the first bits eight registers, and the last output through the diode is connected to the clock inputs of the last bits of eight registers, the last output is connected to the second control input of the first key and the first control input of the second key, the outputs of the second pulse distributor are connected in series to the clock inputs of the bits of eight registers, the first output connected to the clock inputs of the last bits of eight registers, the last output through the diode connected to the clock inputs of the first bits of eight registers, the last output also connected through the diode to the first control input of the first key and the second control input of the second key, the second bit inputs in each register are combined and the combined inputs are accordingly, the 1 - 8th information inputs of the block, the outputs of the bits in each register are combined and are respectively the 1 - 8th outputs of the block, the block for selecting the horizontal clock and the block for extracting the frame clock are identical and each includes the first, second, third pulse counters, the first, the second, third elements are NOT, the first and second elements AND and the diode, the outputs of the first and second pulse counters are connected to the inputs of the first element And, the output of which and the output of the third pulse counter are connected to the inputs of the second element And, the output of which is the output of the block, the inputs of the three elements are NOT connected respectively to the three counting inputs of the pulse counters, which are the inputs of the block, the outputs of the elements are NOT and the output of the second element AND are connected through the diode and connected to the control inputs of the pulse counters.

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