RU2462828C1 - Stereoscopic television system - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: photoelectric transducer (PET) is introduced on a transmitting side of a system, comprising two image receivers, every of which includes a matrix of "brightness - code" converters, six units of pulse amplifiers, six units to identify signals of high orders in a code, six units of encoders and six units of four-digit registers.

EFFECT: generation of a digital video image with its analog-to-digital conversion into a binary code of 30-bit colour depth.

22 dwg

Description

The invention relates to radio communications technology and can be used for digital broadcasting.

The prototype adopted "Universal television system" [1], containing two photoelectric converters on the transmitting side, the first generates signals of three colors of the right frame and signals of three colors of the left frame of stereo pairs, includes six ADC video signals, six encoders that compress the stream of frame codes with a compression ratio 4 per frame, code stream shaper, two triggers, two self-propelled pulse distributors / SRI /, two ADC audio signals, a frequency synthesizer and a single-channel radio signal transmitter, on the receiving side comprising a control unit, a path for receiving codes of video signals, a first channel for processing codes from three channels of color signals R ₁ , G ₁ , B ₁ , a second channel for processing codes from three channels of color signals R ₂ , G ₂ , B ₂ , the first and second flat panel screens . Stereopair frames go in parallel; polar separation of signals is applied. On the receiving side, the compressed video information is restored by the decoders, on the right and left screens the right and left frames are reproduced, which the viewer observes through the glasses of separate fields of view. The disadvantages of the prototype are the lengthy process of reading video signals when using an image sensor with a charge injection matrix device, the charges accumulated by each pixel of the PZI sensor [2, p. Each matrix element converts the amount of luminous flux into voltage in proportion to the brightness of the flux, which also requires analog-to-digital conversion to convert it to a digital video signal. The lower the signal reading frequency, the greater the signal voltage; with an increase in the frame rate, the signal value decreases, and the quality of the image transmitted to the receiving side decreases.

The purpose of the invention is the use on the transmitting side of the system of image receivers forming a digital video signal independent of the readout frequency, and obtaining on the transmitting side 30-bit color depth: ten bits in the codes of red, green and blue, on the receiving side, image reproduction from 30 -bit color depth.

The technical result is the formation of a digital video frame with a speed of light propagation with simultaneous analog-to-digital conversion to binary codes of 30-bit color depth. The essence of the invention is that on the transmitting side of the stereo television system, a photoelectric converter / photovoltaic converter is introduced, containing two image detectors, each of which includes a matrix of the corresponding number of transducers "radiation brightness - code", six blocks of pulse amplifiers, six blocks of the selection of senior bits of the code , six blocks of encoders and six blocks of four-digit registers, on the receiving side, a series-connected cheap block is introduced into each channel for processing color code codes Rathor and power recovery ten-digit code. In the inventive system, the video mode is 1000 _lines × 1100 _samples × 25 Hz, where 1000 is the number of lines in a frame, 1100 is the number of samples in a line, 25 Hz is the frequency of stereo pairs. The right and left frames go in parallel. Sampling rate of video signal codes:

f _d = 25 Hz × 1100 × 1000 = 27.5 MHz,

line frequency f _c = 25 Hz × 1000 = 25 kHz. The system uses encoders that compress the stream of codes with a coefficient of 4 per frame. With a compression ratio of 4, the frequency of issuing codes from the encoders is: f _d = 27.5 MHz: 4 = 6.875 MHz. The frequency of the clock sinusoidal oscillations during the formation of the stream of frame codes is:

f _t = 6.875 MHz × 16 = 110 MHz,

, период разрядов в коде

.where 6.875 MHz is the frequency of issuing codes from encoders, 16 is the number of bits in the sound codes, in the color signal codes of five bits, the total code in the right and left frames of 15 bits / five bits of the color R, five bits of the color G, five bits of color B, totaling a total of 15 bits. Codes Period

, period of bits in the code

.

The carrier frequency of the transmitter of the receiving side is taken f _n = 110 MHz × 16 = 1760 MHz / λ = 17 cm decimeter range /.

The upper side frequency f _HB = 1760 + 110 = 1870 MHz,

lower lateral frequency f _nn = 1760-110 = 1650 MHz / λ = 18 cm /.

Two code streams are transmitted in parallel from the radio signal transmitter: the right frame R ₁ , G ₁ , B ₁ and the left frame R ₂ , G ₂ , B ₂ stereo pairs. On the receiving side, the compressed video information is restored to 100%, on two screens two images are displayed in parallel: on the right screen, the right frame, on the left screen - the left. Screen resolution 1100 _count × 1000 _lines = 1.1 × 10 ⁶ pixels. Of 1100 samples in each line, three samples are sent for the transmission of three sound codes / Fig. 2/. The transmitting side in figure 1, the structure of the digital stream in figure 2, the arrangement of elements in the matrix of the image receiver in figure 3, the triad of one element of the matrix in figure 4, the Converter "radiation brightness - code" in figure 5, the block selection senior the discharge in the code in FIG. 6, the register block in FIG. 7, the code stream generator in FIG. 8, the amplitude-modulated signal spectrum in FIG. 9, the bipolar amplitude detector in FIG. 10, the encoder in FIG. 11, the receiving side on FIG. 12, the decoder of FIG. 13, the ten-bit code recovery unit of FIG. 14, the drive ko s of the frame in Fig. 15, the register blocks in Fig. 16, 17, the allocation block of the SSI, CSI in Fig. 18, one matrix element and its inside view from above in Fig. 19, the emitting cell in Fig. 20, the placement of the matrix elements in screen line in Fig.21, timing diagrams of the system in Fig.22.

и можно снизить несущую частоту в 1,875 раза: вместо 30 разрядов в посылке /10×3/ передаются 16 разрядов /сигнал звука/, частота тактовых колебаний при 30 разрядах составляет 6,875 МГц × 30=206,25 МГц, несущая будет 206,25 МГц × 16=3300 МГц.

На приемной стороне код восстанавливается в первоначальный вид дешифратором и блоком восстанавления кода.The transmitting side contains / Fig. 1 / photoelectric converter 1 / PEC /, which is a sensor of signals of three colors of the right frame and three colors of the left frame, and includes a first lens 2 and a first image receiver 3, the receiving side of which is located in the focal plane of the first lens 2, optical resolution images receiver 3 1100 × 1000 / 1.1 × ¹⁰ June / pixel outputs three groups with which 1 - 1.1 × 10 ^7/10 bits × 1.1 × ¹⁰ June / are connected to inputs respectively 1.1 × 10 ⁷ blocks of 4, 5, 6 pulse amplifiers, and their outputs 1 - 1.1 × 10 ⁷ from each of blocks 4-6, each respectively connected to the inputs 1 - 1.1 × 10 ⁷ blocks 7, 8, 9 of the selection signal of the highest category of code, the decoders in blocks 7, 8, 9 correspond to the resolution of the frame 1.1 × 10 ⁶ , outputs 1.1 × 10 ⁶ blocks 7-9 are connected to the same inputs of blocks 10, 11, 12 of the encoders, each of which includes encoders [3, p. 207, Fig. 8.6] according to the frame resolution number 1.1 × 10 ⁶ , the outputs of the encoders are connected to the inputs of the corresponding four-digit registers of blocks 13, 14, 15 registers, each of these blocks includes four-bit registers in the number of resolutions 1.1 × 10 ⁶ frames / 7 /. 1 includes FEP second lens 16, a second image receiver 17, the receiving side it is located in the focal plane of the lens 16, the resolution matrix of 1.1 × 10 ^6/1100 × 1000 / three groups of outputs to which 1.1 × ¹⁰ July connected to inputs 1.1 × 10 ⁷ blocks 18, 19, 20 of pulse amplifiers, the outputs of each block 18, 19, 20 are connected respectively to the inputs 1.1 × 10 ^{7 of} blocks 21, 22, 23, containing decoders that extract high-order signals in the outputs 1,1 × ¹⁰ June blocks 21-23 are connected respectively to the inputs of 1,1 × ¹⁰ June blocks 24, 25, 26 encoders, each of which comprises a number of bit encoders frame sheniya 1,1 × June ^10, first - fourth encoder outputs each connected to their four-digit registers in blocks 27, 28, 29, each of which comprises a number of registers of the frame permits 1,1 × June ^10, first - fourth outputs of blocks 13 -15 and 27-29 are the outputs of the FEC 1. The transmitting side includes six encoders 30, 31, 32, 33, 34, 35, made similar to the encoders of the analog [4, p.6, Fig.5, 6], includes a stream former 36 codes, frequency synthesizer 37, issuing from the first output pulses of the frequency 25 Hz stereo pairs, from the second output pulses U _vyd 6.875 MHz, the third - impu sy sampling sound codes 75 kHz, the fourth - sinusoidal oscillation clock 110 MHz, the fifth - the frequency of 25 kHz pulses row, the sixth - a sampling frequency of 27.5 MHz pulses codes, the seventh - sinusoidal oscillations of the carrier frequency 1760 MHz. All signals with a stability of 10 ^-7 include the first 38 and second 39 self-propelled pulse distributors / SRI /, performed identically [5, p. 269, 274, Fig. 9.7], the first 40 and second 41 ADC sound signals, identical to the ADC sound signals in analogue [6, p.5, Fig.7]. ADCs 40, 41 convert 3v1 and 3v2 audio signals into 16-bit codes with a frequency of 75 kHz. SRI 38 generates a horizontal sync pulse code of 16 units in a row, SRI 39 generates a frame sync pulse code of 16 consecutive units, during transmission, the sync and CSI codes are separated by a polar attribute. The transmitting side comprises a radio signal transmitter 42 from a serially connected carrier frequency amplifier 43, an amplitude modulator 44 including a ring modulator serially connected, suppressing the carrier of 1760 MHz [7, p. 234, 235], and a band-pass filter that filters out the unnecessary upper side frequency of 1870 MHz. The lower side frequency of 1650 MHz with the video information of the stereo pair codes enters the output amplifier 45 and radiates to the air with a stability of 10 ^-7 , hence the ± 165 Hz or 330 Hz occupied band. The first 3 and second 17 image receivers give the “initial product” to the stereo television system — the right and left frames of the stereo pair for transmitting and reproducing them on the receiving side. Receivers 3, 17 images are performed identically and the speed of light propagation is formed digital video frames of right and left frames each comprising a matrix of 1.1 × ¹⁰ June / 1100 × 1000 / elements arranged sequentially 1,100 pieces per line, the frame comprises 1000 lines. Images of frames are projected by lenses 2, 16 onto the receiving surfaces of image receivers 3, 17. Each individual element of the matrix is represented by a triad / Fig. 4/ of the three converters "radiation brightness - code" / Fig. 5/. The left-hand converter receives red R radiation, the upper converter receives green G radiation, the lower right receives blue B radiation. The "radiation brightness code" converter / Fig. 4, 5 / includes an opaque case 46 in the shape of a rectangular parallelepiped made of insulating material, at the front end of the case 46 there is a color filter 47 of one of the basic colors R, G, B, behind a color filter 47 in an opaque septum 48 microscope objective 49 is attached, by which the optical axis and an angle of 45 ° thereto consecutively arranged and rigidly fastened to the first to tenth translucent _1-10 micromirror 50 on the housing side, to which the micromirrors are rotated, pa put the first to tenth respective photodetectors 51 _1-10, receiving reflected radiation translucent micromirrors, and outputs the electrical pulses in a pulse amplifier block 4/5, 6 /, or 15/16, 17 /. The luminous flux after the color filter enters the micro-lens 49, directing it along its axis to the centers of translucent micromirrors 50 _1-10 . The principle of conversion "radiation brightness - code" is based on the fact that each front micromirror 50 transmits to the next stream of light, attenuated by half, which corresponds to the principle of binary code. In micromirrors, a beam splitting coating, which fulfills the ratio of reflected radiation to transmitted radiation as 1: 0.5 [8, p.223]. The number of translucent micromirrors 50 corresponds to the receipt of ten-digit codes. The electric signal from photodetectors 51 / Fig. 5/ is amplified in pulse amplifiers of blocks 4-6 and 18-20, is formed by amplitude and duration, and is fed to the inputs of blocks 7-9 / 21-23 /, the decoders in which are allocated in each ten-digit code signal "1" high order code. Codes from the converters consist of the following units, based on this, the option is taken not to transmit the whole ten-digit codes from units, but to transmit only the binary code of the signal of the high order unit in the code. In this case, the code does not contain ten digits, but only four: the unit code of the most significant digit will be from 0001 to 1010 / from 1 to 10 /. In this case, the number of transmitted signals is reduced by 2.5 times

and you can reduce the carrier frequency by 1.875 times: instead of 30 bits in the package / 10 × 3/16 bits are transmitted / sound signal /, the clock frequency at 30 bits is 6.875 MHz × 30 = 206.25 MHz, the carrier will be 206.25 MHz × 16 = 3300 MHz.

On the receiving side, the code is restored to its original form by a decoder and a code recovery unit.

Table 1 Codes from the transmitter "radiation brightness - code" Codes of high-order signals from block encoders 10-12, 24-26 0000000001 0001 /one/ 0000000011 0010 / 2 / 0000000111 0011 / 3 / 0000001111 0100 /four/ 0000011111 0101 /5/ 0000111111 0110 / 6 / 0001111111 0111 / 7 / 0011111111 1000 /8/ 0111111111 1001 /9/ 1111111111 1010 /10/

Highlighting “1” of the highest order in the codes is performed simultaneously and simultaneously in all codes of blocks 7–9, 21–23 by decoder circuits 52/6 /, including 20 NOT elements and 10 AND elements according to the number of bits in the code. Ten-bit codes in parallel form come from the outputs of blocks 4-6 / 18-20 / to the first and tenth inputs of the decoder 52, which gives the output signal from one bit - the highest bit in each code to blocks 10-12 / 24-26 / encoders , which, in turn, issue the binary code of this high order bit in register blocks 13-15 / 27-29 /, the number of encoders in blocks 10-12 / 24-26 / by 1.1 × 10 ⁶ . The blocks of registers 13-15, 27-29 are identical, each includes 1.1 × 10 ⁶ four-digit registers (Fig. 7/55) and a key 56 and a pulse distributor 57 connected in series with 1.1 × 10 ⁶ outputs from the first. The information inputs of the register block 13-15 / 27-29 / are the first and fourth inputs of all the registers connected to the outputs 4 × 1.1 × 10 ⁶ blocks 10-12, 24-26. The outputs of the register blocks 13-15, 27-29 are the bitwise combined first-fourth outputs of all the registers 55. The first control input of the register block 13-15 / 27-29 / is the signal input of the key 56 / 27.5 MHz /, the second control input U _from / 25 Hz / is the control input of the key 56, the output of which is connected to the input of the pulse distributor 57, the outputs of which from the first to 1.1 × 10 ⁶ are connected in series to the control inputs of the registers 55 _{1-1.1 × 10} ⁶ and are output signals U _vyd codes from registers 55. The key 56 is opened by the leading edge of the frequency pulse 25 Hz frames for a duration of 40 ms, during which the output signals from the 57 pulse distributor give codes from registers 55 sequentially to the corresponding encoder 30-35 at a frequency of 27.5 MHz. The encoders are identical to the encoders of the analogue [2, p.6, Fig.5, 6]. The transmitting side includes six encoders 30-35, a code stream shaper 36, a frequency synthesizer 37, the first 38 and second 39 self-propelled pulse distributors / SRI /, performed identically [5, p. 269, 274], the first 40 and second 41 ADC sound signals performed identically to the ADC of the analog sound signal [6, p.5, Fig.7]. The encoders are identical, each includes (Fig. 11) a series-connected register 79, a comparison circuit 80, a pulse counter 81 and a decoder 82, a delay element block 83, a key block 84, and a buffer code buffer 85 of the frame codes connected in series. The first and fourth information inputs are the bitwise combined inputs of the register 79, the first inputs of the comparison circuit 80 and the inputs of the delay element block 83. The outputs are the first to fifth outputs of the buffer storage 85 frame codes, the volume of which is 302500 five-digit codes / 275 _count × 1100 _lines /. The sequential issuance of codes from blocks 13-15, 27-29 to encoders 30-32, 33-35 is carried out by sampling signals of 27.5 MHz codes. Four-digit codes in parallel form are supplied to the first and fourth inputs of the register 79, to the first inputs of the comparison circuit 80 and to the inputs of the delay element block 83. The initial state of the keys in block 84 is open. The code in block 83 is delayed by 18 ns for the duration of the comparison circuit 80 and enters through the public keys of block 84 to the first and fourth bits of the buffer storage 85 of frame codes with a capacity of 302500 five-digit codes. Comparison scheme 79 performs a comparison of the size of each previous and subsequent codes to identify their equality or inequality. When unequal codes are followed, they pass through block 83, the public keys of block 84 and go to the first and fourth inputs of the first and fourth bits of the buffer storage 85 of the codes. The issuance of codes from block 85 is performed by 6.875 MHz signals from block 37. Codes arrive at block 85 when unequal codes are followed, with a frequency of 27.5 MHz. In the general stream of codes there are a large number of equal codes in magnitude, the higher the sampling rate, the more equal codes. The encoder compresses the stream with a floating compression ratio from 1 to 15. The average compression ratio per frame is taken as 4, so the output signals from block 85 are carried out at a frequency of 6.875 MHz. With a compression ratio of more than 4, this frequency will be all the more satisfying. The comparison circuit 80 compares the codes and is represented by two 530SP1 microcircuits with a comparison time of 18 ns [9, p. 279]. In case of inequality of codes A> B, a signal appears at output 2 of block 80, with equality of codes A = B, a signal appears at output 1 of block 80, with A <B, a signal from output 3. If the codes are equal, the signal from output 1 closes the keys in block 84 , is supplied by a counting pulse U _cf to the input of the counter 81 and to the first control input U _{output of the} register 79. The counter 81 counts the pulses from the output 1 of block 80 while equal codes are being sent. The counter 81 is four-digit, the maximum code in it is 1111/15 /, hence the floating compression ratio is from 1 to 15. The counter 81 is made of K500IE160 microcircuits with a response time of 8 ns [9, p. 428]. When unequal codes appear from circuit 80, a signal from output 2 or 3, which are combined, follows, the signal from them is used to issue a code for the number of equal codes from counter 81 through diodes of 1–4 bits of block 85 and to fill in block 85 of the fifth bit, which it is used when decoding to identify the code for the number of equal codes, the same signal opens the keys in block 84 / input 1 / and resets the register 79 / input 2 /. The code issued before this from block 85 is the first code in the sequence; in diagram 1 / Fig. 11/ they are marked with crosses. Codes of equal magnitude and counted by counter 81 are excluded from the code stream, diagram III. The exclusion of equal codes from the stream determines the compression ratio. The capacity of the buffer storage of 85 codes corresponds to the number of five-digit frame codes 302500 and provides a rate of passage of codes with a frequency of 6.875 MHz. When following consecutive codes, equal in magnitude more than 15 pieces, the work enters the decoder 82: the code 1111 from the counter 81 the decoder 82 outputs a pulse, that simultaneously opens the keys at block 84 / Input 1 / resets the register 79, outputs the U signal _vyd code from the counter 81 / input 1 / and nullifies the counter 81 / input 2 /, and the fifth digit of block 85 receives a signal for identifying the code for the number of equal codes. The bandwidth of the encoder is determined by the response time of the comparison circuit 80/18 ns / and is up to 50 × 10 ⁶ four-digit codes. From the outputs of encoders 30-32, the codes in parallel form arrive at the first information input of block 36 / Fig. 1/, from the encoders 33-35, the codes go to the second information input of block 36. The stream generator 36 of codes gives the first code of the horizontal sync pulse SSI / Fig. 2 /, from the compressed code stream generates and issues second to 272 signal codes B ₁ , G ₁ , R ₁ and B ₂ , G ₂ , R ₂ , and at the end of each line there are three sound codes 273-275. Shaper 36 code stream / Fig.8/ includes three channels, the first and second are identical. The first channel includes series-connected the first block of elements 58 And of 15 elements And, the first 59 and second 60 elements OR, the first output key 61 and the first SRI 62, the second channel includes the second block 63 of elements And of 15 elements And / three a code of color signals, each of five digits /, the third 64 and fourth 65 OR elements, the second output key 66 and the second SRI 67. The third channel includes two blocks 68, 71 elements AND 16 elements each, the fifth element 69 OR, the sixth element 72 OR, the third SRI 70 and the fourth SRI 73. The code stream generator 36 includes first 74, second 75 and third 76 keys, 16-bit pulse counter 77 and decryptor 78 connected in series. The information inputs of block 36 are: the first are the first inputs of the AND elements of block 58, the second are the first inputs of the AND elements of block 63, the third are the first / from 1 to 16 / inputs of elements AND block 68, fourth - first / from 1 to 16 / inputs of elements AND block 71, fifth - signal input of the third key 76, sixth - third input of the fourth element OR 65. The first output is the combined outputs of the output keys 61, 66, the second is the third output of the decoder 78, connected to SRI 38. The control inputs are: the first is the combined inputs of the keys 74, 75 and the counting input of the counter 77 pulses, the second is the combined inputs / 110 MHz / output keys 61, 66, the third is the control input 25 kHz of the counter 77, the fourth is the control input U _about 25 Hz of the third switch 76. The first output of the decoder is connected to the first control input U _{from the} first switch 74, a second output connected to the second control input U _of the key 74 and to the first control input U _from the second switch 75, a third output is connected to the second control U _of the input of the second switch 75 and I wish to set up the second output unit 36. The second inputs of the AND units 58, 63, blocks 68, 71 are connected to the outputs of the HRE respectively 62, 67 and 70, 73, 16 having outputs sixteenth outputs HRE 62, 67 are not used. The output of the first key 74 is connected to the inputs of the SRI 62, 67, the output of the second key 75 is connected to the inputs of the SRI 70 and 73. The output of the third key 76 is connected to the third input of the second OR element 60 / Fig. 8/.

The receiving side contains / FIG. 12 / antenna, control unit 86 / channel selection /, one path for receiving and processing video signal codes, a channel for generating control signals, first and second flat-panel screens, two sound reproduction channels and glasses 140 with separate fields of view. The path for receiving and processing codes of video signals contains a series-connected block 87 for receiving radio signals, an amplifier 88 for radio frequencies and a bipolar amplitude detector 89 (Fig. 10/), the first and second channels for processing codes of video signals: the first channel for processing codes includes a series-connected first pulse generator 90, whose input connected to the first output of the bipolar amplitude detector 89, a first receiving register 91, and the fifteen bits of three channel color signals: signal channel R _1, G ₁ channel signal, kan signal V _1, the second code processing channel includes series connected second shaper 111 pulses, the input of which is connected to the second output bipolar amplitude detector 89, a second receiving register 112 of 15 bits, and three-channel color signals: signal channel R _2, signal channel G ₂ , signal channel B ₂ . The signal channel R ₁ includes serially connected five-digit register 92, decoder 93, decoder 94, ten-bit code recovery unit 95, 96 frame code storage unit and pulse amplifier block 97, including pulse amplifiers based on the number of outputs of 96 storage frame codes and bits in 10 × 1 code 1 × 10 ^6/1100 × 1000 /, G ₁ channel signal comprises a serially coupled register 98, a decoder 99, a descrambler 100, the recovery unit 101 is a 10-bit code, the drive frame 102 and the block 103 codes the pulse amplifiers of 1.1 × 10 ⁷ pulse amplifiers, signal channel Ala B ₁ includes a five-bit register 104, a decoder 105, a decoder 106, a 10-bit code recovery unit 107, a frame code storage 108 and a pulse amplifier unit 109 of 1.1 × 10 ⁷ pulse amplifiers. The outputs of the blocks 97, 103, 109 of the pulse amplifiers are connected to the inputs 3 × 1.1 × 10 ^{7 of the} first flat panel screen 110. The signal channel R ₂ includes a register 113, a decoder 114, a decoder 115, a block 116 for recovering a 10-bit code, a drive 117 codes frame and block 118 of pulse amplifiers of 1.1 × 10 ⁷ , channel G ₂ includes a five-bit register 119, decoder 120, decoder 121, block 122 recovery 10-bit code, the drive 123 frame codes and block 124 pulse amplifiers, channel signal B ₂ includes a five-digit register 125, decoder 126, decoder 127, block 128 recovery 10- bit code, a drive 129 frame codes and a block 130 of pulse amplifiers from 1.1 × 10 ⁷ pulse amplifiers. The outputs of blocks 118, 124, 130 are connected to the inputs 3 × 1.1 × 10 ^{7 of the} second flat panel screen 131. The order of operation of the receiving side is determined by the channel for generating control signals, including a block 132 for selecting horizontal sync pulses / SSI /, frequency synthesizer 133, key 134, a counter 135 pulses and a decoder 136, and block 137 allocation of frame sync pulses / CSI /. The receiving side includes identical first 138 and second 139 sound reproduction channels, each of which contains a converter of 16-bit codes of sound into analog signals / DAC /, a power amplifier and a loudspeaker. The viewer perceives the image surround through glasses 140 separate fields of view. The glasses contain / Fig. 12/ a frame with earbands, glasses windows without glasses, are interconnected by a movable vertical axis to rotate them relative to each other in the horizontal plane, to separate the fields of view of the eyes, each window of the glasses has a removable conical hood at the end of a rectangular shape and under the shape of the screen. Two-part hood: the first part is screwed into the glasses window, the second part is movable, extends and retracts into the first, changing the length of the hood. When viewing the viewer by turning the windows of the glasses and changing the lengths, the blend adjusts the visual fields of the eyes so that each eye sees only its own screen. Decoders 93, 99, 105, 114, 120, 126 are identical, each contains a first five-bit register 141 connected in series, a frame code storage 142 with a capacity of 299200/272 samples × 1100 lines / five-bit codes, a second five-bit register 143, the first block of 144 keys of four keys and a third four-bit register 145, connected in series to the second block of keys 146 of four keys, a four-digit subtracting counter 147 pulses and a decoder 148, the first 149, second 150, the third 151 and fourth 152 keys. The information input is the first to fifth inputs of the register 141, the output is the first to fourth outputs of the third register 145. The control inputs are: the first is the combined control inputs of the register 141 and the signal input 6.875 MHz of the third key 151, the second is the combined signal inputs of 27.5 MHz keys 149, 150, 152. The output of the fifth rate register 143 is connected in parallel to the first control input of the second switch 150, a second control input key 151, 152 and 149, to the second control input U _of the block 144 and to a first control input U _from vtorog Block 146 keys. The output of the key 149 is connected to the first control input U _{vyd1 of the} register 145, the second control input U _{vy2 of} which is connected to the output of the second key 150, to which the counting input of the subtracting pulse counter 147 is connected. Output of decoder 148 is connected in parallel to the first control input of the keys 144 of the first unit to the second control input U _of the unit key 146, to the first control input U _from keys 149, 151, 152 and to the second control vxodu U _of key 150. The output of the third switch 151 connected to the control input U _vyd drive frame 142 codes, key 152 output U connected to the control input of the second register 143 _vyd.

The operation of the decoder, Fig.13

Codes are sent in parallel to the first register 141, from which 142 codes of a frame with a capacity of 299,200 five-digit codes are issued to the drive, from which codes are sent with 6.875 MHz signals from key 151. With the private key 151, drive 142 concentrates the codes in itself. The initial state of the keys in block 144 is open, in block 146 is closed, keys 149, 151, 152 are open, key 150 is closed. In the first and fifth digits of the second register 143, signals of 1-4 digits are received, and if there is a signal in the fifth digit of the code / the signal for identifying the code for the number of equal codes / it enters the fifth digit of the register 143, from which the signal _Uout is issued from key 152 with a frequency 27.5 MHz While codes without identification signal arrive in register 143, they enter through the public keys in block 144 into the third register 145, and from it they are issued by the signal U _iss1 from key 149 to the decoder output with a frequency of 27.5 MHz. The signal U _vyd1 when issuing the code and resets 1-4 bits of the register 145. When the code 143 receives the identification signal in the fifth category, the signal from the fifth category closes the keys in block 144, opens the keys in block 146, closes the keys 149, 151, 152 and opens the key 150. The issuance of codes from the register 143 is interrupted, and the drive 142 accumulates the codes of the frame, as codes continue to come into it. The code of the number of equal codes through the public keys of block 146 enters the subtracting counter 147 pulses, the counting input of which from the key 150 receives pulses of 27.5 MHz. The pulses from the key 150 are received by the output signal U _2d2 to the second control input of the register 145 and issue the code contained in it, but do not reset it. Therefore, while the counter 147 is working on subtracting from the register 145 the same code is issued, these codes were removed during compression of the code stream in the encoder on the transmitting side. From the output of register 145 is a 100% restored stream of codes. From register 145 are four-digit codes with a frequency of 27.5 MHz. Upon completion of the subtraction in the counter 147, the code from zeros enters the decoder 148, from the output of the decoder 148 the signal closes the keys in block 146 / input 2 /, closes the key 150, opens the keys in block 144 and the keys 149, 151, 152. From the drive 142 codes codes are again issued to register 143, from it through the public keys of block 144 to register 145, then the processes are repeated. The decoder throughput is set by the response time of the counter 147 / 10.5 ns /, chip 100IE137 [9, p. 428] plus the response time of the decoder 148 / chip 100ID161 [9, p. 433] /, the recovery speed is up to 50 MB / s. The recovered stream with a frequency of 27.5 MHz is supplied to the inputs of the decoders 94, 100, 106, 115, 121, 127. The combinations of binary codes from 0001 to 1010 / from 1 to 10 /, which correspond to one corresponding output from the decoders, enter the decoders inputs [3, p.202]. When decrypting according to the binary code, one of the ten outputs of the decoder displays a signal supplied to the corresponding input of the block 95/101, 107, 116, 122, 128 / recovering the ten-digit code. The blocks for recovering ten-digit codes are identical / Fig. 14/, each includes ten inputs, nine groups of diodes connected to the corresponding groups of diodes, and ten outputs on which the restored ten-bit code appears. Fig. 14 shows an example of recovering the code 0000111111: the binary code 0110 was input to the decoder, a signal appears on the fifth output of the decoder 94, which is fed to the fifth input of block 95 / Fig. 14/, and signals appear on the fifth to tenth outputs of block 95 representing the reconstructed code 0000111111 obtained on the transmitting side by the "radiation brightness - code" converter. The first group of diodes in block 95 is from a single diode, its input is connected to the first input / senior / block 95, and the diode output is connected to the second output of block 95. The second group of diodes is from two diodes, their outputs are combined and connected to the third output of block 95, and their inputs are separately connected to the first and second inputs of block 95. The third group of diodes is of three diodes, their outputs are combined and connected to the fourth output of block 95, and the inputs are connected separately to the first - third inputs of block 95, the fourth group of four diodes, outputs their connected to the fifth in block 95, their inputs are connected separately to the first and fourth inputs of block 95, the fifth group of five diodes, their outputs are connected to the sixth output of block 95, and the inputs are connected separately to the first - fifth inputs of block 95, the sixth group of diodes from six their outputs are connected to the seventh output of block 95, and the inputs are separately connected to the first to sixth inputs of block 95, the seventh group of diodes is from seven diodes, their outputs are combined and connected to the eighth output of block 95, and the inputs are connected separately to the first - seventh inputs of block 95 eighth groups diodes of eight diodes, their outputs are connected to the ninth output of block 95, and their inputs are connected separately to the first and eighth inputs of block 95, the ninth group of nine diodes, their outputs are combined and connected to the tenth output of block 95, and the inputs are separately connected to the first - to the ninth inputs of block 95. Blocks 95, 101, 107, 116, 122, 128 of restoration of two-digit codes restore the codes to their original form, which they were at the outputs of the "radiation brightness - code" converters of image receivers 3, 17 of the image / Fig. 1/. The recovered ten-digit codes are received in their drives 96, 102, 108, 117, 123, 129 frame codes, executed identically, each includes (Fig.15) blocks 153 _1-1000 registers by the number of lines in the frame / 1000 /. The information input of the frame code storage device is the bitwise integrated first to tenth inputs of blocks 153 of _1-1000 registers. The outputs are the parallel outputs of all blocks of 153 registers, of which 10 × 1.1 × 10 ⁶ or 1.1 × 10 ⁷ . The control inputs of each block of code frame storage are: the first is the first 25 Hz control input of the first block 153 ₁ registers, the second is the combined second control inputs 25 kHz U _output of 153 register blocks, the third is the combined third control inputs U _d 27.5 MHz of 153 blocks registers. Each control output of the previous block of registers is the first control input for each subsequent block of 153 registers / Fig. 15/, the control output of the last block of 153 ₁₀₀₀ registers is connected in parallel to the fourth control inputs of all blocks of 153 registers, total outputs from the drive 96 frame codes 1.1 × 10 ⁷ . Blocks 153 registers are performed identically, each includes / Fig. 16, 17 / first 154, second 155 keys, distributor 156 pulses and ten registers 157 _1-10 , each of 1100 bits according to the number of samples in a row. The information inputs of the block 153 registers are bitwise combined first to tenth third inputs of the bits of ten registers 157. The outputs are the parallel outputs of all 1100 bits of the ten registers 157: total outputs 11000/10 × 1100 /. The control inputs are: the first is the first control input U _from 25 Hz of the first key 154, the second is the signal input 25 kHz U _{output of the} second key 155, the third is the signal input U _d 27.5 MHz of the first key 154, the fourth is the first control input U _from key 155. The last output of the distributor 156 pulses is the control output of block 153 ₁ in the next block 153 ₂ registers and connected to its first control input of the first 154 key. The output of the key 154 is connected to the input of the pulse distributor 156, the outputs of which are connected in series from the first to the 1100th in parallel to the first / clock / inputs of the bits of the ten registers 157. The output of the second key 155 is connected in parallel to the second inputs of the bits of the ten registers 157 and to the second control U _{from the} input of its key 155, the last one pulse _Uout closes the key 155. The outputs of the drives 96, 102, 108, 117, 123, 129 are connected to the information inputs of their blocks 97, 103, 109, 118, 124, 124, 130 of pulse amplifiers, each of which includes pulse amplifiers if the frame number of the resolution and the number of bits in the code: 10 × 1,1 × 10 ⁶ or 1,1 × 10 ^7th. With the arrival of the signal from the last block 153 ₁₀₀₀ registers to the fourth control inputs of all the blocks 153 _1-1000 registers the codes of the right and left frames are provided to a pulse amplifier, which outputs a signal in code units, reinforced to the required magnitude and duration of 40 ms, parallel arrive at the inputs of screens 110, 131, respectively. The SSI block for extracting horizontal sync pulses and the CSI frame sync block extracting unit 137 are identical, each includes / Fig. 18/ five-digit counter 158 pulses, decoder 159, element H E 160 and two diodes D1, D2. The counter 158 counts 16 pulses / code 10000 /. The information input of block 132 is the counting input of the counter 158 connected to the output of the pulse shaper 90, the control input is the input of the diode D1 connected to the output of the second pulse shaper 111 / Fig.12/. In block 137, the information input is connected to the output of the second pulse shaper 111, and the control input is connected to the output of the first pulse shaper 90. The output of the decoder 159 is the output of the block 132/137 / and is connected through the diode D2 to the output of the element HE 160, together they are connected to the control input of the pulse counter 158 after the diode D1. The SSI code / and the CSI code / of 16 units goes to the counting input of block 158, the counter counts sixteen pulses in a row: the outputs are 1 to 4 counters are zeros, on the fifth output the signal decoded by block 159 is the output of block 132, the clock pulse of the SSI line, at the output of block 137, it is the sync pulse of the CSI frame. When the SSI code is on, there are no signals from block 111 and vice versa / Fig. 2/. Starting from the second line code / Fig.2/ from block 111 go to the control input of the counter 158 codes. With the arrival of each code pulse, the counter 158 is reset and cannot reach the count of 16. In parallel, the code pulses from block 90, in which there are 1 and 0, will arrive at the counting input, and for each zero the element NOT 160 gives a pulse that also resets the counter 158, in addition, when the pulse SSI / CSI / from the block 159 is output, through D2 it enters the control input of the counter 158 and also resets it. As a result, the circuit blocks 132, 137 exclude the appearance of false SSI and CSI at the output. Block 137 works in the same way as block 132. Flat-panel screens 110, 131 are identical. Each screen contains a matrix of elements according to the number of screen resolutions 1.1 × 10 ⁶ , 1100 × 1000. One matrix element forms a pixel with three radiating cells emitting the basic colors R, G, B. A general view of one matrix element and its top view inside the housing in Fig. 19 and includes an opaque housing 161 of the corresponding shape, combining three radiating cells: the lower left 162 radiates red R color, the upper 163 emits green G color, the lower right 164 emits blue B color. Each emitting cell contains in the front end of the housing 161 a microlens 165, which acts as a micro lens, and a color filter 166 of one of the basic colors R, G, B is fixed in the output end of the housing. Between the microlens 165 and the color filter 166 there is a diaphragm having a cylindrical body 169 with eight slots in which translucent and neutral microfilter filters 167 _{1-10 /} Fig. 20/ are attached to their micropiezoelectric elements 168 _1-10 along one another along the optical axis of the microlens 165. The first ends of the micropiezoelectric elements 168 with two control inputs are rigidly fixed in the matrix element housing 161, to the free ends of the micropiezoelectric elements 168 translucent neutral microfilter filters 167 are attached, which in the absence of control pulses from the pulse amplifier blocks completely block the radiation flux from the microlens 165. The emitting cells work the same way, the principle the action is that each translucent neutral microfilter 167 attenuates the radiation of the stream by half, which corresponds to the principle of two egg code. The radiation from the sources of irradiation / backlight / super-bright white LEDs is directed by the microlens 165 along its optical axis through the translucent neutral microfilter 167 to the color filter 166, which gives the output radiation the corresponding color. The inputs of the micropiezoelectric elements 168 _1-10 are the control inputs of the matrix element and are connected to the outputs of the pulse amplifiers in blocks 97, 103, 109, 118, 124, 130. In the absence of control pulses / unit signals / micropiezoelectric elements are in an unstressed state, all translucent microfilter filters 167 are located along the optical axis of the microlens 165, the radiation flux is completely blocked. With the arrival of the control pulse at the input of the micropiezoelectric element 168, its free end bends and removes its translucent microfilter 167 from the radiation stream for a duration of 40 ms so that it does not overlap and attenuate the radiation flux, which corresponds to a unit in the code that is not removed from the radiation flux of the microfilter 167 corresponds to zero in the code category. Upon receipt of the code from one unit 1111111111, all micro-filters 167 _1-10 are removed from the stream, and the maximum radiation comes from the emitting cell. Upon receipt of different codes from the radiation flux, microfilter filters corresponding to units in the code are output. Micropiezoelectric elements 168 are used tubular piezoelectric elements that work on bending, durable and reliable for prolonged operation [10, p.27]. Emitting cells are made as miniature as possible with transverse dimensions up to 1 × 1 mm. The radiating cells are manufactured separately and combined into a matrix element housing 161, and a screen matrix is drawn from the elements. The radiation of three cells forms the brightness and color tone of the pixel. The microlenses 165 are irradiated with super-bright white LEDs located in the appropriate amount and in the corresponding order on the back side inside the screen body.

During the operation of the stereo television system, lenses 2 and 16 project images of the right and left frames on the matrix of receivers 3, 17 of the image in which all the triads of the "radiation brightness - code" converters simultaneously issue codes of all video signals of colors R ₁ , G ₁ , B _{1 of the} right frame in blocks 4, 5, 6 of pulse amplifiers and codes of all video signals R ₂ , G ₂ , B _{2 of the} left frame into blocks 18, 19, 20 of pulse amplifiers, from which pulses of codes in parallel form enter blocks 7-9 and 21-23 senior bit of the code, the signals of the allocated bits of the codes come in pairs allele to the inputs of blocks 10-12, 24-26 encoders, in which the signals of the selected high-order bits are encrypted with a binary four-digit code from 0001 to 1010 and enter their blocks 13-15, 27-29 registers. With the arrival of the next pulse U _to 25 Hz at the control input U _{from the} key 56 (Fig. 7/), the key 56 opens, passes 27.5 MHz clock pulses to the input of the 57 pulse distributor, which are sequentially issued from the registers 55 _1-1.1x10 ⁶ four-bit codes to encoders 30-35. Coders compress the stream of codes with a coefficient of 4 per frame, the frequency of issuing codes from encoders 30-35 6.875 MHz. From the outputs of the encoders, the codes are five-digit, the fifth digit, the service one, is a signal for identifying the code for the number of equal codes in value.

From encoders 30-32, the codes are sent to the first information input of the generator 36 of the code stream (Fig. 1/), from encoders 33-35, codes are sent to the second information input of the block 36 / Fig. 8/. timing diagrams of the operation of the shaper 36 stream of codes in Fig.22. Shaper 36 code stream converts parallel codes into sequential ones and replaces the representation of units from pulses with positive ones in codes R ₁ , G ₁ , B ₁ and negative in codes R ₂ , G ₂ , B ₂ half-sinusoids of mono frequency 110 MHz with a stability of 10 ^-7 . The third and fourth information inputs receive 16-bit sound codes from the ADC 40, 41, the information 5 and 6 inputs receive 16-bit SSI and CSI codes from self-propelled code distributors 38, 39. The CSI code is the first code in the first line of the stereo pair frame / Fig.2/, the SSI code is the first code in each line, starting with the second. Units in the codes of the right frame are represented at the output of the code stream generator 36 by positive sine waves, units in the codes of the left frame of the stereo pair are represented at the output of block 36 by negative sine waves of the same frequency of 110 MHz.

The operation of the shaper 36 code stream, Fig. 8.

Выходной ключ 61 в открытом состоянии пропускает одну положитльную полусинусоиду на выход, выходной ключ 66 в открытом состоянии пропускает на выход одну отрицательную полусинусоиду той же моночастоты 110 МГц. Выходы ключей 61, 66 объединены и являются первым информационным выходом блока 36, выходные сигналы с которого являются полными или неполными синусоидами частоты 110 МГц со стабильностью 10^-7. Порядок следования в строке кодов КСИ, ССИ, кодов звука задают сигналы с выходов дешифратора 78. Счетчик 77 импульсов девятиразрядный ведет счет 275 импульсов с частотой 6,875 МГц с первого по 275 /фиг.2/. При коде 000000001 импульс с первого выхода дешифратора 78 открывает ключ 74, пропускающий импульсы 6,875 МГц, являющиеся сигналами пуска U_п для СРИ 62, 67, и идет формирование кодов строки с №2 по №272. С приходом на вход счетчика 78 импульса 272 строки с второго выхода блока 78 импульс U_з закрывает ключ 74 и открывает U_от ключ 75: формируются три кода звука 3в1 и три кода звука 3в2, это 273, 274 и 275 отсчеты строки /фиг.2/. Импульсы кодов 3в1 с блока И 68 через элементы ИЛИ 69 поступают на второй вход элемента ИЛИ 60 и открывают на время своей длительности 9 нс выходной ключ 61, импульсы кодов звука 3в2 с элемента ИЛИ 72 поступают на второй вход элемента ИЛИ 65 и открывают выходной ключ 66, формируются три кода 3в1 и 3в2, коды 3в1 представляются положительными полусинусоидами тактовой частоты 110 МГц, коды 3в2 представляются отрицательными полусинусоидами той же частоты. С приходом в счетчик 77 275-го импульса строки с третьего выхода блока 78 импульс U_з закрывает ключ 75 и как сигнал пуска U_п запускает СРИ 38, выдающий код из 16-ти единиц - код ССИ, который проходит открытый ключ 76 и поступает на третий вход второго элемента ИЛИ 60. По окончании периода кадра импульс следующего кадра 25 Гц передним фронтом закрывает ключ 76 на длительность 16-ти разрядов кода КСИ 144 нс /9 нс × 16/ и передним же фронтом запускается СРИ 39, выдающий 16-разрядный код КСИ, поступающий на третий вход элемента ИЛИ 65. Сигналы КСИ представляются на выходе выходного ключа 66 отрицательными полусинусоидами. Когда идет код КСИ, нет импульсов кода ССИ, ключ 76 закрыт, когда идет код ССИ, нет импульсов кода КСИ. Полные и неполные синусоиды с выхода 1 блока 36 являются модулирующими сигналами для несущей частоты в амплитудном модуляторе 44 /фиг.1/. Нижняя боковая частота 1650 МГц с информацией кодов излучается в эфир. На приемной стороне радиосигналы принимаются блоком 87 /фиг.12/, являющимся селектором каналов с электронной настройкой, блок 87 включает входную цепь, усилитель радиочастоты и смеситель, на второй вход которого с синтезатора 133 частот /вход 3 блока 87/ подается частота, равная несущей частоте передатчика 42, необходимая для детектирования однополосного сигнала [11, с.146]. Сигнал со смесителя, являющийся выходным сигналом блока 87, поступает на вход усилителя 88 радиочастоты, где усиливается до необходимой величины и поступает на вход двухполярного амплитудного детектора 89, выполненного по принципиальной схеме на фиг.10. Диод Д1 выделяет положительную огибающую модулирующего сигнала /диаграмма 9, фиг.22/. Диод Д2 из модулирующей выделяет огибающие положительных полусинусоид - символы единиц кодов правого кадра R₁, G₁, B₁ /диаграмма 10, фиг.22/. Диод Д3 из модулирующей выделяет огибающие отрицательных полусинусоид - символы единиц кодов левого кадра R₂, G₂, В₂ /диаграмма 11, фиг.22/. С первого выхода блока 89 продетектированные положительные полусинусоиды 110 МГц поступают на вход первого формирователя 90 импульсов, со второго выхода блока 89 продетектированные отрицательные полусинусоиды той же частоты поступают на вход второго формирователя 111 импульсов. Формирователи 90, 111 импульсов выполнены по схеме несимметричного триггера с эмиттерной связью [12, с.209], формирующий прямоугольные импульсы из гармонически изменяющихся сигналов. Импульсы имеют одну полярность и длительность, равную длительности импульсов на передающей стороне. Единицы в кодах вновь представляются импульсами, нули их отсутствием. При включении питания ключ 134 в закрытом состоянии. Порядок работы приемной стороны задается сигналами с канала формирования управляющих сигналов, задающая роль принадлежит блоку 132 выделения ССИ. При каждом приходе на вход блока 132 кода ССИ на его выходе появляется строчный синхроимпульс ССИ 25 кГЦ, который открывает ключ 134. По сигналам ССИ выполняется и точная подстройка частоты в блоке 133, собственная частота которого имеет стабильность 10^-6. Вторые входы блока 133 подключены к второй группе выходов блока 86 /выбора каналов/, сигнал с которого определяет частоту, выдаваемую с блока 133 на третий вход блока 87. Синтезатор 133 частот выдает: с первого выхода импульсы 6,875 МГц, со второго выхода - тактовые импульсы 110 МГц, с третьего - импульсы 75 кГЦ для выдачи кодов звука, с четвертого - импульсы дискретизации кодов 27,5 МГц, с пятого выхода - синусоидальные колебания соответствующей несущей частоты на третий вход блока 87. С первого формирователя 90 импульсов коды поступают на информационный вход первого приемного регистра 91, со второго формирователя 111 импульсов импульсы кодов поступают на входы второго приемного регистра 112. Приемный регистр 91 имеет пятнадцать разрядов и принимает три пятиразрядных кода цветовых сигналов R₁, G₁, B₁ правого кадра. Приемный регистр 112 имеет тоже пятнадцать разрядов и принимает три пятиразрядных кода левого кадра R₂, G₂, B₂. С приемных регистров сигналы U_выд 6,875 МГц синхронно выдают коды сигналов R₁, G₁, B₁ в регистры 92, 98, 104 и коды сигналов R₂, G₂, B₂ в регистры 113, 119, 125. С этих регистров коды в параллельном виде с частотой 6,875 МГц поступают в декодеры соответственно 93, 99, 105, 114, 120, 126, которые восстанавливают сжатые потоки кодов цветовых сигналов. Восстановленные потоки кодов с частотой 27,5 МГц поступают на информационные входы дешифраторов 94, 100, 106, 115, 121, 127. Дешифраторы соответственно комбинации двоичного кода старшего разряда выдают сигналы на одном из первого - десятого выходов в блоки 95, 101, 107, 116, 122, 128 восстановления десятиразрядных кодов, с первого - десятого выходов которых коды поступают на информационные входы своих накопиелей 96, 102, 108, 117, 123, 129 кодов кадра.Three five-digit codes from encoders 30, 31, 32 are received at the first inputs of fifteen AND elements of block 58; three codes from encoders 33, 34, 35 are received at the first inputs of fifteen AND elements of block 63. The second inputs of AND elements of blocks 58, 63 are received by fifteen pulses from the outputs of SRI 62, 67. From the outputs of blocks 58, 63, the pulses of the codes sequentially through the OR elements 59, 60 and 64, 65 are fed to the control inputs of the output keys 61, 66 and open them for a duration of 9 ns

The output key 61 in the open state passes one positive half-sine wave to the output, the output key 66 in the open state passes one negative half-sine wave of the same mono frequency 110 MHz to the output. The outputs of the keys 61, 66 are combined and are the first information output of the block 36, the output signals from which are full or incomplete sine waves of a frequency of 110 MHz with a stability of 10 ^-7 . The sequence in the line of codes of CSI, SSI, sound codes is set by the signals from the outputs of the decoder 78. The 77-pulse counter nine-digit counts 275 pulses with a frequency of 6.875 MHz from the first to 275 / Fig.2/. With the code 000000001, the pulse from the first output of the decoder 78 opens the key 74, which transmits 6.875 MHz pulses, which are the start signals U _p for SRI 62, 67, and the formation of line codes from No. 2 to No. 272 is in progress. With the arrival at the input of the counter 78 of the pulse 272 lines from the second output of block 78, the pulse U _s closes the key 74 and opens U _{from the} key 75: three 3v1 sound codes and three 3v2 sound codes are generated, these are 273, 274 and 275 line samples / Fig.2 /. Pulses of 3v1 codes from block AND 68 through the OR 69 elements go to the second input of the OR element 60 and open the output key 61 for a duration of 9 ns, pulses of 3v2 sound codes from the OR element 72 go to the second input of the OR element 65 and open the output key 66 , three codes 3v1 and 3v2 are generated, 3v1 codes are represented by positive half-sine waves of 110 MHz, 3v2 codes are represented by negative half-sines of the same frequency. With the arrival at the counter 77 of the 275th pulse of the line from the third output of block 78, the pulse U _s closes the key 75 and, as the start signal U _p, launches the SRI 38, issuing a code of 16 units - the SSI code, which passes the public key 76 and goes to the third input of the second element OR 60. At the end of the frame period, the pulse of the next 25 Hz frame by the leading edge closes the key 76 for a duration of 16 bits of the CSI code 144 ns / 9 ns × 16 / and the leading edge starts the SRI 39, issuing a 16-bit code CSI coming to the third input of the OR element 65. Signals of the CSI are presented at the output de output key 66 negative sine. When the CSI code is in, there are no pulses in the CSI code, key 76 is closed, when the CSI code is in, there are no pulses in the CSI code. Complete and incomplete sinusoids from the output 1 of block 36 are modulating signals for the carrier frequency in the amplitude modulator 44/1 /. The lower side frequency of 1650 MHz with code information is broadcast. At the receiving side, the radio signals are received by block 87 (Fig. 12/), which is an electronically tuned channel selector, block 87 includes an input circuit, a radio frequency amplifier, and a mixer, the second input of which from the synthesizer 133 frequencies / input 3 of block 87 / is supplied with a frequency equal to the carrier the frequency of the transmitter 42, necessary for the detection of a single-band signal [11, p.146]. The signal from the mixer, which is the output signal of block 87, is fed to the input of the radio frequency amplifier 88, where it is amplified to the required value and fed to the input of the bipolar amplitude detector 89, made in accordance with the circuit diagram in FIG. 10. Diode D1 selects the positive envelope of the modulating signal / chart 9, Fig.22 /. The diode D2 from the modulating one selects the envelopes of the positive half-sinusoids - symbols of units of codes of the right frame R ₁ , G ₁ , B ₁ / chart 10, Fig.22 /. The diode D3 from the modulating one selects the envelopes of the negative half-sinusoids - symbols of units of codes of the left frame R ₂ , G ₂ , B ₂ / diagram 11, Fig. 22 /. From the first output of block 89, the detected positive half-sine waves of 110 MHz are supplied to the input of the first pulse generator 90, and from the second output of block 89, the detected negative half-sine waves of the same frequency are fed to the input of the second pulse generator 111. Shapers 90, 111 pulses are made according to the scheme of an asymmetric trigger with emitter coupling [12, p.209], forming rectangular pulses from harmonically changing signals. The pulses have one polarity and a duration equal to the duration of the pulses on the transmitting side. Units in codes are again represented by pulses, zeros by their absence. When the power is turned on, key 134 is in the closed state. The order of operation of the receiving side is set by the signals from the channel for generating control signals, the decisive role belongs to the block 132 allocation SSI. Each time the SSI code block 132 arrives at the input, a horizontal SSI clock pulse of 25 kHz appears at its output, which opens the key 134. The SSI also performs fine tuning of the frequency in block 133, whose natural frequency has a stability of 10 ^-6 . The second inputs of block 133 are connected to the second group of outputs of block 86 / channel selection /, the signal from which determines the frequency output from block 133 to the third input of block 87. Frequency synthesizer 133 outputs: 6.875 MHz pulses from the first output, clock pulses from the second output 110 MHz, from the third - pulses of 75 kHz for issuing sound codes, from the fourth - sampling pulses of codes 27.5 MHz, from the fifth output - sinusoidal oscillations of the corresponding carrier frequency to the third input of block 87. From the first driver 90 pulses, the codes are sent to the information input the first receiving register 91, from the second pulse shaper 111, the code pulses are fed to the inputs of the second receiving register 112. The receiving register 91 has fifteen bits and receives three five-bit codes of color signals R ₁ , G ₁ , B _{1 of the} right frame. The reception register 112 also has fifteen bits and receives three five-bit codes of the left frame R ₂ , G ₂ , B ₂ . From the receiving registers, the signals _Udat 6.875 MHz synchronously provide the signal codes R ₁ , G ₁ , B ₁ to the registers 92, 98, 104 and the signal codes R ₂ , G ₂ , B ₂ to the registers 113, 119, 125. From these registers, the codes in a parallel form with a frequency of 6.875 MHz, decoders 93, 99, 105, 114, 120, 126, respectively, which recover the compressed code signal color streams. Recovered code streams with a frequency of 27.5 MHz are fed to the information inputs of the decoders 94, 100, 106, 115, 121, 127. The decoders, respectively, the combination of the binary code of the highest order, give signals at one of the first to tenth outputs in blocks 95, 101, 107, 116, 122, 128 recovery ten-digit codes, from the first to tenth outputs of which the codes are fed to the information inputs of their drives 96, 102, 108, 117, 123, 129 frame codes.

The operation of the drive codes of the frame, Fig.15, 16, 17.

The code signals in block 96 are supplied to the third inputs of the bits of ten registers 157 / Fig.16/. Filling the registers with row codes begins with the opening of the first key 154 in the first block 153 _{1 of the} registers with the signal U _to 25 Hz. The key 154 passes pulses U _d 27.5 MHz to the input of the distributor 156 pulses, the clock pulses from which are sequentially fed to the first / clock / inputs of the bits in parallel with ten registers 157 _1-10 . By filling the register 157 from the last 1100-th output unit 156 _of the signal U closes switch 154 and a control signal unit 153 in the following _two registers, the registers 157 are filled with codes _1-10 of the second row. Over a period of 40 ms frame, row codes fill in the registers 157 _{1-10 of} all blocks 153 _1-1000 registers / Fig. 15/. From the last block 153 _{1000, the} output signal is sent in parallel to the fourth control inputs of all blocks of 153 registers and opens in them the second keys 155 / Fig.16/, passing one signal U _output , synchronously issuing from all the bits of all registers 157 and in all blocks 153 codes in block 97 of the pulse amplifiers. Each drive 96, 102, 108, 117, 123, 129 has 1.1 × 10 ⁷ outputs that are connected to the same inputs in their respective units 97, 103, 109, 118, 124, 130 of pulse amplifiers. The outputs of three blocks of pulsed amplifiers 97, 103, 109 are connected to the inputs in the first screen 110, the outputs of three blocks 118, 124, 130 of pulsed amplifiers are connected to the inputs in the second screen 131. Signals of code units amplified in pulsed amplifiers and lasting 40 ms are received parallel and synchronously to the respective inputs of their screens 110, 131.

Stereo system operation.

а поперечные размеры корпуса преобразователя "яркость излучения - код" должны соответствовать 18×18 мкм /фиг.4/. Реализация таких размеров в приемниках 3, 17 изображения возможна при участии нанотехнологий. В заявляемой системе формирование цифровых видеокадров осуществляется приемниками изображения на основе преобразователей "яркость излучения - код" при 30-битной глубине цветов правого и левого кадров стереопар, на приемной стороне воспроизведение кадров на двух экранах выполняется без использования строчной и кадровой разверток и приемом зрителя изображения объемным через очки раздельных полей зрения.The receivers 3 and 17 of the image / Fig.1/ synchronously generate the codes of the video signals of the right and left frames of stereo pairs. The pulses of the bits of the codes are amplified in parallel in blocks 4-6 and 18-20 of pulse amplifiers and in parallel are fed into blocks 7-9, 21-23 of the signal allocation of the highest bit of codes, codes with one significant bit in the code are sent to blocks 10-12, 24-26 encoders, in which the high-order code signal receives a binary code, these codes are received in parallel form in blocks 13-15 and 27-29 registers. From register blocks, four-bit codes with a sampling frequency of 27.5 MHz are output to their encoders 30-35, which compress the code streams with a coefficient of 4 per frame, the frequency of issuing codes from encoders 30-35 to 6.875 MHz. The compressed code streams are respectively supplied to the first and second information inputs of the code stream generator 36, which converts parallel codes into serial ones with replacing unit symbols from pulses with positive and negative half-sinusoids of the 110 MHz monofrequency. The third and fourth inputs of block 36 receive 16-bit codes of sounds from the ADC 40 and 41. The stream of codes from the first output of block 36 is a modulating signal in the amplitude modulator 44. The lower side frequency of 1650 MHz is modulated by half-sine signals of the codes, amplified and transmitted to the air, occupying the 330 Hz band in it. At the receiving side, the radio signals are received by block 87, are detected by a bipolar amplitude detector 89/12 /, from the outputs of which the half-sinusoids are formed by pulse shapers 90 and 111 into positive pulses and with a duration equal to the pulse duration on the transmitting side. From the outputs of the pulse shapers 90, 111 pulses of the codes are transmitted to the corresponding first 91 and second 112 receiving registers, from which the codes are distributed through their channels of color signals R ₁ , G ₁ , B ₁ and R ₂ , G ₂ , B ₂ , in which the decoders the compressed streams are restored, the blocks 95, 101, 107, 116, 122, 128 restore the initial decimal codes, and the frame code drives concentrate all frame codes during the first frame of 40 ms, with the arrival of a leading edge of the pulse of 25 Hz frame, all frame codes of three colors synchronously issued in blocks of pulse amplifiers, in oryh amplified pulses code bits are generated for the duration of 40 ms and outputted in their screens 110, 131. The reproduced video mode is 1100 × 1000 × 25 Hz. The viewer perceives from two screens of the image surround through the glasses 140 separate fields of view. If you use image receivers 3, 17 with a frame format of 40 × 40 mm and a frame resolution of 1100 × 1000 in the photomultiplier, then the dimensions of one element / triad / matrix will be 36 × 36 μm

and the transverse dimensions of the transducer housing "radiation brightness - code" must correspond to 18 × 18 microns / 4 /. The implementation of such sizes in receivers 3, 17 of the image is possible with the participation of nanotechnology. In the inventive system, the formation of digital video frames is carried out by image receivers based on converters "radiation brightness - code" at 30-bit color depth of the right and left frames of stereo pairs, on the receiving side, frames are displayed on two screens without using horizontal and frame scans and surround image viewer reception through glasses of separate fields of vision.

Information sources

1. RF patent No. 2410846 C1, cl. H04N 7/00, bull. 3 from 01/27/11, prototype.

2. RF patent No. 2356179 C1, cl. H04N 15/00, bull.14 from 05.20.09, analogue, p.6, fig.5, 6, p.7 of fig.10.

3. Kolesnichenko OV, Shishigin I.V. PC hardware. 5th ed., St. Petersburg, 2004, p. 830-832.

4. V.N. Tutevich. Telemechanics. M., 1985, 2nd ed., P. 202, fig. 8.1.

5. V.I. Ilyin. Remote control and telemetry. M., 1982, p. 269, 274, Fig. 9.7.

6. Patent No. 2298297 C1, cl. H04N 5/00, bull. 2 from 04/27/07, analogue, p. 5, Fig. 7.

7. Radio transmitting devices. M.S. Shumilin, M, 1981. p. 234-235.

8. B.N. Begunov, N.P. Zakaznov. Theories of optical systems. M., 1973, p.223.

9. Digital integrated circuits. Directory. Minsk, 1991, p. 279, 428, 433.

10. A.F. Polonsky, V.I. Thearo. Piezoelectronics. M., 1979, p. 27.

11. Radio communications, broadcasting and television. Ed. A.D. Fortushenko. M., 1981, p. 146.

12. V.F. Barkan, V.K. Zhdanov. Amplification and impulse technology. M., 1981, p. 209.

Claims (1)

A stereo television system containing a transmitting side as part of a photoelectric converter (PEC) including the first and second lenses, first to sixth encoders, a code stream shaper, first and second self-propelled pulse distributors (SRI), the first and second ADCs of sound signals to the information inputs of which sound signals are supplied, of a series-connected frequency synthesizer and a radio signal transmitter from a series-connected carrier frequency amplifier, an amplitude modulator, the second input of which it is connected to the first output of the code stream former and the information amplifier of the code stream former is connected: the first to the outputs of the first and third encoders, the second to the outputs of the fourth and sixth encoders, the third and fourth are connected to the outputs of the first and second ADC audio signals, respectively , fifth and sixth - to the outputs of the first and second SRIs, respectively, the second output of the code stream generator is connected to the input of the first SRI, the outputs of the frequency synthesizer are connected: the first (25 Hz) to the corresponding input of the photomultiplier, to the fourth the first control input of the code stream generator and to the control input of the second SRI, the second to the combined control inputs of the encoders, the first control input of the code stream generator and the combined first control inputs of the first and second ADC audio signals, the third to the combined third control inputs of the first and the second ADC of the sound signals, the fourth to the second control input of the code stream former, the fifth to the third control input of the code stream former and to the combined second control inputs the first and second ADCs of sound signals, the sixth - to the corresponding input of the photomultiplier, the seventh - to the input of the carrier frequency amplifier of the radio signal transmitter, containing the receiving side as part of the control unit (channel selection), the path for receiving and processing video signal codes, including the antenna connected in series, the receiving unit radio signals, the group of the second control inputs of which is connected to the first group of outputs of the control unit, a radio frequency amplifier and a bipolar amplitude detector, a first channel for processing video signal codes c, including a first pulse shaper connected in series, the input of which is connected to the first output of a bipolar amplitude detector, a first receiving register and three color signal channels: signal channel R _one signal channel G _one signal channel B _one each of which includes a register and a decoder connected in series, a frame code storage device and a pulse amplifier unit, comprising pulse amplifiers in terms of the number of outputs from the frame code storage device, a second video signal processing channel, including a second pulse shaper connected in series, the input of which is connected to the second the output of a bipolar amplitude detector, a second receiving register and three color signal channels: signal channel R ₂ signal channel G ₂ signal channel B ₂ each of which includes a register and a decoder connected in series, a frame code storage device and a pulse amplifier unit containing pulse amplifiers in terms of the number of outputs from the frame code storage device, the receiving side contains the first and second flat-panel screens, glasses of separate fields of view, a channel for generating control signals , the first and second channels of sound reproduction, the channel for generating control signals includes a series-connected block for selecting horizontal sync pulses (C I), the information input of which is connected to the output of the first pulse shaper, a frequency synthesizer, the second control inputs of which are connected to the second group of outputs of the control unit, a key, a pulse counter and a decoder, and a frame sync pulse allocation unit (CSI), the input of which is connected to the output of the second pulse shaper, the signal input of the key is connected to the first output of the frequency synthesizer, the first control input U _from key is connected to the output of the block allocation SSI, the second control input U _s key and control U _about the pulse counter input is combined and connected to the second output of the decoder, the information input of the first sound reproduction channel is connected to the output of the first pulse shaper, the information input of the second sound reproduction channel is connected to the output of the second pulse shaper, the first and fourth control inputs of both sound reproduction channels are paired and connected: the first to the first output of the decoder, the second to the second output of the decoder, the third to the second output of the frequency synthesizer, four the third output of the frequency synthesizer, the first output of which is connected to the combined second control inputs of the first and second receiving registers, the combined first control inputs of which are connected to the second output of the frequency synthesizer, the control inputs of the registers of the three signal channels R _one , G _one , AT _one , three channels of R signals ₂ , G ₂ , AT ₂ and the first control inputs of the decoders of the three channels R _one , G _one , B _one and three channels of R signals ₂ , G ₂ , B ₂ connected to the first output of the frequency synthesizer, the fourth output of which is connected to the combined second control inputs of the decoders of the three signal channels R _one , G _one , AT _one and three channels of R signals ₂ , G ₂ , B ₂ and to the combined third control inputs of the drive codes of the frame code of the three channels R _one , G _one , AT _one and three channels of R signals ₂ , G ₂ , B ₂ , the combined first and second control inputs of the frame code storage devices of the same channels are connected to the outputs of the SSI allocation block and the CSI selection block, the fifth output of the frequency synthesizer is connected to the third input of the radio signal receiving unit, the frame code drives are identical, each contains register blocks by the number of lines ( 1000) in the frame, the information inputs are the bitwise combined inputs of all the register blocks, the control inputs are: the first is the first control input of the first block of registers, the second is the combination second control inputs of register blocks, third - combined third control inputs of all register blocks, each control output of the previous register block is the first control input for each subsequent register block, the control output of the last register block is connected in parallel to the fourth control inputs of all register blocks, drive outputs frame codes are the parallel outputs of all register blocks, register blocks are identical, each includes the first and second keys, the distributor and pulses and registers according to the number of bits in the code, the information input is the bitwise combined third inputs of the bits of all registers, the outputs are the parallel outputs of all bits of the registers, the control inputs are: the first is the first control input of the first key, the second is the signal input of the second key, and the third is the signal input of the first key, fourth - the first control U _from the input of the second key, the output of the first key is connected to the input of the pulse distributor, the outputs of which are sequentially, starting from the first, connected to the first (clock) inputs of the bits in parallel to all registers, the last output is connected to the second control input of the first key and is the control output of the register block, output the second key is connected in parallel to the second inputs of the bits of all registers and to the second control U _s , to the input of the second key, the first and second flat-panel screens are identical, each contains a matrix of elements according to the number of screen resolutions, the matrix element includes an opaque case of the corresponding form, in which three emitting cells are located, the upper one emits green G color, the lower left one emits red R color, the lower right one emits blue. In color, each emitting cell contains a microlens in the input end face, successively arranged along its optical axis, one after another, according to the number of bits in the code, neutral micro filters and contains micropiezoelectric elements according to the number of discharges in the code, one end with two control inputs of the micropiezoelectric element is fixed rigidly in the wall of the matrix element housing, the second free end of the micropiezoelectric element is appropriately attached to its microfilter, and a color filter of one of the primary colors is placed in the output end of the housing (R, G, B), the control inputs of the emitting cell are the control inputs of the micro-piezoelectric elements connected to the outputs of the corresponding pulse amplifiers in accordance blocks of pulse amplifiers, glasses of separate fields of view represent a frame with ear arches, windows of glasses without glasses, interconnected movably to rotate relative to each other in the horizontal plane, each window of glasses has a removable conical hood at the end made to fit the screen, a hood made of two parts: the first part is screwed into the glasses window, the second part is extended and pushed into the first, changing the hood length, the block for selecting horizontal sync pulses (SSI) and the block for allocating frame sync pulses (K I) are identical, each includes a five-digit pulse counter and a decoder connected in series, the output of which is the output of the block, includes the element NOT, the first and second diodes, the information input of the block is the counter input of the pulse counter, the control input is the input of the first diode, the output of which is connected to the control input U _about pulse counter, the decoder output through the second diode is connected to the output of the element NOT, together they are connected after the first diode to the control input of the pulse counter, the input of the element is NOT connected to the counting input of the pulse counter, the information input of the SSI isolation unit is connected to the output of the first pulse shaper, its control the input is connected to the output of the second pulse shaper, the information input of the CSI selection unit is connected to the output of the second pulse shaper, the control input of which is connected to the output the first pulse shaper, characterized in that on the transmitting side the photoelectric converter is made up of series-connected first image pickup, the receiving side of which is located in the focal plane of the first lens, and three groups of outputs of three color signals R _one , G _one , B _one , in each of which exits by the number of resolutions of the image receiver and the number of bits in the code 1.1 · 10 ⁷ (1100 · 1000 · 10) are connected in parallel to the same inputs of three color signals, respectively, in the first to third blocks of pulse amplifiers, the outputs from each of which are connected to the corresponding as many inputs of the first or third blocks of the signal allocation of the highest order code, outputs (1, 1 · 10 ⁶ ) from each of which are connected to as many inputs of the corresponding first to third blocks of encoders, the outputs from each of which are 4 · 1,1 · 10 ⁶ connected to as many inputs of the corresponding first to third blocks of registers, the first to fourth outputs from each of which are the first to third information outputs of the photomultiplier tubes, which are connected to the first to fourth inputs of the corresponding first to third encoders, and as part of a second image receiver connected in series, the receiving side of which is located in the focal plane of the second lens, and three groups of outputs of three color signals R ₂ , G ₂ , B ₂ in each of which outputs on the resolution of the image receiver and the number of bits in the code 1.1 · 10 ⁷ (1100 · 1000 · 10 bits) are connected in parallel to the same inputs in the fourth to sixth blocks of pulse amplifiers, the outputs from each of which are 1.1 · 10 ⁷ connected to the same number of inputs of the fourth to sixth blocks of the signal allocation of the highest order code, outputs 1.1 · 10 ⁶ from each of which are connected to as many inputs of the corresponding fourth to sixth blocks of encoders, the outputs from each of which are 4 · 1,1 · 10 ⁶ connected to as many inputs of the corresponding fourth to sixth blocks of registers, the first to fourth outputs from each of which are the fourth to sixth information outputs of the photomultiplier tubes, which are connected to the first to fourth inputs of the fourth to sixth encoders, respectively, the first control inputs (25 Hz) of the first the sixth register blocks are combined and connected to the first output of the frequency synthesizer, the sixth output (27.5 MHz) of which is connected in parallel to the second control inputs of the first to sixth register blocks, the first and second reception iki images are identical, each comprising a matrix of 1,1 · 10 ⁶ elements, each matrix element is represented by a triad of three transducers "radiation brightness - code", the lower left transducer receives red R radiation, the upper transducer receives green G radiation, the lower right transmits blue B radiation, the transducers "brightness radiation - code" are identical, each includes an opaque case of the corresponding form made of insulating material, in the front end of the case there is a color filter of one of the primary colors (R, G, B), behind a color filter in an opaque A micro-lens is fixed to the rim, along the optical axis of which and at an angle of 45 ° to it, sequentially translucent micro-mirrors are placed and rigidly mounted from the first to the tenth micro-mirrors, on the side of the housing to which the micro-mirrors are rotated according to the number of bits in the code there are ten corresponding photodetectors receiving reflected from micromirrors of radiation, the outputs of photodetectors are the first to tenth outputs of the converter "radiation brightness - code", the principle of conversion: each translucent mi located in front the mirror passes to the radiation stream following it, twice weakened, the translucent micromirror contains a beam splitting coating, which fulfills the ratio of reflected radiation to the transmitted one as 1: 0.5, the number of translucent micromirrors corresponds to the receipt of ten-digit codes, the first to sixth blocks of pulse amplifiers are identical each includes pulse amplifiers according to the number of resolutions of the image receiver and the number of bits in the code, the total outputs from the block of pulse amplifiers 1.1 · 10 ⁷ , the first to sixth blocks of the signal selection of the highest order code are identical, each contains decoders for the number of resolution of the image receiver 1.1 · 10 ⁷ , the decoder includes an eleven-bit register, the first bit of which is zero, no signals arrive at it, ten-bit codes in parallel form arrive at the first to tenth bits of the register, the first bit is senior, the tenth is the least significant, the output of the zero bit of the register is connected to the input of the first element NOT, the output which is connected to the first input of the first element And _one , the output of the first category of the register is connected to the input of the second element NOT, the output of which is connected to the first input of the second element AND ₂ and to the input of the third element is NOT, the output of which is connected to the second input of the first element AND _one , the output of the second category of the register is connected to the input of the fourth element is NOT, the output of which is connected to the first input of the third element AND ₃ and to the input of the fifth element is NOT, the input of which is connected to the second input of the second element AND ₂ , the output of the third category is connected to the input of the sixth element is NOT, the output of which is connected to the first input of the fourth element AND _four and to the input of the seventh element is NOT, the output of which is connected to the second input of the third element AND ₃ , the output of the fourth category of the register is connected to the input of the eighth element NOT, the output of which is connected to the first input of the fifth element AND ₅ and to the input of the ninth element is NOT, the output of which is connected to the second input of the fourth element AND _four , the output of the fifth category is connected to the input of the tenth element is NOT, the output of which is connected to the first input of the sixth element AND ₆ and to the input of the eleventh element is NOT, the output of which is connected to the second input of the fifth element AND ₅ , the output of the sixth digit of the register is connected to the input of the twelfth element NOT, the output of which is connected to the first input of the seventh element AND ₇ and to the input of the thirteenth element is NOT, the output of which is connected to the second input of the sixth element AND ₆ , the output of the seventh digit is connected to the input of the fourteenth element is NOT, the output of which is connected to the first input of the eighth element And ₈ and to the input of the fifteenth element NOT, the output of which is connected to the second input of the seventh element And ₇ , the output of the eighth digit is connected to the input of the sixteenth element is NOT, the output of which is connected to the first input of the ninth element AND ₉ and to the input of the seventeenth element is NOT, the output of which is connected to the second input of the eighth element AND ₈ , the output of the ninth category is connected to the input of the eighteenth element is NOT, the output of which is connected to the first input of the tenth element AND ₁₀ and to the input of the nineteenth element is NOT, the output of which is connected to the second input of the ninth element AND ₉ , the tenth digit output is connected to the input of the twenty element NOT, the output of which is connected to the input of the twenty-first element NOT, the output of which is connected to the second input of the tenth element AND ₁₀ , the first to sixth blocks of the encoders are identical, each encoder in the block encrypts decimal numbers from zero to ten, the encoders in the block according to the resolution number of the image receiver 1.1 · 10 ⁶ , the first to sixth register blocks are identical, each register block contains 1.1 · 10 ⁶ four-digit registers and series-connected key and pulse distributor, each having 1.1 · 10 ⁶ outputs, information inputs of the register block are the first to fourth inputs of each register, total inputs 4 · 1,1 · 10 ⁶ , the outputs of all the registers are bitwise combined, the first to fourth outputs are the outputs of the register block, the first control input is the control input of the 25 Hz key connected to the first output of the frequency synthesizer, the second control input is the signal input (27.5 MHz) of the key connected to the sixth the output of the frequency synthesizer, on the receiving side, the first and second receiving registers are made fifteen-bit, the registers in the color signal channels R _one , G _one , AT _one and R ₂ , G ₂ , B ₂ made five-bit and connected in the signal channels R _one , G _one , B _one to the outputs, respectively 1-5, 6-10, 11-15 of the first receiving register, in the signal channels R ₂ , G ₂ , B ₂ to the inputs 1-5, 6-10, 11-15 of the second receiving register, respectively, a decryptor and a ten-digit code recovery unit are connected in series to each color signal channel, the first to fourth decoder inputs in each channel are connected to the first to fourth outputs of its decoder, the first to tenth outputs of the decoder are connected to the first to tenth inputs of the ten-digit code recovery unit, the first to tenth outputs of which are connected to the first to tenth information inputs of the channel code frame storage unit, block and recovery of ten-digit codes are identical; each includes ten inputs, nine groups of diodes and ten outputs, the first group of one diode, the input of which is connected to the first (senior) block input, the diode output is connected to the second output of the block, the second group of diodes from two diodes, their outputs are combined and connected to the third output of the block, and their inputs are connected separately to the first and second inputs of the block, the third group of three diodes, their combined outputs are connected to the fourth output of the block, and the inputs are separately connected to the first or third inputs of the block, the fourth group of four iodines, their outputs are connected to the fifth output of the block, and the inputs of the diodes are connected separately to the first to fourth inputs of the block, the fifth group of five diodes, their combined outputs are connected to the sixth output of the block, the inputs of the diodes are connected separately to the first to fifth inputs of the block, the sixth group of six diodes, their combined outputs are connected to the seventh output of the block, the inputs are connected separately to the first to sixth inputs of the block, the seventh group of diodes of seven diodes, their combined outputs are connected to the eighth output of the block, and the inputs are separately connected are the first to eighth inputs of the block, the ninth group of nine diodes, their combined outputs are connected to the tenth output of the block, and the inputs are separately connected to the first to ninth inputs of the ten-digit code recovery block, the first to tenth outputs of each ten-bit code recovery block are connected to the first to the tenth information inputs of the channel frame code drive, a diaphragm having cylinders is inserted into each element of the matrix of the first and second flat-panel screens between the microlens and the color filter A housing with slots in the number of discharges in the code, in which there are executing elements represented by translucent neutral microfilter filters along the optical axis of the microlens, of which each translucent neutral microfilter attenuates the radiation flux from the microlens in the number of discharges in the code, appropriately attached to the free ends of its micropiezoelectric elements according to the principle of the binary code twice, the irradiation of microlenses of all emitting cells is performed by superbright white LEDs about luminescence, arranged in the appropriate amount and in the appropriate order on the back side inside the housing a flat panel display.

Images