RU2358412C1 - Video camera - Google Patents

Abstract

FIELD: physics; image processing.

SUBSTANCE: present invention relates to home digital video, and can be used for recording and playing back video. Technical outcome is achieved by that the video camera contains two switches, a self-powered pulse distributor, and three OR elements. There are two CID matrices in the photoelectric transducer and there is a unit for selecting clock pulses of stereopairs in the playback device. In each channel of the playback device, there is an accumulator of frame codes and a generator of control signals. The device for displaying video is a flat-panel light-emitting diode screen.

EFFECT: simple design of photoelectric transducer and doubling of frame resolution.

10 dwg, 2 tbl

Description

The invention relates to household digital video equipment, can be used to record and play video information. The prototype adopted "Camcorder" [1], containing the right and left lenses, a photoelectric converter / photomultiplier /, which is a sensor of video signals of two images of the same space and includes three piezoelectric reflectors with reflectors at their ends, three amplifiers, voltage reference sources, horizontal and vertical scanning units , four dichroic mirrors, six micro-lenses, six photodetectors, six pre-amplifiers, and containing six ADCs of a video signal, two ADCs of a sound signal, frequency synthesizer, first key, trigger, second d and third keys, from the first to the sixth encoders, two encoders of a sound signal, five blocks of AND elements, a video detector, a digital information storage device and a playback device that contains a frequency synthesizer, three channels of R, G, B signals, two sound channels, an AND element and a key, an IR transmitter on the case of a digital monitor, ZD glasses with an IR receiver on the frame of glasses. The channels of the signals R, G, B are identical, each includes a key and a serial decoder, a processing / doubling / code unit and a pulse amplifier unit, the outputs of which are connected to the inputs of a digital monitor. Video mode when receiving video information 400 _samples × 600 _pages × 50 Hz, video mode when playing 800 _samples × 600 _lines × 50 Hz, frame resolution 480000 pixels / 800 × 600 /. The disadvantages of the prototype are: the design of the photomultiplier requires maintaining precise alignment during operation, insufficient resolution of the frame / 800 × 600 /.

The purpose of the invention is to simplify the photomultiplier and double the resolution of the frame. The technical results are the simplification of the photomultiplier construction by introducing into it two FDI arrays / charge-injection devices made using Foreon X3 technology [2 p. 522] / with the exception of piezoelectric deflectors and horizontal and vertical scanning blocks from the photomultiplier, doubling the resolution of the frame / 1200 × 800 / by introducing into each channel the signal R, G, B of the frame code accumulator and the driver of the control signals, and by presenting the video information display device with a flat-panel LED screen / LED screen /. The essence of the invention is that in a video camera containing the first and second lenses, photomultiplier tubes, three ADCs of a video signal, three encoders, three blocks of AND elements, a frequency synthesizer, three keys and a trigger, a digital information storage device and a playback device including a frequency synthesizer, three channels R, G, B signals, each of which includes a key, a decoder and a code processing unit, and a video information display device with an IR transmitter, ZD glasses with an IR receiver on the frame, two keys are entered, a self-propelled pulse distributor / SRI /, three element OR in PE Two FDI arrays are inputted, and the seventh key and a stereo pair / SIS / sync pulse extracting unit are introduced into the playback device, and a frame code accumulator and a driver of the control signals are introduced into each channel of the R, G, B signal, the video information display device is represented by a flat-panel LED screen / LED -screen/. An image of one space will be formed in the video camera in two successive right and left frames making up a stereo pair. The frequency of stereo pairs is 25 Hz, the frame rate is 50 Hz / 25 + 25 /.

Video mode in the camcorder: 600 _counts × 800 _lines × 50 Hz. The received information in each frame is compressed over a frame period of 4 times / or more / and is recorded in a digital information storage device. During playback, the digital information storage device is connected to a playback device in which the compressed information is restored, the number of samples in each row is doubled. The signal codes of each frame are concentrated for the frame period in three frame code storage devices, the frame pulse of the next frame synchronously generates R, G, B codes in three shapers of control signals that convert the value of each code into the corresponding number of pulses from the LEDs in the LED screen.

The scheme of the video camera in Fig. 1, the playback device in Fig. 2, the frame code storage in Fig. 3, the register block in Figs. 4 and 5, the SIS allocation block in Fig. 7, the control signal generator in Fig. 6, the SD cell in Fig.8, the radiating element of the matrix in Fig.9, the location of the radiating elements in the LED screen of Fig.10. The sampling frequency of the video signal codes is

f _ADC = 800 _lines × 600 _count × 50 Hz = 24 MHz,

where: 800 - the number of encoded lines in the frame,

600 is the number of encoded samples per line,

50 Hz - frame rate: 25 right + 24 left.

Тактовая частота при последовательном следовании кодов в последовательном виде в сжатом потоке:

Line frequency f _c = 800 × 50 Hz = 40 kHz. The smallest compression ratio of the frame code stream is assumed to be 4. Sample rate of codes in a compressed stream of 6 MHz

The clock frequency when sequentially following the codes in sequential form in a compressed stream:

- число отсчетов в строке в сжатом потоке кодов,Where:

- the number of samples per line in the compressed stream of codes,

9 times - the number of bits in the code at the output of each encoder.

Video mode during playback: 800 _pages × 1200 _ots × 50 Hz, frame resolution 960000/1200 × 800 / pixels.

20 мс - длительность кадра, 255 - разрешение 8-разрядного кода, число выходов с блока 80. С приходом кода в дешифратор 77 сигналы с его выходов открывают соответствующие ключи в блоке 78, которые последовательно пропускают на вход выходного ключа 79 с соответствующих разрядов блока 80 сигналы U_от, и светодиод в СД-экране за период кадра выдает соответствующее число импульсов излучений, следующие друг за другом через равные интервалы времени. Чем больше величина кода, тем больше импульсов излучений выдает светодиод за период кадра. Пример распределения импульсов излучений в периоде кадра приведен в таблице 1.The video camera includes / Fig. 1/ first / right / lens 1, second / left / lens 2, photoelectric converter 3 / FEP /, which is a sensor of video signals in two images of the same space and generating three video signals of the right frame R _P , G _P , V _P and three video signals of the left frame R _L , G _L , V _L , and contains the first FDI matrix 4, the photosensitive side of which is located in the focal plane of the first lens 1, the second matrix 5, the photosensitive side of which is located in the focal plane of the second lens 2. FDI matrix - P charge injection probe using Foreon X3 technology from a three-layer CMOS sensor [2 p.552] and [3 p.832, 833, 835] with the corresponding optical resolution / not less than 800 × 600 /, the first, second and third outputs of the FDI matrix 4 are connected to the first inputs of the pre-amplifiers 6, 7, 8, the first and third outputs of the FDI matrix 5 are connected to the second inputs of the pre-amplifiers 6, 7, 8, the outputs of which are the first and third outputs of the photomultiplier. The video camera includes the first 9, second 10, third 11 ADCs of the video signal R, G, B, identical to the ADCs in the prototype [1 p.4, 5, Fig. 5], first 12, second 13, third 14 encoders, identical to the encoders in prototype [1 p.5, 10], the first 15, second 16, third 17 blocks of elements And, also made identical to the same blocks in the prototype [1 p.22, Fig.9], the outputs of which are connected to the first inputs, respectively 18, 19, 20 elements OR, frequency synthesizer 21, serially connected first key 22 and trigger 23, second key 24, third key 25, fourth key 26 and fifth key entered yuch 27 and a self-propelled pulse distributor 28 / SRI /, the output of which is connected in parallel to the second inputs of the OR elements 18, 19, 20, includes a video detector 29, serially connected to the first ADC 30 of the sound signal, the first encoder 31 of the sound signal and the first block 32 of the And signal elements sound, sequentially connected to the second ADC 33 of the sound signal, the second encoder 34 of the sound signal and the second block 35 of the And elements of the sound signal, the drive 36 of digital information and the device 37 playback. The self-propelled pulse distributor 28 has nine discharges, the outputs of which are combined, the combined output is connected in parallel to the second inputs of the OR elements 18, 19, 20. When a self-propelled distributor of 28 pulses / SRI / starting pulse of 25 Hz arrives at the input, it gives a code of nine units 111111111, being a sync pulse of SIS stereopairs. Three SIS codes simultaneously arrive at the first to third inputs of block 36 and are the first code in each stereo pair. The playback device 37 / FIG. 2/ contains a frequency synthesizer 38, a sixth 39 and a seventh 40 keys, a newly-introduced SIS stereo pair sync pulse extracting unit 41, a signal channel R including a first key 42 and a first decoder 43 connected in series, a first code processing unit 44, the first drive 45 of the frame codes and the first driver 46 of the control signals, the signal channel G, including the second key 47 and connected in series to the second decoder 48, the second unit 49 of the code processing, the second drive 50 of the code codes and the second driver 51 of the control signals, a signal channel B including a third key 52, and a third decoder 53, a third code processing unit 54, a third frame code storage 55 and a third control signal generator 56 connected in series, comprises a first sound channel including a fourth key 57 connected in series to decoder 58 sound codes, sound signal register 59, analog sound signal generating unit 60 and loudspeaker 61, second sound channel including fifth key 62, sound code decoder 63 connected in series, sound signal register 64, forming unit 65 The analogue sound signal and loudspeaker are 66, and includes a flat-panel LED screen 67 with an IR transmitter 68 on the housing of the LED screen, ZD glasses 69 and an IR receiver 70 on the frame of the ZD glasses. The decoders 43, 48, 53 are identical to the decoders in the prototype [1 p.5, 11], the decoders 63, 58 of the sound codes are made similarly to the decoders in the prototype. Blocks 44, 49, 54 of the code processing are identical to the same blocks in the prototype [1 c.6, 11, Fig.12]. The drives 45, 50, 55 of the frame codes are identical, each includes / Fig. 3/ connected in series blocks of 71 registers, of which 800 by the number of lines in the frame, i.e. 71 _1-800 . The information input of the block 45/50, 55 / are the bitwise combined first - eighth inputs of all blocks 71 _1-800 registers. The outputs are the outputs of all the blocks of registers 71, only outputs 7.68 × 10 ^6/1200 × 8 × 800 /. The control inputs are: the first is the first control input / 50 Hz / of the first block 71 ₁ registers, the second is the combined second control inputs / U _output 40 kHz / blocks 71, the third is the combined third control inputs / U _d 48 MHz / blocks 71 / fig .3 /. The control input of each previous block 71 registers is the first control input for each subsequent block 71 registers. The control output of the last / 800th / block of registers is connected in parallel to the fourth control inputs of all blocks of 71 registers. The blocks 71 of the registers are identical, each includes / Fig. 4, 5 / the first 72 and the second 73 keys, the distributor 74 pulses and eight registers 75 _1-8 , each of which contains 1200 bits / according to the number of samples in the line /. The information inputs 1-8 of the block 71 of the registers are bitwise combined first to eighth of the third bits of eight registers 75. The outputs are the parallel outputs of all bits of the eight registers 75, total outputs 9600/1200 × 8 /. The outputs of 800 blocks of 71 registers are the outputs of each drive 45, 50, 55 frame codes. The control inputs are: the first is the first control input / 50 Hz / of the first key 72, the second is the signal input / U _output 40 kHz / second key 73, the third is the signal input / U _d 48 MHz / first key 72, the fourth is the first control input the second key 73. The output of the key 72 is connected to the input of the pulse distributor 74, the outputs of which are connected in series from the first to the 1200th to the first / clock / bit inputs in parallel of eight registers 75. The last output of the block 74 is connected to the second control input of the first key 72 and is control output bl Single 71 and connected to the first control input of switch 72 in the next block 72 /fig.5/. The output of the second key 73 is connected in parallel to the second inputs of the bits of the eight registers 75 and to the second control input of the key 73, the last pulse U _output closes the key 73. The outputs of the drives 45, 50, 55 frame codes are connected (Fig. 2/) to the information inputs of the drivers 46 , 51, 56 control signals of their channels, the purpose of which is to perform the conversion "code - the number of pulses of radiation" to obtain the duty cycle of the radiation of each LED for the period of the frame, respectively, the code value of the color signal. Each of blocks 46, 51, 56 includes (Fig. 6/) a pulse shaper block 76 containing identical pulse shaper circuits by the number of converters and whose input is a control input U _to 50 Hz, and contains code-to-number radiation pulse converters by number samples per line 1200 and the number of lines per frame 800, i.e. 960000/1200 × 800 /. The converters are identical, each of them includes (Fig. 6/) decryptor 77 connected in series, the first to eighth information inputs of which are also the information inputs of the control signal generator, key block 78 of 255 keys and output key 79, includes a self-propelled pulse distributor 80 / SRI / and a single LED power supply 81 in the LED screen. 255 outputs of the decoder 77 are connected to the first control inputs U _{from the} corresponding keys in the key block 78, the outputs of the keys are combined and connected to the control input U _{from the} output key 79, the signal input of which is connected to the output of the power supply 81. The input of the SRI 80 is connected to its output in the block 76 of the pulse shapers and has 255 bits, the outputs of which are connected to the signal inputs of the corresponding 255 keys in the block 78 / input 2 /. The information inputs of block 46/51, 56 / are the information inputs of all decoders 77, the outputs of all output keys 79 are the outputs of block 46/51, 56 /, which are connected to the corresponding inputs of the LED screen 67 / Fig. 2/. The initial state of the output keys 79 and keys in blocks 78 is closed. The control input of block 46 receives a signal U _to 50 Hz, which is supplied in parallel to the inputs of all pulse shaper circuits, which generate pulses of the corresponding amplitude and duration, which are triggering U _p for SRI 80. Each pulse from block 78 of the keys opens the output key 79 for a period of 78 μs:

20 ms is the frame duration, 255 is the resolution of the 8-bit code, the number of outputs from block 80. When the code arrives at the decoder 77, the signals from its outputs open the corresponding keys in block 78, which are sequentially passed to the input of the output key 79 from the corresponding bits of block 80 U signals _from , and the LED in the LED screen for the period of the frame gives the corresponding number of radiation pulses, following each other at equal time intervals. The larger the code value, the more pulses of radiation the LED emits for the frame period. An example of the distribution of radiation pulses in the frame period is given in table 1.

Table 1 Decoder Input Code 77 The distribution of radiation pulses in the frame period The number of emissions per frame

0 - absence of a radiation pulse,

1, 2, 3 - 255 - sequential sequence of emissions in the frame period. Following radiation pulses in the frame at appropriate equal time intervals creates natural conditions for human vision to perceive image brightness and color accuracy. The response inertia is accepted up to I μs. Upon completion of the accumulation of the frame codes by blocks 45, 50, 55, all R, G, B codes are synchronously issued to blocks 46, 51, 56, where they are converted to the number of supply voltage to the LEDs of the LED screen 67. Modern technologies allow each of the blocks to be executed 45, 55, 50, 46, 51, 56 with a single chip. The SIS isolation block 41 includes / Fig. 7/ first 82, second 83, third 84 pulse counters, the counting inputs of which are the first - third inputs of block 41, the first 85 and second 86 elements AND, the first 87, second 88, third 89 elements NOT and diode. The outputs of the first and second pulse counters 82, 83 are connected to the inputs of the And 85 element, the output of which and the output of the third pulse counter 84 are connected to the inputs of the second And 86 element, the output of which is the output of block 41. The inputs of the elements are NOT connected to the counting inputs of the first or third counters 82, 83, 84 pulses, the outputs of the elements NOT and the output of the AND 86 element through the diode are combined and connected in parallel to the control inputs of the pulse counters 82, 83, 84. The flat-panel LED screen 67 represents a set of radiating elements in the matrix of the number of permits frame 960000, which are carried out in glass LED screen. The LED screen includes a glass screen and a matrix of radiating elements according to the number of frame resolutions / 1200 × 800/960000 pixels. Each emitting element includes / Fig. 9 / three LED cells / LED cells /, each of which emits one of the primary colors R, G, B. The LED cell contains / Fig. 8/ a white LED 90 and the corresponding color filter 91 on the radiating side. Three LED cells constitute a radiating element (Fig. 9), the arrangement of which in the LED screen of FIG. 10. The brightness level of the radiation of the LED cell is proportional to the number of pulses of the LED radiation over the frame period, which can be from 1 to 255, occupying from 78 μs to 20 ms. The total emission of the three primary colors by three LED cells forms the brightness and color tone of one pixel of the screen. As LEDs, superbright LEDs of the type manufactured by Nichia, Ledtronics, Kingbright [4 p47], but with a diameter of up to 0.5 mm / Fig. 8/, and better LEDs developed using PLED technology using LEDs with polymer organic molecules [5 p. 43]. LEDs are made in glass / or in film / using microelectronic technology. With the size of one radiating element 1 × 1 mm / Fig. 9/, the dimensions of the LED screen are: horizontal 1200 × 1 mm = 1200 mm, vertical 800 × 1 mm = 800 mm, diagonal 1442 mm or 56.7 inches. The photoelectric converter 3 matrices PZI 4 and 5 generates three analog color signals of the right image and three analog color signals of the left image. In the first frame period / 50 Hz / 24 MHz pulses of reading the R, G, V pixels horizontally [3 p.832], they come from key 24 to the second input of the FDI 4 and 40 kHz matrix from key 26 to the first input of the FDI 4 matrix for reading signals vertically. Analog video signals from the first to third outputs of the FDI matrix 4 are fed to the first inputs of the preamplifiers 6, 7, 8. At the second frame, 24 MHz and 40 kHz pulses are sent from the keys 25 and 27, respectively, to the second and first inputs of the second FDI matrix 5 for reading signals pixels. Analog video signals from 1-3 outputs of the second FDI matrix 5 are fed to the second inputs of the preamplifiers 6, 7, 8. Alternating, the analogue color signals of the right and then left frames of the stereo pair are fed to the ADC inputs 9, 10, 11. The sequence in the stereo pair is first set by the key 22 and the trigger 23. The key 22 is opened by the 25 Hz signal of the stereo pair from the eighth output of the frequency synthesizer 21. The public key 22 passes 50 Hz pulses to the trigger 23. With the arrival of the first pulse of 50 Hz, the signal from the first output of the trigger 23 opens the keys 24, 26, the signals are read from the first matrix of the FDI 4. With the arrival of the second pulse of 50 Hz to the input of the trigger 23, the signal from it the second output opens the keys 25, 27, the signals are read from the second matrix of the FDI 5. The ADCs 9-11 convert the analog signals into 8-bit codes, which with a frequency of 24 MHz are supplied in parallel to the inputs of their encoders 12, 13, 14. Synthesizer 21 frequency gives: from the first output pulses 24 MHz sampling deosignals to the signal inputs 24, 25, from the second - frame frequency pulses of 50 Hz to the input of the first key 22 and to the first input of the video signal 29, from the third - sampling pulses of 90 kHz sound signal to the control inputs of the ADC 30, 33 sound signal, from the fourth - clock pulses of 1.53 MHz sound signal to the control inputs of blocks 32, 35 of AND elements and to the first control input of digital information storage 36, from the fifth output 54 MHz clock pulses to the second control input of block 36, from the sixth - 6 MHz pulses U _output control inputs of blocks 15-17 elements And, with the seventh output pulses of 40 kHz line frequencies to the signal inputs of the keys 26, 27 and to the second control input of the video detector 29, from the eighth - the frequency pulses of 45 Hz stereo pairs to the control input of the first key 22 and to the input of the SRI 28. The ADC 33, 30 convert the sound signals into 16-bit codes, which are supplied in parallel to the inputs of encoders 31, 34, C, ADCs 9–11, codes are received respectively by 12–14 encoders, which compress the code stream by performing operations: comparing code values to identify codes of equal size and the following one after another, counting the number code s of equal size, and the formation of a binary code of this number, the introduction of the code of the number of equal codes in the stream after the first code of its sequence and the introduction of a marker / signal into the ninth digit / in this code to identify it during decoding. In the prototype, the compression ratio of the code stream per frame is taken to be 2, i.e. in the range of 2-255 [1 c.8] at a sampling rate of 12 MHz. And the higher the sampling rate of the codes, the more codes of equal magnitude in the stream. In the inventive device, the sampling frequency of the codes is twice as high as 24 MHz, therefore, the smallest compression ratio is taken to be 4. To detect when recovering compressed code information the number of equal codes is entered into it in the ninth digit: eight bits 1-8 are informational, and the ninth one discharge is a service for code recognition during decoding. From encoders 12-14, the codes in parallel form go to the inputs of their 15-17 AND elements, which convert the parallel codes into sequential ones that enter the first inputs of OR elements 18, 19, 20, from the outputs of which the codes go respectively to the first, second, third the inputs of block 36, the fourth and fifth inputs of which come from blocks of elements And 32, 33 are sequential codes of sound signals. The first and second control inputs of block 36 from the fourth and fifth outputs of the synthesizer 21 frequencies receive respectively pulses U _T 1.53 MHz and 54 MHz. To play video information from the drive 36 digital information / 2 / to its third to seventh inputs are connected respectively from the first to fifth control outputs of the device 37 playback. A frequency synthesizer 38 produces: from the first output, 40 kHz pulses to the second control inputs of the drives 45, 50, 55 frame codes, from the second — 48 MHz pulses of double sampling frequency to the third control inputs of the blocks 45, 50, 55, and from the third — clock pulses 54 MHz to the signal inputs of the keys 39, 40 and to the first control inputs of the decoders 43, 48, 53, from the fourth - 24 MHz sampling pulses to the second control inputs of the decoders 43, 48, 53 and to the control inputs of the code processing units 44, 49, 54 , from the fifth - pulses of 1.53 MHz to the signal inputs of the keys 57, 62 and the first unitary enterprise branching inputs of decoders 58, 63, from the sixth - pulses of 90 kHz of sampling the sound signal to the second control inputs of decoders 58, 63, from the seventh output - pulses of U _{to a} frequency of 50 Hz frames to the first control inputs of blocks 45, 50, 55 and to the control inputs shapers of control signals 46, 51, 56. The initial state of the keys 39, 42, 47, 52, 57, 62 is open, the second key 40 is closed. After turning on the power, the key 39 in the open state passes U _T 54 MHz through the public keys 42, 47, 52 to the third and fifth inputs of block 36, issuing the signal codes R, G, B in serial form to the information inputs of decoders 43, 48, 53, in parallel, the codes arrive at 1-3 inputs of the block 41 allocation of the SIS. With the arrival at the inputs of three counters 82, 83, 8 4 / Fig. 7/ SIS codes, a pulse of 25 Hz appears at the output of block 41. With other codes, at least one of them will have an “O”, according to which the pulse counters are not reset from any element, and there will be no false SIS at the output of block 41. The signal 25 Hz / SIS / binds the first pulse of 54 MHz / U _vyd / to the beginning of the right frame of the stereo pair, closes the key 39, opens the key 40, which passes 54 MHz pulses through the public keys 42, 47, 52 to the third-fifth control inputs of block 36 issuing codes R, G, B to the inputs of decoders 43, 48, 53, restoring compressed code streams by performing operations: determine the code for the number of equal codes, decode it to generate the number of signals for issuing the first code by the number of codes removed, issue the first sequence code by the number seized codes. From the outputs of the decoders, the reconstructed code streams go to their code processing units 44, 49, 54, which double the number of samples per line from 600 to 1200, and obtain intermediate / average / codes between each passing code and the one that follows it. From the outputs of blocks 44, 49, 54, the codes go with a frequency of 48 MHz to the first and eighth information inputs of drives 45, 50, 55 frame codes. With the arrival of a pulse of 25 Hz / SIS / at the input of the IR transmitter 68, it emits an IR pulse received by the IR receiver 70/2 /. The IR receiver provides a control signal to the LCD cell of the left glass of the ZD glasses, dimming it for 20 ms, then it outputs a second control signal to the LCD cell of the right glass, dimming it for 20 ms: each eye sees its own frame. The glasses of the ZD glasses are made using the technology of LCD cells of the translucent type, used as electronically controlled filters / shutters / [3 p.558].

The operation of the blocks of registers, Fig.3, 4, 5. Signals of the codes are fed to the third inputs of the bits of eight registers 77/4 /. The filling of the registers with the codes of the first line begins with the opening of the first key with a signal U _to 50 Hz in the first block 71 _{1 of the} registers / Fig. 4/, the key 72 passes 48 MHz sampling pulses to the input of the pulse distributor 74, the clock pulses from which are fed sequentially to the first / clock / bit inputs parallel to eight registers 75. By filling in the registers 75 from the last output of the / 1200th / block 74, the U ₃ signal closes the key 72 and opens the key 72 in the next block _{2 of 2} registers, the registers of which are filled as a control output signal are the codes of the second line. Over a period of 20 ms frame registers 75 of all blocks 71 _1-800 registers are sequentially filled with codes. From block 71 _{800, the} output signal arrives in parallel to the fourth inputs of all blocks of registers 71 / Fig. 3/ and opens in them the second keys 73 / Fig. 4/, which pass one pulse U _output , which gives out frame codes from all blocks 71 synchronously in shapers 46, 51, 56 of their channels. Each frame code drive 45, 50, 55 has 7.68 × 10 ⁶ outputs / 1200 × 8 × 800 /, which are connected to the same inputs in each of the blocks 46, 51, 56, each of which has 960000 converters / 1200 × 800 / "code - the number of pulses of radiation". The outputs of the three control signals formers 2.88 × 10 ^6/3 × 960000 / are connected to the inputs of the LED screen 67. The pulses U _T 1,53 MHz sound with keys 57, 62 is issued with a sound unit 36 codes input to the decoders 58, 63. The audio signal codes in blocks 60, 65 are converted into analog audio signals that are reproduced by loudspeakers 61, 66. Video detector 29 uses codes from the ADC 9-11 and reproduces a frame of 800 lines with 600 samples in a line with a frequency of 25 Hz,

The operation of the camcorder.

PECs with FDI matrices 4 and 5 generate analog video signals of the right and left frames, converted by the ADC 9-11 with a frequency of 24 MHz into 8-bit codes, which enter the encoders 12-14, which compress the code stream with a coefficient of at least 4 for the frame period. Parallel codes in blocks of 15-17 AND elements are converted into sequential ones, which through the OR elements 18-20 are fed to 1-3 inputs of the digital information storage 36, not the fourth and fifth inputs of which are supplied with sound signal codes. When playing back / Fig. 2/, the 54 MHz clock signals from the outputs of the keys 42, 47, 52 go to the third and fifth control inputs of the block 36 and give the signal codes R, G, B to the inputs of the decoders 43, 48, 53, restoring the compressed code streams . Blocks 44, 49, 54 double the codes in a row, codes with a frequency of 48 MHz from these blocks go to the information inputs of drives 45, 50, 55 frame codes, which for the first frame period concentrate all frame codes in their blocks 71 _1-800 registers . The output from the last register unit ₇₁₈₀₀ outputs all the block codes in conditioners 46, 51, 56 control signals in which the codes are converted into signals energize LEDs LED screen. The video playback mode on the LED screen is 1200 × 800 × 50 Hz. Line and frame scans are absent as unnecessary. When playing the right and left frames on the screen, the glasses of the ZD glasses alternately lose transparency, and the viewer perceives the image in bulk. Pulses of 1.53 MHz from the keys 57, 62 are received at the sixth and seventh inputs of block 36, give out sound codes, decoders 58, 63 restore the code flows, blocks 59, 64 convert the codes into analog audio signals reproduced by the speakers. The technical characteristics of the camcorder are given in table 2.

table 2 Specifications Values Formation of two images two FDI arrays Stereo / Frame Rate 25 Hz / 50 Hz Shooting video mode 800 pages × 600 _count × 50 Hz Number of lines / number of samples 800/600 Code Sample Rate 24 MHz Video coding 8 digits Play Video playback 800 _pp × 1200 _count × 50 Hz Frame resolution 960,000 pixels 1,200 × 800 3D image perception through ZD glasses with IR receiver Image playback flat panel led screen

Used sources

1. Patent No. 2304361 Cl, cl. H04N 13/00, bull. 22, from 08/10/07, prototype.

2. V.I. Murakhovsky. Computer device. M., 2003, p. 522.

3. Kolesnichenko O. In, Shishigin I.V. PC hardware. 5th ed., St. Petersburg, 2004, p. 832, 833, 835, 558.

4. "Radio" No. 9, 2004, p. 47.

5. "Home computer" No. 12, 2006, p. 43.

Claims (1)

A video camera containing the first and second lenses, a photoelectric converter / photoelectric converter /, including first to third preamplifiers, the outputs of which are the first and third outputs of the photoelectric converter, containing the first and third ADCs of the video signal, the information inputs of which are connected to the first and third outputs of the photoelectric converter, The control inputs of the three ADCs of the video signal are combined, from the first to the third encoders, the information from the first to eighth inputs of which are connected to the first and eighth outputs, respectively, of the first and third ADCs of the video signal la, the first through third blocks of AND elements, the first - ninth inputs of which are connected to the first - ninth outputs of the first - third encoders, the control inputs of the blocks of AND elements are combined, a frequency synthesizer, the first key and the trigger connected in series, the signal input of the first key is connected to the second output of the frequency synthesizer, the second and third keys, the signal inputs of which are combined and connected to the first output of the frequency synthesizer, the first control input of the second key and the second control input of the third key connected and connected to the first output of the trigger, the second control input of the second key and the first control input of the third key, combined and connected to the second output of the trigger, the viewfinder, the information inputs of which are connected to the first - eighth outputs of the first - third ADCs of the video signal, and the first and second control its inputs are connected to the eighth and seventh outputs of the frequency synthesizer, containing in series the first ADC of the sound signal, the first encoder of the sound signal and the first block of AND signal elements, the last soundly connected to the second ADC of the sound signal, the second encoder of the sound signal and the second block of elements AND sound signal, the sound signals are applied to the inputs of the first and second ADCs of the sound signal, their control inputs are combined and connected to the third output of the frequency synthesizer, to the fourth output of which control inputs are connected the first and second blocks of elements And the sound signal, and containing a series-connected drive of digital information and a playback device, the fourth and fifth information inputs of the drive digitally information are connected to the outputs of the first and second elements AND an audio signal, its first and second control inputs are connected to the fourth and fifth outputs of the frequency synthesizer, the first and fifth outputs of the digital information storage device are connected respectively to the first and fifth inputs of the playback device, the first and fifth outputs of which are connected respectively, to the third and seventh control inputs of the digital information storage device, the playback device contains a frequency synthesizer, a sixth key, the signal input of which connected to the third output of the frequency synthesizer, contains a signal channel R including a first key, and a first decoder and a first code processing unit connected in series, a signal channel G including a second key and a second decoder and a second code processing unit connected in series, a signal channel B including the third key and the third decoder and the third code processing unit connected in series, the information inputs of the first, second and third decoders are connected respectively to the first and third outputs of the digital information storage device formations, the first control inputs of the first to third decoders are combined and connected to the third output of the frequency synthesizer, the second control inputs of the first to third decoders and the first control inputs of the first to third blocks of code processing are combined and connected to the fourth output of the frequency synthesizer, signal inputs of the first to third keys combined and connected to the output of the sixth key, the first and second control inputs of the first - third keys are connected respectively to the second and first control outputs in the first - tr By means of a network of decoders, the output of the first to third keys are connected respectively to the third, fourth and fifth control inputs of a digital information storage device, it contains a first sound channel including a fourth key and serially connected first sound code decoder, a sound signal register, an analog sound signal generating unit and a loudspeaker, the second sound channel, including the fifth key and connected in series to the second sound code decoder, the sound signal register, the unit for generating the analog sound signal and loud the evaporator, the information inputs of the first and second sound code decoders are connected to the fourth and fifth outputs of the digital information storage device, the signal inputs of the fourth and fifth keys and the first control inputs of the first and second sound code decoders are combined and connected to the fifth output of the frequency synthesizer, the second control inputs of the first and the second sound code decoders and the first control inputs of the sound signal registers are combined and connected to the sixth output of the frequency synthesizer, the first and second control inputs of the fourth and the fifth key are connected to the second and first outputs of the first and second sound code decoders, the outputs of the fourth and fifth keys are connected to the sixth and seventh control inputs of the digital information storage device, the playback device contains an IR transmitter located on the body of the video information display device, and ZD glasses with an IR receiver on their frame, the input window of which when playing the image is located against the output window of the IR transmitter, characterized in that the fourth and fifth keys, a signal the input inputs of which are combined and connected to the seventh output of the frequency synthesizer, from the first to third elements OR, the first inputs of which are connected to the outputs of the first to third blocks of AND elements, the combined control inputs of which are connected to the sixth output of the frequency synthesizer, a self-propelled pulse / SRI is introduced /, the input of which and the control input of the first key are combined and connected to the eighth output of the frequency synthesizer, the outputs of the first and ninth bits of the SRI are combined and connected in parallel to the second the first and third elements of the FDI are introduced into the photomultiplier inputs of the first or third elements OR, the photosensitive side of the first FDI matrix is located in the focal plane of the first lens, the first and third outputs are connected to the first inputs of the first and third pre-amplifiers, respectively, and its control inputs are connected: the first to the output of the fourth key, the second to the output of the second key, the photosensitive side of the second FDI matrix is located in the (focal plane of the second lens, the first and third outputs are connected to the second m inputs of the first and third pre-amplifiers, the first and second control inputs are connected respectively to the output of the fifth key and to the output of the third key, the first control input of the fourth key and the second control input of the fifth key are combined and connected to the first output of the trigger, the second control input of the fourth key and the first control input of the fifth key are combined and connected to the second trigger output, the outputs of the second and third keys through diodes are combined and connected to the combined control inputs of the first - the third ADC of the video signal, the seventh key is inserted into the playback device, the signal input of which is connected to the signal input of the sixth key, the output of which and the output of the seventh key are combined, the stereo pair / SIS / clock allocation unit, the first and third inputs of which are connected to the first and third outputs of the drive digital information, and its output is connected in parallel to the input of the IR transmitter, to the second control input of the sixth key and to the first control input of the seventh key, and a flat-panel LED screen / SD-ek wound /, a frame code storage device and a control signal generator are introduced into each channel of the R, G, B signal, the information inputs of the frame code storage drive are connected to the outputs of the channel code processing unit, and the outputs are connected to the information inputs of the control signal generator of its channel, the control inputs of which combined with the first control inputs of the drive codes of the frame of the three channels and connected to the seventh output of the frequency synthesizer, the first output of which is connected in parallel to the second control inputs of the three channels frame code amplifiers, the third control inputs of which are combined and connected to the second output of the frequency synthesizer, the flat-panel LED screen contains a glass screen and a matrix of emitting elements made in it according to the frame resolution number / 1200 × 800 /, each emitting element includes three LED cells / LED -cells /, each of which emits one of the primary colors, the LED cell includes a white LED and the corresponding color filter on the radiating side, the control input of each LED is connected to corresponding to the output of the corresponding driver of control signals, the drive codes of the frame are identical, each includes sequentially connected blocks of registers, which by the number of lines in the frame, the information inputs are the first and eighth inputs of all register blocks bit-wise, the control inputs are: the first is the first control input of the first block registers, the second - the combined second control inputs of the register blocks, the third - the combined third control inputs of the register blocks, each control The output output of the previous block of registers is the first control input of each subsequent block of registers, the control output of the last block of registers is connected in parallel to the fourth control inputs of all register blocks, the outputs of the frame code storage are the parallel outputs of all register blocks / 1200 × 800 /, the register blocks are identical, each includes the first and second keys, a pulse distributor and eight registers, the information input is the bitwise integrated third inputs of the bits of eight registers, the output The odes are the parallel outputs of all bits of eight registers, the control inputs are: the first is the first control input of the first key, the second is the signal input of the second key, the third is the signal input of the first key, the fourth is the first control input of the second key, the output of the first key is connected to the input of the distributor pulses, the outputs of which are connected in series to the first / clock / bit inputs in parallel with eight registers, the last output of the pulse distributor is connected to the second control input of the first yucha is the control output connected to the first control input of the next block of registers, the output of the second key is connected to the second inputs of the bits in parallel to eight registers and to the second control input of the second key, the control signal shapers are identical, each includes a pulse shaper block, the input of which is a control input shaper control signals, and converters "code - the number of pulses of radiation" by the number of frame resolutions / 1200 × 800 /, each of which includes sequentially with single decoder, the first and eighth inputs of which are the information inputs of the code-to-number of radiation pulses converter, a key block of 255 keys and an output key, a self-propelled pulse distributor / SRI / of 255 digits, the outputs of which are connected to the signal inputs of the corresponding keys in the key block and a power source, the corresponding outputs of the decoder are connected to the control inputs / U _OT / of the corresponding keys in the key block, the key outputs of which are combined and the combined output is connected to the control input / U _OT / output key, the signal input of which is connected to the output of the power source, the output of the output key is the output of the converter, the pulse generating unit contains pulse generating circuits according to the number of code-to-number radiation pulses converters, the output of each pulse generating circuit is connected to the SRI input of its converter , the information inputs of the driver of the control signals are the inputs of the decoders of all converters, the outputs are the outputs of the output keys of all converters "code - h radiation pulse layer ", the SIS extraction unit includes the first - third pulse counters, the counting inputs of which are 1-3 inputs of the block, the first and second elements AND, the first - third elements NOT and a diode, the outputs of the first and second pulse counters are connected to the inputs of the first element And, whose output and the output of the third pulse counter are connected to the inputs of the second AND element, the output of which is the output of the SIS extraction unit, the inputs of 1-3 elements are NOT connected to the counting inputs of the first and third pulse counters, respectively, and the outputs lementov HE and an output of second AND gate via a diode coupled and connected in parallel to the control inputs of the first - third pulse counters.

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