RU2359425C1 - Video camera - Google Patents

Abstract

FIELD: physics, video engineering.

SUBSTANCE: invention is related to household digital video equipment and may be used for recording and reproduction of video information. Result is achieved by the fact that PZI matrix is introduced in PET, three coders are introduced in video chamber, decoder and generator of control signals are introduced in every channel of reproduction device, and device of video information display is represented by flat panel light diode screen.

EFFECT: simplification of design of photoelectric transducer /PET/, increased duration of continuous use of video chamber and increased resolution of frame achieved by PZI matrix introduction in PET made by HZ, by compression of video information codes flow and application of flat panel light diode screen.

14 dwg, 2 tbl

Description

The invention relates to household digital video equipment, can be used to record and play video information. An analogue is a "Digital video camera" [1], which contains a lens, a photoelectric converter / photoelectric converter /, three ADCs of a video signal, a frequency generator and synthesizer, four blocks of AND elements, a digital information storage device, a video detector and a playback device that includes three channels for processing R codes, G, B, radiation modulation unit, horizontal and vertical scanning units, projection lens and matte screen. Frame construction is carried out by electron-optical scanning of two rays modulated by brightness with projection by their lens on a matte screen that does not have the afterglow property. Disadvantages of the analogue: low brightness of the image on the screen and insufficient resolution of the frame / 800 _pages × 1000 _counts /.

The prototype adopted "Digital Video Camera" [2], containing a lens, photomultiplier, including two amplifiers, two piezo-deflectors, voltage sources, two dichroic mirrors, three micro-lenses, three photodetectors, three pre-amplifiers and horizontal and vertical scanning units containing three ADCs of a video signal , ADC of a sound signal, four blocks of AND elements, a master oscillator and a frequency synthesizer, a digital information storage device, a video detector and a playback device including a master generator and a frequency synthesizer, a key, three channels processing of signal codes R, G, B, each of which contains a register, a code processing unit, a first delay unit, an adder and a first frame code store, a second delay unit and a second frame code store, including the first to sixth pulse amplifier units, a modulation unit radiation, horizontal scanning unit, projection lens and matte screen, the playback device contains a sound signal register, an analog signal generating unit / from a DAC, a low-pass filter and a power amplifier / and a loudspeaker. Video mode when recording video information 400 _lines × 500 _counts × 25 Hz, video mode when playing 800 _lines × 1000 _counts × 25 Hz, frame resolution 1000 × 800 = 800000 pixels.

The disadvantages of the prototype: the complexity of the design of the photoelectric converter, requiring the preservation of precise alignment during operation, the complexity of the modulation unit of radiation and electron-optical scanning, insufficient resolution of the frame / 1000 × 800 /, recording video without compression limits the working time of using the video camera. The purpose of the invention is to simplify the photomultiplier, compress the stream of the resulting video information and increase the resolution of the frame. The technical results are the simplification of the photomultiplier with the exception of piezoelectric deflectors, amplifiers, reference voltage sources, horizontal and vertical scanning units, and the introduction of a PZI matrix / device with charge injection according to the HZ technology [3 p.552] /, video compression with a coefficient of at least 4 for each frame, the introduction of three encoders to the digital information storage device and three decoders in the playback device, increasing the resolution of the frame by half 1.6 × 10 ⁶ against the prototype. Video mode when receiving video information 1000 × 800 × 25 Hz, where: 1000 is the number of encoded lines of the frame, 800 is the number of encoded samples in the line, 25 Hz is the frame rate. Sampling frequency for analog-to-digital conversion: f _ADC = 1000 × 25 Hz × 800 = 20 MHz. Frequency lad 25 kHz / 25 Hz × 1000 /. The smallest compression ratio of the stream of frame codes is accepted 4. The sampling rate of the codes after data compression is 5 MHz / 20 MHz: 4 /. Clock frequency when following codes in sequential form:

- число отсчетов в отроке сжатого потока кодов,Where:

- the number of samples in the segment of the compressed stream of codes,

9 _times - the number of bits in the code at the output of the encoder. The period following the codes with the ADC is 50 ns. The video mode during playback is 1600 × 1000 × 25 Hz, where: 1600 is the number of samples in a line after doubling, 1000 is the number of lines in a frame, 25 Hz is the frame rate. The resolution of the frame when playing 1600 × 1000, 1.6 × 10 ⁶ pixels.

The essence of the invention is that in a video camera containing a lens, a photoelectric converter comprising three preamplifiers containing three ADCs of a video signal, an ADC of a sound signal, four blocks of I elements, a digital information storage device and a playback device including three channels for processing R, G codes, In, the FDI matrix is introduced into the photoelectric converter, three encoders, a key, and in each channel of the playback device, a decoder and driver of control signals, and a video information display device pre it is delivered by the flat-panel LED screen / SD screen /. The structural diagram of the video camera in Fig. 1, the playback device in Fig. 2, the encoder in Fig. 3, the operation diagrams of the encoder in Fig. 4, the block of elements And in Fig. 5, the decoder in Fig. 6, the code processing unit in Fig. 7 , frame code accumulator in Fig. 8, register block in Figs. 9, 10, control signal generator in Fig. 11, CD cell in Fig. 12, radiating element in Fig. 13, arrangement of radiating elements in the LED screen in Fig. .fourteen. The video camera includes / Fig. 1 / lens 1, a photoelectric converter / photomultiplier / 2, which is a sensor of three primary colors R, G, B, including a PZI 3 matrix / device with charge injection /, made using Foreon X3 technology from a three-layer CMOS sensor [ 3, p.552, 4, p.832-835] about the optical resolution of 800 × 1000, which provides 24-bit color depth [4, p.835], the photosensitive side of the PZI 3 metric is located in the focal plane of lens 1, from the first to the third outputs of the matrix FDI 3 are connected respectively to the inputs of the preliminary amplifiers of the solar cells 4 / R /, 5 / G /, 6 / V /. The video camera includes the first 7, second 8, third 9 ADCs of the video signal R, G, B, which are identical to the ADC in the analogue [1, p. 4 of FIG. 5], the first 10, second 11, third 12 encoders, first 13, second 14 , the third 15 blocks of elements And, the master oscillator 16 and the synthesizer 17 frequencies, the first 18 and second 19 keys, the video detector 20 with an LCD display, the ADC 21 of the sound signal, which is identical to the ADC of the sound signal in the analogue [1, p. 4 Fig. 6], an element block 22 AND / fourth /, a digital information storage device 23 and a reproducing device 24 comprising / a figure 2/ a master oscillator 25 and a synthesizer 26 from, key 27, and three channels for processing the codes R, G, B, the channel for processing R codes includes a series-connected decoder 28, a code processing / doubling unit 29, a frame code storage 30 and a control signal generator 31, the G code processing channel includes connected decoder 32, code processing unit 33, frame code storage 34 and control signal generator 35, code processing channel B includes serially connected decoder 36, code processing unit 37, frame code storage 38 and control signal generator 39. The playback device includes a flat-panel LED screen 40 / LED screen / and a series-connected register 41 of the sound signal, the unit 42 for generating an analog audio signal from the DAC, a low-pass filter and a power amplifier and a speaker 43. The encoders 10, 11, 12 are identical, each includes / figure 3 / connected in series register 44, the comparison circuit 45 / comparator /, pulse counter 46 and decoder 47, connected in series block 48 elements of delays, block 49 keys and buffer storage 50 frame codes. Information inputs are bitwise integrated first-eighth inputs of the register 44, the first inputs of the comparison circuit 45 and the inputs of the block 48 delay elements. The outputs are the first to ninth outputs of the buffer storage 50 frame codes, the volume of which is 200 × 10 ³ nine-digit frame codes. The control input is the control input of block 50. Blocks 13, 14, 15 of AND elements (Fig. 5/) are made respectively of blocks of And elements in the analogue [1, p.5 of Fig. 12], they convert parallel codes into serial ones before they enter the drive 23 digital information. Each of the blocks 10, 11, 12 includes nine elements AND _I ... AND ₉ , a self-propelled pulse distributor / SRI / and an OR element. The start pulse U _p 5 MHz comes from the fourth output of block 17. Block 22 of AND elements contains 16 AND elements / by the number of bits in the code /, SRI and OR element. The start pulse U _p are pulses of 80 kHz from the second output of block 17. The decoders 28, 32, 36 are identical, each includes / Fig. 6/ connected in series the first / nine-bit / register 51, the drive 52 of the frame codes with a capacity of 200 × 10 ³ nine-digit codes, second / nine-digit / register 53, the first block of keys 54 of eight keys and the third / eight-bit / register 55, sequentially connected the second block 56 of the keys of eight keys, eight-bit subtracting counter 57 pulses and decoder 58, the first 59, second 60, third 61 and fourth 62 keys. The information input is the information input of the first register 51, the outputs are the first to eighth outputs of the third register 55. The control inputs are: the first is the first control input / Ut 45 MHz / of the first register 51, the second is the combined second control input / 5 MHz / register 51 and the signal input of the third key 61, the third - the combined signal inputs / 20 MHz / keys of the first 59, second 60, fourth 62. Blocks 29, 33, 37 processing / doubling / codes are identical, each includes /Fig. 7/ [1 p.5 9 of FIG. 10] trigger 63, first 64, second 65 key blocks / B keys in each /, first 66, second 67, third 68, fourth 69 registers, adder 70, fifth 71 and sixth 72 registers that store codes for 50 ns, and 16 diodes. The information input is the bitwise combined from 1 to 8 inputs of blocks 64, 65 of the keys, to which color signal codes with a frequency of 20 MHz are received in parallel. The control input is the combined input of the trigger 63 and the control input of the adder 70. The outputs are the bitwise combined outputs 0-7 of the adder 70, the outputs 1-8 of the fifth 71 and sixth 72 registers. From the outputs of blocks 29, 33, 37, codes in parallel form follow with a frequency of 40 MHz to the frame code stores 30, 34, 38, respectively. The frame code stores are identical / Fig. 8/, each includes series-connected blocks of 73 registers, of which the number of lines in the frame, i.e. 73 _1-1000. The information input of the frame code storage device is the bitwise integrated / 1-8 / inputs of all blocks of 73 _1-1000 registers. The outputs are the outputs of all the blocks of registers 73, only outputs 12.8 × 10 ^6/1600 × 8 × 1000 /. The control inputs are: the first is the first control input / 25 Hz / of the first block of 73 registers, the second is the combined second control inputs / U _output 25 kHz / blocks 73, the third is the third control inputs / U _d 40 MHz / blocks 73 registers. The control output of each previous block 73 registers is the first control input for each subsequent block 73. The control output of the last / 1000th / block 73 registers is connected in parallel to the fourth control inputs of all blocks 73 registers. Blocks 73 registers are identical, each includes /Fig.9, 10 / first 74 and second 75 keys, a pulse distributor 76 and eight registers 77 _1-8 , each of which contains 1600 bits, according to the number of samples in a row. The information inputs of the register block are bitwise combined from the first to the eighth third inputs of the bits of the eight registers 77. The outputs are the parallel outputs of all the bits of the eight registers 77, the total outputs from the block 73 12800/1600 × 8 /. The outputs of 1000 are the outputs of blocks 73 of each drive 30, 34, frame code 38 12.8 × I0 ^6/12800 × 1000 /. The control inputs are: the first is the first control input / 25 Hz / first key 74, the second is the signal input / U _output 25 kHz / second key 75, the third is the signal input / U _d 40 MHz / first key 74, the fourth is the first control input the second key 75. The output of the key 74 is connected to the input of the pulse distributor 76, the outputs of which are connected in series from the first to the 1600th to the first / clock / bit inputs in parallel of eight registers 77. The last output of the block 76 is connected to the second control input of the first key 74 and is control output bl Single 73 and connected to the first control input of the first switch 74 in the next block register 73 _2. Yield of the second switch 75 is connected in parallel to the second inputs of the eight bits of the register 77 and to its second control input key 75, the last one pulse U _vyd closes switch 75. The outputs of accumulators 30, 34, 38 are connected /fig.2/ frame codes to their data inputs shapers 31, 35, 39 control signals, the purpose of which is to perform the conversion "code - the number of pulses of radiation" to obtain the duty cycle of the radiation of the LEDs in the frame period, respectively, the value of the color signal code. Each of the blocks 31, 35, 39 includes (Fig. 11/) a pulse former block 78, containing identical pulse generation circuits by the number of converters 1.6 × 10 ⁶ and whose input is a control input / U _to 25 Hz / of the driver of control signals, and contains converters "code - the number of pulses of radiation" by the number of samples in line 1600 and the number of lines in frame 1000, i.e. 1.6 × 10 ⁶ . The converters are identical, each of them includes (Fig. 11/) a decryptor 79 connected in series, the information inputs 1-8 of which are the information inputs of the control signal generator 31, the key block 80 of 255 keys and the output key B1, also includes a self-propelled pulse distributor 82 / SRI / and a power source 83 for its LED in the LED screen. The outputs of the decoder 79 are connected to the first control inputs U _{FROM the} corresponding keys in the key block 80, the key outputs of which are combined and the combined output is connected to the control input U _{from the} output key 8I, the signal input of which is connected to the output of the power source 83. The input of the SRI 82 is connected to its output in the block 78 of the pulse shapers, the SRI 82 has 255 bits, the outputs of which are connected to the signal inputs of the corresponding 255 keys in the block 80 / input 2 /. The information inputs of block 31/35, 39 / are the information inputs of all decoders 79, the outputs of all output keys 81 are the outputs of block 31, which are connected to the corresponding inputs of the LED screen 40. The initial state of the output keys 81 and the keys in blocks 80 is closed. The control input of block 31/35, 39 / receives a signal U _K 25 Hz, which is supplied in parallel to the inputs of all pulse shaper circuits that generate pulses of the corresponding amplitude and duration, which are the triggering U _p for SRI 82. Each pulse from block 80 of the keys opens an output key 81 for a time of 156 μs t _from = 40 ms: 255 = 156 μs, 40 ms - frame duration, 255 - resolution of the 8-bit code, the number of outputs from the block 82. With the arrival of the code in the decoder 79, the signals from its outputs open the corresponding keys in block 80, which are sequentially passed to the output Lok 80 with respective bits of MIS signals U 82 _from the output switch 81 and the LED 40 for a screen frame period, outputs the corresponding number of pulses of radiation at regular intervals over the frame period. The larger the code, the more pulses of radiation the LED emits during the frame period. An example of the distribution of radiation pulses according to the code values in table 1.

Table 1 Block Input Code 79 The distribution of radiation pulses in the frame period The number of emissions per frame period 00000000 00 ... 00 0 00000001 00 ... 128 00 one 00000010 00 88 176 00 2 00000011 00 64 124 192 00 3 00000100 00 62 124 186 248 00 four . . . . . . . . . 11111110 one, 2 3 four ... 254 00 254 11111111 one, 2 3 four ... 254, 255 255 0 - means the absence of a radiation pulse. 1, 2, 3 ... 255 - numbers of radiation studies in the frame period.

Following radiation in the frame period at equal time intervals creates the best conditions for human vision to perceive the brightness of the image and the reliability of color reproduction. The inertia of the operation of the LEDs should be up to 1 μs. Upon completion of the accumulation of frame codes by blocks 30, 34, 38, all signal codes R, G, B are synchronously issued to control signal generators 31, 35, 39, where the codes are converted to the number of supply voltage to the LEDs of the LED screen. Modern technologies allow each of the blocks 30, 31, 34, 35, 38, 39 to be executed in one chip. The flat-panel LED screen 40 represents a set of radiating elements in the matrix according to the number of frame resolutions 1.6 × 10 ⁶ , which are performed in the glass. The LED screen includes a screen glass and a matrix of radiating elements according to the number of frame resolutions. Each emitting element includes three LED cells / LED cells /, each of which emits one of the primary colors R, G, B. The LED cell contains / Fig. 12 / white light-emitting diode 84 and the corresponding color filter 85. Three LED cells make up the emitting matrix element / Fig. 13/, the arrangement of the matrix elements and LED cells in the LED screen 40 in Fig. 14. The radiation brightness level of the LED cell is proportional to the number of LED pulses per frame period, the pulses can be from 1 to 255, i.e. from 156 μs to 40,000 μs. The total emission of the three primary colors by three LED cells forms the brightness and color tone of one pixel of the screen. As LEDs, superbright LEDs of the type manufactured by Nichia, Ledtronies, Kingbright [5, p. 47], but with a diameter of 0.5 mm / can be used. 12 / or LEDs developed by PLED technology using LEDs with polymer organic molecules [6, p. 43]. LEDs are made in glass using the microelectronic technology. The size of one radiating element 1 × 1 mm / Fig.13/. The size of the LED screen is: horizontal 1600 × 1 mm = 1600mm,

vertical 1000 × 1 mm = 1000,

diagonally 188 cm, or 74 inches.

Photoelectric converter 2 with a matrix of PZI 3 generates three analog signals of the primary colors R, G, B. Lens 1 creates an image in the focal plane in which the photosensitive side of the matrix of PZI 3 is located, its optical resolution is 800 _ot × 1000 lines. The FDI matrix is made three-layer by the HZ technology. In the period / 40 ms / frame, for each of the three layers of the FDI matrix, input 1 from key 18 receives 20 MHz pulses for reading horizontal, R, G, B pixel signals [4, p. 832], to the second input of the FDI matrix from key 19 pulses of 25 kHz line frequency are received to read the pixel signals vertically. Analog signals from 1-3 outputs of the PZI 3 matrix are respectively supplied to the inputs 4, 5, 6 of pre-amplifiers, the outputs of which are fed to the inputs 7, 8, 9 of the ADC, the outputs of which are 8-bit codes in parallel with 20 MHz sampling arrive at the inputs of their encoders 10, 11, 12. Synchronization of the start of reading from the beginning of the frame period is performed by a frame frequency pulse of 25 Hz, which simultaneously opens both keys 18, 19 for passing 20 MHz and 25 kHz into the matrix of control signals. A frequency synthesizer 17 produces: from the first output, 20 MHz sampling pulses to the control inputs of the ADC 7-9 and the key 18 signal input, from the second output - 80 kHz sampling pulses of the sound signal to the control inputs of the ADC 21 and block 22 of I elements, from the third - frequency pulses 25 Hz frames to the control inputs of the keys 18, 19 and to the second control input of the video detector 20, from the fourth - 5 MHz pulses to the control inputs of encoders 10, 11, 12, and to the control inputs of blocks 13, 14, 15 of the And elements, from the fifth - pulses of 25 kHz line frequency to the signal input of the key 19 and the third control yayuschy input viewfinder 20, the sixth - 1.28 MHz clock / 80 × 16 kHz / audio signal into a second control input 23 drive the digital information from the seventh output 45 MHz clock pulses to the first control input 23 digital information storage.

The operation of the encoder, FIG. 3.

Codes with a frequency of 20 MHz are received at 1–8 inputs of register 44, at the first inputs of the comparison circuit 45, and at the inputs of the block of 48 delay elements delaying codes for the response time of 18 ns of the comparison circuit 45, which is represented by two 530CD1 microcircuits with a response time of 18 ns [ 7, p. 279]. The code after the delay in block 48 through the public keys of block 49 is fed to the first or eighth inputs of the buffer storage 50 frame codes with a capacity of 200 × 10 nine-bit codes. Scheme 45 compares the magnitude of each previous and subsequent codes in order to identify their equality or inequality. When unequal codes are followed, they pass through block 48, the keys of block 49 and go to the first or eighth inputs of the buffer storage 50 codes, the output of which is performed by a signal

U _vyd 5 MHz output from the fourth block 17. Receipt of the codes in the block 50 when following uneven codes is 20 MHz. In the general stream of codes there are a large number of equal codes in magnitude, and the higher the sampling rate, the more equal in magnitude the codes. The encoder compresses the stream of codes with a floating coefficient from 1 to 255. The total compression ratio of the stream of codes for the period of each frame is taken at least 4, which will be fully implemented at a sampling frequency of 20 MHz. With the inequality of codes A> B, a signal appears at the output of block 2 45 / in the microcircuit, output 5 [7, p.272 Fig. 2.190], when the codes are equal, the signal from output 1 of block 45 closes the keys in block 49, and enters a counting pulse to counter 46 and both U _vyd signal to the first control input of register 44. The eight-bit counter 46 produces count of pulses from the output unit 45 until 1 codes are equal in magnitude. Counter 46 has a maximum code of 11111111/255 /, hence the maximum compression ratio of 255. Using a counter with a higher bit capacity, the compression ratio will be greater. A counter made of K531IE160 microcircuits with a response time of 8 ns [7, p. 428]. When unequal codes appear from circuit 45, a signal from output 2 or 3 / with A <B /, which are combined, follows, the signal from them is used to issue a code for the number of equal codes from counter 46, which is transmitted through diodes to the first to eighth inputs of block 50 and fills the ninth bit in block 50, from this bit the signal is used to identify the code for the number of equal codes when decoding. The same signal opens the keys in block 49 / input 1 / and resets the register 44 / input 2 /. The code issued before this from block 50 is the first sequence code; in diagram I of FIG. 4 they are marked with crosses. Codes of equal magnitude and counted by counter 46 are excluded from the code stream / diagram III /. The capacity of the buffer storage 50 frame codes is 200 × I0 ³ nine-bit codes to provide a compression ratio of 4 for the frame period. When successively following codes of equal magnitude more than 255, the decoder 47 enters the work. With the code 11111111, the decoder 47 issues a signal that simultaneously opens the keys in block 49 / input 1 /, resets the register 44 / input 2 /, and issues the code from the counter 46 / input 1 / and resets the counter / input 2 /, and the ninth digit of block 50 receives a signal to identify the code of the number of equal codes. The bandwidth of the encoder is determined by the response time of the comparison circuit 45/18 ns / and is up to 50 MB / s. From the outputs of the encoders 10, 11, 12, the codes are sent in parallel to the inputs of the blocks 13, 14, 15 of the And / 1/1 elements, in which the parallel codes are converted to serial ones before being transferred to the digital information storage device 23. The signal codes R, G, B are received at the inputs 1, 2, 3 of the digital information storage device 23, respectively. When shooting, the codes from the outputs of the ADC 7, 8, 9 also go to the information inputs of the video detector 20, for 1-3 control inputs of which pulses of 20 MHz, 25 Hz, and 25 kHz, respectively, are received. The ADC 21 of the sound signal converts the analog sound signals to 16-bit 80 kHz discretization codes [l, p. 8, FIG. 6], which are received in parallel in block 22 of the AND element, from which sound codes in sequential form are sent to 4 drive input 23 digital information frame codes. The playback device 24 is designed to view the captured material. Its frequency synthesizer 26 generates: from the first output, clock pulses U _T 45 MHz to the signal input of the key 27 and to the first control inputs of the decoders 28, 32, 36, from the second output - 1.28 MHz pulses for outputting sound signal codes from block 23 and to the first control input of block 41, from the third - pulses, sampling of 80 kHz sound signal, from the fourth - pulses of 5 MHz U _output from decoders 28, 32, 36 / input 2 /, fifth - pulses of 25 Hz to the control input of key 27, to the first the control inputs of the drives 30, 34, 38 and the control inputs of the drivers 31, 35, 39 of the control signals from the pole th output - pulses double sampling of 40 MHz on the third control inputs of the drives 30, 34, 38 of the frame codes, the seventh - impulses of 25 kHz to the second control inputs of the drive frame codes 30, 34, 38 / U _spd / eighth - pulses 20 MHz to the third control inputs of decoders 28, 32, 36 and to the control inputs of blocks 29, 33, 37. Pulses of 25 Hz open the key 27 for the duration of the frame, during which the key skips passes U _T 45 MHz to 1, 2, 3 drive inputs 23 digital information, which are signals U _vyd serial codes of signals R, G, B, k which go to the information inputs of the decoders 28, 32, 36, respectively

The work of decoders, Fig.6.

The codes in serial form received c 5 MHz to an information input 1 of the first register 51 to the first / timing / control input of which receives the clock pulses of 45 MHz, the second control input receives the signal (U _vyd 5 MHz, the third control input of the pulses 20 received MHz from the output 8 of block 26. Filling the nine bits of register 51, the code takes on a parallel form, in which it is then used. From register 51, the codes are transmitted with a frequency of 5 MHz to the drive 52 frame codes, its capacity is 200 × 10 nine-bit codes. 52 codes you are given by 5 MHz signals from key 61. When the key 61 is closed, the codes are accumulated by the drive 52. The initial state of the keys in the decoder: in block 54, open, 56 closed, keys 59, 61, 62 open and key 60 closed. second register 53 receives the first to eighth code data signals, and the presence in the ninth digit identification number equals the code signal, it enters the ninth digit register 53. since the register code is set 53 U _vyd signal from the key 62 has a frequency of 20 MHz. While codes 53 are received in register 53 without a signal in the ninth category, they then go through the public keys of block 54 to the third register 55, and from it they are issued by the signal U _exp1 from key 59 to the output of the decoder. The signal U _vyd1 when issuing a code and zeroes the bits of register 55. When a code is entered in register 53 with a signal in the ninth category, the signal from the ninth category closes the keys in block 54 and opens the keys in block 56, closes the keys 59, 61, 62 and opens the key 60 . The issuance of codes from the register 53 is interrupted, and the drive 52 codes accumulates the codes of the frame, as it continues to receive codes. The code of the number of equal codes through the public keys of block 56 enters the subtracting counter 57 pulses, the counting input of which from the key 60 receives pulses of 20 MHz. Impulse from key 60 comes in as a signal

U _input2 to the second control input of the register 55 and outputs the code contained in it, but does not reset it. Therefore, while the counter 57 is subtracting, the same code is issued from register 55. These codes are codes seized during compression of the stream of codes in the encoder. From the output of register 55 there is a 100% restored stream of codes. From register 55, only eight-bit codes with a sampling rate of 20 MHz go to block 29 of the code processing. At the end of the subtraction in counter 97, a code of zeros enters decoder 58. From the output of the decoder 58, the signal is simultaneously: closes the keys in block 56, opens the keys in block 54 / input 1 /, closes the key 60 and opens the keys 59, 61, 62. Codes 52 are again sent to the register 53 from the drive through the keys at block 54 to register 55, and the processes are repeated. The decoder throughput is determined by the response time / 10.5 ns / counter 57, which is from 100IE137 microcircuits [7, p. 428], plus the response time of 6 ns of the decoder 58 from the 100ID161 microcircuit [7, p. 433). Code stream recovery rate up to 50 MB / s. The reconstructed stream of codes with a frequency of 20 MHz / with the number of 800 samples in the line / is fed to the input of the code processing unit 29/33, 37 /, which doubles the number of samples in the line / 800 × 2 /. Doubling is performed by obtaining intermediate / middle / codes between each passing and the following codes. Blocks 29, 33, 37 perform the addition of the previous and subsequent codes and the division of the sum code into two. Moreover, the division is performed without time-consuming: by discarding the least significant digit in the sum code / as is done when dividing the decimal number by ten / by appropriately connecting the outputs 0-7 of the adder / Fig. 7/70 and the outputs 1-8 of registers 71, 72:

Bit 0 means transfer to the high bit when the sum of codes.

Doubling samples in a row shortens the period of codes in

, т.е. 40 МГц. Процесс сложения двух 8-разрядных кодов должен занимать 25 нс. В качестве сумматора применяется микросхема К555ИМ6 [7, с.258] с временем сложения 25 нс. После включения питания в регистрах 66-69 нули. С приходом первого импульса 20 МГц на вход триггера 63 /фиг.7/ с его первого выхода сигнал U_выд1 одновременно: выдает "код 0" с регистра 67 на первые входы сумматора 70, из регистра 68 "код 0" в регистр 72 для хранения на 50 нс и через диоды на вторые входы сумматора 70, сигналы выдачи и обнуляют регистры, открывает U_от ключи в блоке 64 на время прохода следующего кода через ключи, и регистры 66, 67 заполняются кодом "код 1". В сумматоре 70 за 25 нс идет сложение "код 0+код 0", и код суммы идет на выход при этом он делится на два:two times that becomes 25 ns

, i.e. 40 MHz. The process of adding two 8-bit codes should take 25 ns. As an adder, the K555IM6 microcircuit is used [7, p. 258] with an addition time of 25 ns. After turning on the power in the registers 66-69 zeros. With the arrival of the first 20 MHz pulse to the input of trigger 63 (Fig. 7/) from its first output, the signal U _vyd1 simultaneously: gives a "code 0" from register 67 to the first inputs of the adder 70, from register 68 "code 0" to register 72 for storage for 50 ns and through diodes to the second inputs of the adder 70, the output signals and reset the registers, opens the U _{from the} keys in block 64 for the time the next code passes through the keys, and the registers 66, 67 are filled with the code "code 1". In the adder 70 for 25 ns, the addition is "code 0 + code 0", and the sum code goes to the output while it is divided into two:

Регистры 71 и 72 хранят код /задерживают/ 50 нс, причем первая половина задержки приходится на процесс выполнения сложения в сумматоре /0-25 нс/. С приходом второго импульса 20 МГц в триггер 63 он обнуляет сумматор 70, а сигнал со второго выхода триггера U_выд2 одновременно: выдает с регистра 72 код №2 "код 0", с регистра 66 "код 1" в регистр 71 и через диоды в сумматор, с регистра 69 "код 0" в сумматор, открывает ключи в блоке 65, и регистры 68, 69 заполняются кодом "код 2". В сумматоре идет сложение "код 0+код 1", по окончании которого /через 25 нс/ код суммы идет на выход сумматора с делением на два:

С приходом третьего импульса 20 МГц в триггер 63 он обнуляет сумматор 70, а сигнал с его первого выхода U_выд3 одновременно: выдает с регистра 71 код №4 "код 1" на выход блока, из регистра 67 выдает "код 1" в сумматор, из регистра 67 "код 2" в регистр 72 и через диоды в сумматор, открывает ключи в блоке 64, и регистры 66, 67 заполняются кодом "код 3". В сумматоре идет сложение "код1+код 2", код суммы идет на выход и делится на два:

С приходом четвертого импульса в триггер 63 он обнуляет сумматор 70, а с сигнал U_выд одновременно: выдает код №6 "код 2" из регистра 72, с регистра 66 "код 3" в регистр 71 и через диоды в сумматор, с регистра 69 "код 2" в сумматор, открывает ключи в блоке 65, регистры 68, 69 заполняются следующим кодом «код 4». В сумматоре идет сложение "код3+код4", и код суммы идет на выход с делением его на два: код 7

С приходом пятого импульса в триггер 63 он обнуляет сумматор 70, а сигнал U_ВЫД5 с первого выхода триггера одновременно: выдает с регистра 72 код №8 "код 3", выдает с регистра 67 "код 3" в сумматор, с регистра 68 "код 4" в регистр 72 на хранение и черев диоды в сумматор, открывает ключи в блоке 64, и регистры 66, 67 заполняются кодом "код 5". Сумматор выполняет сложение "код 3+код 4", код суммы следует на выход с делением на два: код №9

С приходом шестого и следующих импульсов в триггер 63 процессы повторяются. Выходы 0-7 сумматора 70 и выходы 1-8 регистров 71, 72 поразрядно объединены и являются выводами блока 29 /33, 37/. Коды с блоков 29, 33, 37 с частотой 40 МГц в параллельном виде поступают на информационные входы накопителей соответственно 30, 34, 38 кодов кадра.

Registers 71 and 72 store the code / delay / 50 ns, and the first half of the delay falls on the addition process in the adder / 0-25 ns /. With the arrival of a second pulse of 20 MHz in trigger 63, it resets the adder 70, and the signal from the second output of trigger U _vyd2 simultaneously: it issues code No. 2 "code 0" from register 72, from code 66 "66" to register 71 and through diodes to the adder, from register 69 "code 0" to the adder, opens the keys in block 65, and the registers 68, 69 are filled with the code "code 2". In the adder is the addition of "code 0 + code 1", after which / after 25 ns / the sum code goes to the output of the adder divided by two:

With the arrival of the third 20 MHz pulse in trigger 63, it resets the adder 70, and the signal from its first output U _vyd3 simultaneously: it issues code No. 4 "code 1" from register 71 to the output of the block, from code 67 it outputs "code 1" to the adder, from register 67 "code 2" to register 72 and through diodes to the adder, opens the keys in block 64, and registers 66, 67 are filled with code "code 3". In the adder is the addition of "code1 + code 2", the sum code goes to the output and is divided into two:

It resets the adder 70, and a U signal _vyd simultaneously with arrival of the fourth pulse trigger 63 to output a code №6 "code 2" from the register 72, a register 66 "code 3" in the register 71 and through the diodes in the adder 69 to the register "code 2" in the adder, opens the keys in block 65, registers 68, 69 are filled with the following code "code 4". In the adder is the addition of "code3 + code4", and the sum code goes to the output by dividing it into two: code 7

With the arrival of the fifth pulse in the trigger 63, it resets the adder 70, and the signal U _{OUT 5} from the first output of the trigger simultaneously: gives code No. 8 "code 3" from register 72, provides 3 "from code 67 to the adder, 68" code from register 68 4 "into the register 72 for storage and through the diodes into the adder, opens the keys in block 64, and the registers 66, 67 are filled with the code" code 5 ". The adder performs the addition of "code 3 + code 4", the sum code should be output with a division into two: code No. 9

With the arrival of the sixth and subsequent pulses in the trigger 63, the processes are repeated. The outputs 0-7 of the adder 70 and the outputs 1-8 of the registers 71, 72 are bitwise integrated and are outputs of the block 29/33, 37 /. Codes from blocks 29, 33, 37 with a frequency of 40 MHz in parallel form arrive at the information inputs of drives respectively 30, 34, 38 frame codes.

The operation of the blocks 73 registers, Fig.8, 9, 10.

The signals of the codes are fed to the third inputs of the bits of eight registers 77 / 9.9. The filling of the line registers begins with the opening of the U signal _to 25 Hz of the first key in the first block 73 of ₁ registers / Fig. 8/. Key 74 / Fig. 9/ transmits 40 MHz pulses to the input of the pulse distributor 76, the clock pulses from which are sequentially fed to the first inputs of the bits in parallel with eight registers 77. By filling in the registers 77 from the last output / 1600th / block 76, the signal U _s closes the key 74 and as a control output signal opens the key 74 in the next block 73 of ₂ registers, the registers of which are filled with codes of the second line. For a frame period of 40 ms, the registers 77 of all blocks 73 of _1-1000 registers are sequentially filled with codes. From block 73 of ₁₀₀₀ registers, the output signal is sent in parallel to the fourth control inputs of all blocks of 73 registers / Fig. 8/ and opens in them the second keys 75, which pass one signal U _output , which synchronously generates codes from all blocks 73 of _1-1000 registers frames to their shapers 31, 35, 39 control signals (Fig. 2/), Each drive 30, 34, 38 frame codes has 12.8 × 10 ⁶ outputs / 1600 × 8 × 1000 /, which are connected to the same number of inputs in each of blocks 31, 35, 39, each of which includes 1,6 × 10 ⁶ converters / 1600 × 1000 / "code - the number of pulses emissions. " The outputs from the three blocks 31, 35, 39 4.8 × 10 ^6/3 × 1.6 × 10 ⁶ / are connected to the same inputs in the LED screen 40. For reliable and long-term operation of the playback device, the best version of it will be the performance of drives frame codes and control signal generators on the back side of the SD screen in a unified and non-separable design.

The operation of the camcorder.

FEP2 generates a matrix of FDI 3 / Fig. 1/ analog color signals that are converted by the ADC 7, 8, 9 with a frequency of 20 MHz into 8-bit codes that enter the encoders 10, 11, 12, The encoders compress the stream of codes with a coefficient of 4 per frame period. Then, the parallel codes are converted by blocks 13, 14, 15 into sequential ones, which are fed to the 1, 2, 3 inputs of the digital information storage device 23, to the 4th input of which the sound signal codes are received. When playing (Fig. 2/), the 25 Hz signal opens the key 27, which transmits 45 MHz clock signals, which are output signals that issue codes R, G, B from the digital information storage device 23 to the information inputs of three decoders 28, 32, 36, which restore compressed code streams. Blocks 29, 33, 37 double the number of samples in a row, from which codes with a frequency of 40 MHz are fed to the information inputs of drives 30, 34, 38 frame codes, which for the first frame period concentrate all frame codes in blocks 73 of _1-1000 registers. The output control signal from the last block of 73 ₁₀₀₀ registers synchronously provides the new frame codes to the drivers 31, 35, 39 of the control signals, in which the codes are converted into power signals for the LEDs of the LED screen. Video mode when playing on an LED screen 40 1600 × 1000 × 25 Hz. The 1.28 MHz signals from the second output of block 26 provide sound signal codes from block 23, which enter block 41, are converted into analog signals in it, and are reproduced by loudspeaker 43. There are no horizontal and vertical scans in the playback device. The technical characteristics of the video camera in table 2. The device fulfilled the stated goals: the photoelectric converter was simplified, the time spent working with the video camera was increased 4 times, and the frame resolution was doubled.

Used sources

1. Patent No. 220529 C1, cl. H04N 5/225, bull. 5 from 02.20.06, analog.

2. Patent No. 2303334 C1, Cl. H04N 5/225, bull. 20 from 07.20.07, prototype.

3. V.I. Murakhovsky. Computer device, M., 2003, p. 522.

4. Kolesnichenko OV, Shishigin I.V. PC hardware. 5th ed., St. Petersburg, 2004, p. 832, 833, 835.

5. Radio, No. 9, 2004, p. 47.

6. "Home computer", No. 12, 2006, p. 43.

7. Digital integrated circuits. Minsk, 1991, p. 258, 279, 272, 428, 433.

table 2 Specifications Values Imaging Clock frequency 45 MHz Video mode 800 _frames × 1000 _pages × 25 Hz Frame frequency 25 Hz The number of encoded samples per line 800 The number of encoded strings 1000 Sampling signals when shooting 20 MHz Video coding 8 bits., 255 levels Audio sampling 80 kHz Sound coding 16 bits Play Clock frequency 45 MHz Video mode 1600 × 1000 × 25 Hz Frame frequency 25 Number of samples per line / number of lines 1600/1000 Video Sampling Rate 40 MHz Frame resolution 1,600,000 pixels Imaging flat panel led screen

Claims (1)

A video camera containing a lens, a photoelectric converter (PEC), a serially connected master oscillator and a frequency synthesizer, first through third analog-to-digital converters (ADCs) of a video signal, an ADC of a sound signal, to the input of which a sound signal is supplied and its control input is connected to the second output a frequency synthesizer containing the first key, from the first to fourth blocks of AND elements, a digital information storage device, a viewfinder and a playback device, the corresponding inputs of the viewfinder are connected to the output m of the first-third ADC of the video signal and the third control input is connected to the fifth output of the frequency synthesizer, the photoelectric converter contains first to third pre-amplifiers whose outputs are the first, second and third outputs of the photoelectric converter and are connected to the information inputs of the first and third ADCs of the video signal, control inputs which are combined and connected to the first output of the frequency synthesizer, the first to fourth inputs of the digital information storage device are connected to the outputs from the first to fourth blocks of AND elements, and the first and second control inputs are connected to the seventh and sixth outputs of the frequency synthesizer, the inputs of the fourth block of elements And are connected to the outputs of the ADC of the sound signal, the control input of which is connected to the control input of the fourth block of elements And, the control inputs of the first to third blocks of elements And are combined and connected to the corresponding input of the frequency synthesizer, from the first to fourth information inputs of the playback device are connected respectively to the first to fourth outputs of the digital information storage device mations, and its first and second control outputs are connected respectively to the first and second control inputs of the digital information code storage device, the playback device includes a master oscillator and a frequency synthesizer connected in series, a key whose signal input is connected to the first output of the frequency synthesizer, and its control input is connected to the fifth output of the frequency synthesizer, the key output is the first control output of the playback device, the second control output of which is the second output frequency synthesizer, contains three channels for processing codes R, G, B, each of which includes a code processing unit and a frame code storage device, and contains serially connected sound signal register, an analog sound signal generation unit and a loudspeaker, the sound signal register information input is connected to the fourth the output of the digital information storage device, the first control input is connected to the second output of the frequency synthesizer, to the third output of which is connected the second control input of the sound signal register, blocks the codes are identical, each includes a trigger, first and second blocks of keys, from the first to sixth registers, an adder and 16 diodes, the information inputs of the first and second registers are bitwise combined and connected to the outputs of the first block of keys, the information inputs of the third and fourth registers are bitwise combined and connected to the outputs of the second key block, the information input of the block is the bitwise combined inputs of the first and second key blocks, the control input is the trigger input connected to the corresponding to the output of the frequency synthesizer, the first trigger output is connected to the control inputs of the second, third, fifth registers and the first key block, the second trigger output is connected to the control inputs of the first, fourth, sixth registers and the second key block, the first adder inputs are connected to the outputs of the second register and through diodes to the outputs of the first register, the second inputs of the adder are connected to the outputs of the fourth register and through diodes to the outputs of the third register, the control input of the adder is connected to the trigger input, the inputs of the fifth the histories are connected to the outputs of the first register, the inputs of the sixth register are connected to the outputs of the third register, the outputs of the fifth, sixth registers and the outputs of the adder are bitwise combined and are outputs of the code processing unit, characterized in that a PZI matrix is introduced into the photoelectric converter, the photosensitive side of which is located in the focal the plane of the lens, and its first, second, third outputs are connected to the inputs of the first, second and third pre-amplifiers, respectively, the first th, second and third encoders and a second key, the signal input of which is connected to the fifth output of the frequency synthesizer, the third output of which is connected to the combined control inputs of the first and second keys and to the second control input of the viewfinder, the first control input of which and the signal input of the first key are connected to the first output of the frequency synthesizer, the informational first to eighth inputs of the first to third encoders are connected to the first to eighth outputs of the first to third ADCs of the video signal, the combined control inputs of the first to third its blocks of elements AND are connected to the fourth output of the frequency synthesizer, the output of the first key is connected to the first input of the FDI matrix, the second input of which is connected to the output of the second key, a flat-panel LED screen (SD screen) is inserted into the playback device, and in each of the code processing channels R, G, A decoder is introduced, the outputs of which are connected to the information inputs of the channel code processing unit, the outputs of which are connected to the information inputs of the frame code storage device, and a control signal generator is introduced, the information inputs of which are connected to the outputs of the drive code codes of the channel frame, the control input of the key is connected to the fifth output of the frequency synthesizer, to which the combined first control inputs of the drive codes of the frame codes of three channels and the combined control inputs of the drivers of the control signals of three channels are connected, the first, second and third outputs digital information storage devices are connected to the information inputs of the first, second and third decoders of three channels, respectively, the first, second and third the control inputs of the decoders are combined and connected respectively to the first, eighth and fourth outputs of the frequency synthesizer, the combined control inputs of the three code processing units are connected to the eighth output of the frequency synthesizer, the second and third control inputs of the frame code drives of the same name are combined and connected respectively to the seventh and sixth outputs of the synthesizer frequencies, the corresponding information inputs of the LED screen are connected to the corresponding outputs of the shapers of the control signals, the encoders are identical, each includes a register connected in series, a comparison circuit (comparator), a pulse counter and a descrambler, a delay element block, a key block and a frame code buffer store, the information inputs are the first to eighth register inputs, the first inputs of the comparison circuit and the elements block inputs delays, the outputs are from the first to the ninth outputs of the buffer storage of frame codes, the first output of the comparison circuit is connected to the counting input of the pulse counter, to the first control To the register input and to the second control input of the key block, the second and third outputs of the comparison circuit are combined and connected to the second control input of the register, to the first control input of the key block, to the first control input of the pulse counter and to the input of the ninth category of the buffer code storage frame, the first - the eighth pulse counter outputs are connected to the decoder inputs and through the diodes to the first to eighth inputs of the frame code buffer storage, the decoder output is connected to the second control input of the pulse counter x, through the diode to the first control input of the key block, to the second control input of the register, to the first control input of the pulse counter and to the input of the ninth category of the buffer storage of frame codes, the decoders are identical, each includes series-connected first register, storage of code codes, second register, the first block of keys and the third register, connected in series with the second block of keys, subtracting the pulse counter and decoder, from the first to fourth keys, the first to eighth outputs of the second register are connected in relation to the first to eighth inputs of the first block of keys and the second block of keys, the output of the ninth category of the second register is connected to the second control input of the first block of keys, to the first control input of the second block of keys, to the second control input of the first key, to the first control input of the second key and to the second control inputs of the third and fourth keys, the decoder output is connected to the first control input of the first block of keys, to the second control input of the second block of keys, to the first control inputs of the first th, third and fourth keys, to the second control input of the second key, the output of the first key is connected to the first control input of the third register, the output of the second key is connected to the counting input of the subtracting pulse counter and to the second control input of the third register, the output of the third key is connected to the control input drive code frame, the fourth key output is connected to the control input of the second register, the information input of the decoder is the information input of the first register, the outputs are the first the third output of the third register, the control inputs are: the first is the first control (clock) input of the first register, the second is the combined second control input of the first register and the signal input of the third key, the third is the combined signal inputs of the first, second, fourth keys, the frame code drives are identical , each includes series-connected blocks of registers according to the number of lines (1000) in the frame, the information inputs are the bit-wise combined first to eighth inputs of 1000 register blocks controlling the inputs are: the first is the first control input of the first block of registers, the second is the combined second control inputs of the register blocks, the third is the combined third control inputs of the register blocks, each control output of the previous block of registers is the first control input of each subsequent block of registers, the control output of the last block of registers is connected parallel to the fourth control inputs of all register blocks, the outputs of the frame code storage are parallel outputs of all register blocks (1600 × 8 × 1000) , the register blocks are identical, each includes the first and second keys, a pulse distributor and eight registers, the information input is the bitwise combined third inputs of the bits of the eight registers, the outputs are the parallel outputs of all the bits of the eight registers (1600 × 8), the control inputs are: the first - the first the control input of the first key, the second is the signal input of the second key, the third is the signal input of the first key, the fourth is the first control input of the second key, the output of the first key is connected to the distribution input pulse generator, the outputs of which are connected in series to the first (clock) inputs of the bits in parallel to eight registers, the last output of the pulse distributor is connected to the second control input of the first key and is the control output connected to the first control input of the next block of registers, the output of the second key is connected to the second inputs bits parallel to eight registers and to the second control input of the second key, the shapers of the control signals are identical, each includes a block of shapers them pulses, the input of which is the control input of the driver of control signals, and the code-to-number of radiation pulses converters according to the frame resolution number (1600 × 1000), each of which includes a decryptor connected in series, the first to eighth of which inputs are the converter inputs, the key block from 255 keys, and an output key, a self-propelled pulse distributor (SRI) of 255 bits, the outputs of which are connected to the signal inputs of the corresponding keys in the key block and the power source, the corresponding outputs are decoded and connected to the control inputs of the respective keys in the block of keys, key outputs which are combined and the combined output is connected to the control input (U _off) of the output key signal input of which is connected to the output of the power source, and an output switch output is the output transducer block pulses Formation includes pulse shaping circuits according to the number of transducers "code-number of radiation pulses", the output of each pulse shaping circuit is connected to the SRI input of its converter, information input The drivers of the control signals are the inputs of the decoders of all the converters, the outputs of all the converters are “code-number of radiation pulses”. The flat-panel LED screen contains a glass screen and a matrix of emitting elements made in it according to the frame resolution number (1600 × 1000), each emitting element includes three LED cells (LED cells), each of which emits one of the primary colors, the LED cell includes a white LED and the corresponding color filter on the radiating On the other hand, the control input of each LED is connected to the corresponding output of the corresponding driver of control signals.

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