RU2270529C1 - Digital video-camera - Google Patents

Abstract

FIELD: home video equipment, possible use for recording and reproducing video-images.

SUBSTANCE: into digital video camera containing objective, photo-electric transformer, analog-digital converter of video-signal, digital information accumulator and video range-finder, inserted are: set-point generator, frequencies synthesizer, two analog-digital converters of video-signal, four blocks of AND elements, and reproduction device, containing set-point generator, frequencies synthesizer, three code processing channels E_R, E_G, E_B, 1-6, blocks of pulse amplifiers, block for modulating emissions, two amplifiers and two piezo-deflectors, four bearing voltage sources, blocks for row and frame scanning, projection optical system and matte screen. Resolution of image is 800000 pixels: 800 rows with 1000 counts in each row.

EFFECT: doubly improved resolution and decreased hardware requirements for viewing filmed material.

14 dwg, 3 tbl

Description

The invention relates to household digital video equipment, can be used for recording and playback of video images.

The prototype adopted a digital video camera [1, p. 546], containing a lens, a photoelectric converter, represented by photosensitive arrays of three CCDs, an ADC of a video signal and a codec, a video detector, a recording device on a medium (digital information storage device), control, service and external interface components. The resolution of digital video cameras is up to 400 lines, the pixels in the frame are 400,000 [2, p. 179]. The disadvantages of the prototype are low resolution, to play back the material you need a VCR and a TV. The purpose of the invention is to increase the resolution and reduce equipment for reproducing material. The technical result of the invention is to increase the resolution by half and reduce the equipment for viewing the captured material. The technical result in increasing the resolution of a video image is achieved by doubling the number of lines in a frame from 400 to 800 and the number of samples per line from 500 to 1000 during playback, reducing the equipment for playback by introducing a playback device into the video camera, which eliminates the need for a digital tape recorder and television. A digital video camera generates an image with a frequency of 25 Hz, progressive (progressive) frame scan, the number of lines in a frame 400, samples in a line 500. Analog color video signals E _R , E _G , E _{B are} separately converted into 8-bit codes with 5 MHz sampling. Codes in sequential form enter the solid-state drive digital information. During playback, the codes of color video signals from the digital information storage device are separately sent to the playback device, where the number of lines in the frame is doubled (800) and the number of samples in the lines is doubled (1000). Codes of video signals are converted by LEDs into radiation of three primary colors R, G, B, modulated in brightness, and the electron-optical scan generates a color image on a matte screen.

The essence of the claimed invention is that in a digital video camera containing a lens, a photoelectric converter, an ADC of a video signal, a digital information storage device and a video detector, a master oscillator, a frequency synthesizer, a second and third ADC of a video signal, an ADC of a sound signal, four blocks of And elements and a playback device are introduced The photoelectric converter contains a first amplifier and a first piezoelectric deflector with a reflector at the end, a second amplifier and a second piezoelectric deflector with a reflector at the end, four sources voltages, two dichroic mirrors, three micro-lenses, three photodetectors, three pre-amplifiers, horizontal and vertical blocks, the playback device contains a master oscillator and frequency synthesizer, three channels for processing video signal codes (E _R , E _G , E _B ), six blocks pulse amplifiers, a radiation modulation unit, a first amplifier and a first piezoelectric deflector with an end reflector, a second amplifier and a second piezoelectric deflector with an end reflector, four reference voltage sources, horizontal and vertical scanning units , The projection optical system and a matte screen.

The functional diagram of the digital video camera in figure 1, the functional diagram of the playback device in figure 2, the scan frame in figure 3, the shape of the control voltage in figure 4. The ADC of the video signal in FIG. 5, the ADC of the audio signal in FIG. 6, the design of the piezoelectric deflector in FIG. 7, the video detector circuit in FIG. 8, the summing amplifier in FIG. 9, the code processing unit in FIG. 10, the radiation modulation unit in FIG. 11, the block of elements And in Fig. 12, the delay block in Fig. 13, the scan frame on the screen during playback in Fig. 14.

The digital video camera includes (Fig. 1) a lens 2, a photoelectric converter 1, which is a sensor of three primary colors R, G, B, comprising a first amplifier 3 and a first piezoelectric reflector 4 with a reflector at the end, a first source 5 of positive reference voltage, and a second source 6 negative reference voltage, the horizontal scanning unit 7 from the master oscillator 8 and the output stage 9, the second amplifier 10 and the second piezoelectric deflector 11 connected in series with the reflector at the end, the third source 12 a specific reference voltage, a fourth source of negative reference voltage, a frame scanning unit 14 of an And 15 element, a driving oscillator 16 and a summing amplifier 17, the first 18, the second 19 dichroic mirrors, the first 20, the second 21, the third 22 micro lenses, the first 23, the second 24, third 25 photodetectors, first 26, second 27, third 28 pre-amplifiers, first ADC 29 (video signal E _R ), second ADC 30 (video signal E _G ), third ADC 31 (video signal E _B ), ADC 32 sound signals, in series connected by a master oscillator 33 and a frequency synthesizer 34, the first 35, the second 36, the third 37, the fourth 38 blocks of elements and a digital information storage 39, a video detector 40, a key 41, and a playback device 42 that includes a master oscillator 43, a frequency synthesizer 44, a key 45, an E _R code processing channel from the series connected register E _R 46, a code processing unit 47, a first delay unit 48 and an adder 49 and a second delay unit 50, an E _G code processing channel from a series-connected register E _G 51, a code processing unit 52, a first delay unit 53 and an adder 54 and a second block of 55 delays, channel o processing of E _B codes from a series-connected register E _B 56, a code processing unit 57, a first delay unit 58 and an adder 59 and a second delay unit 60, includes the first to sixth units 61, 62, 63, 64, 65, 66 of pulse amplifiers, unit 67 radiation modulation, connected in series with the first amplifier 68 and the first piezoelectric deflector 69 with a reflector at the end, the first source of positive reference voltage 70, the second source of negative reference voltage 71, the horizontal scanning unit 72 from the master oscillator 73 and the output stage 74, the sequence but the connected second amplifier 75 and the second piezoelectric deflector 76 with a reflector at the end, the third source 77 of the positive reference voltage, the fourth source 78 of the negative reference voltage, the block 79 frame scan from a series-connected element And 80, the oscillator 81 and the summing amplifier 82, includes a projection optical system 83, in the outer focal plane of which is located a matte screen 84, a sound signal register 85, an analogue audio signal generating unit 86 from an ADC, a low-pass filter, and an amplifier dividing power and loudspeaker 87. The ADCs 29, 30, 31 are identical, each includes / Fig. 5/ series-connected video amplifier 88 and piezoelectric deflector 89 with a reflector at the end, a source of positive reference voltage 90, a source of negative reference voltage 91, an emitter from a pulse LED 92 , aperture diaphragm 93 and a micro lens 94, a line 95 of a multi-element photodetector, the input windows of which are located against the reflector of the piezoelectric deflector 89 and are optically connected to the emitter, and the encoder 96. The input of the ADC is a video amplifier input For 88, the output is the outputs of the encoder 96, the control input is the input of the pulse LED 92. The ADC 32 includes (Fig.6) a series-connected voltage divider 97, a key block 98, a matching amplifier 99, an audio frequency amplifier 100 and a piezo-reflector 101 with a reflector at the end , a positive reference voltage source 102, a negative reference voltage source 103, an emitter from a pulsed LED 104, a slit aperture 105 and a micro lens 106, a multi-element photodetector line 107, the input windows of which are opposed to of the piezoelectric deflector 101 and are optically connected to the emitter, and the first decoder 108, the encoder 109 and the register 110, the outputs of which are the outputs of the ADC 32, and the second decoder 111 are connected in series. The input of the ADC 32 is the input of the voltage divider 97, the control input is the input of the pulsed LED 104 .

All piezoelectric deflectors are made identically (Fig. 7), each contains [3, p.118] the first 112, the second 113 piezoelectric elements, the inner electrode 114, the first 115 and the second 116 external electrodes, one end of the piezoelectric plates is fixed in the holder 117, fixed to the free end light reflector 118. Video detector 40 (Fig. 8) contains a first 119, a second 120, a third 121 pulse amplifier units (8 each), a radiation modulation unit 122, a first amplifier 123, and a first piezoelectric deflector 124 with an end reflector, a first source 125 positive reference voltage, second source a negative reference voltage nickname 126, a horizontal scanning unit 127 from a driving generator 128 and an output stage 129, a second amplifier 130 and a second piezoelectric deflector 131 with an end reflector, a third positive voltage reference source 132, a fourth negative reference voltage source 133, a vertical scanning unit 134 of element And 135, the master oscillator 136 and the summing amplifier 137, contains a projection optical system 138, in the outer focal plane of which is located a matte screen 139. The width of the reflector in piezoelectric Ore 124 passed 0.02 mm, length 8 mm (0.02 × 400 mm), the width of the reflector 131 pezodeflektora 0.02 mm, length 10 mm (0,02 mm × 500). The area of the permitting element is 0.0004 mm ² . The summing amplifiers 17, 82, 137 are identical, each includes (Fig. 9) a 9-bit pulse counter 140, a decoder 141, a first 142, a second 143 keys, a first 144, a second 145 pulse shapers and an output amplifier 146. The counter input is a counter input 140 pulses and the first input of the output amplifier 146, the control input is the combined inputs of the control input of the counter 140, the first control input of the key 142 and the second control input of the key 143. The output is the output of the output amplifier 146. Code processing units 47, 52, 57 are identical, each There is (FIG. 10) trigger 147, first 148, second 149 key blocks (8 each), first 150, second 151, third 152, fourth 153 registers, first 154, second 155, third 156 delay blocks, fifth 157 and sixth 158 registers, adder 159 and 16 diodes. The information input is the bitwise combined inputs of the first 148 and second 149 key blocks, they are sent with a frequency of 5 MHz (5 MB / s) color signal codes. The control input is the trigger input 147 and the control input of the adder 159. The output is the bitwise combined outputs of the delay unit 156, the fifth 157 and the sixth 158 registers. From the outputs of the code processing blocks 47, 52, 57, the codes follow at a speed of 10 MB / s.

The radiation modulation unit 67 (Fig. 11) comprises a first emitter 160 of three primary colors, a second emitter 161 of three primary colors and an optical system 162. The emitting planes are located in the rear focal plane of the optical system 162, in the front focal plane of which there is a reflector of the first piezoelectric deflector 69 ( figure 2). The emitters 160, 161 through the optical system 162, the reflectors of the piezoelectric deflectors 69, 76 and the projection optical system 83 are optically connected to the matte screen 84. The inputs of the first emitter 160 are connected to the corresponding outputs of the pulse amplifier units 61, 63, 65, the inputs of the second emitter 161 are connected to the corresponding the outputs of blocks 62, 64, 66 of pulse amplifiers. The frame scan on the screen 84 is performed in two lines simultaneously. The radiation modulation unit 122 (Fig. 8) contains one emitter of three primary colors and an optical system. The radiating plane of the emitter is located in the rear focal plane of the optical system, in the front focal plane of which is the reflector of the first piezoelectric deflector 124. The emitter through the optical system, the reflectors of the piezoelectric deflectors 124, 131 and the projection optical system 138 are optically coupled to the matte screen 139. The inputs of the emitter of block 122 are connected to the corresponding outputs of the blocks 119, 120, 121 of pulse amplifiers. Scanning the frame on the screen 139 is performed in one line, the projection optical system 83 (138) in FIGS. 2 and 8 includes a spherical mirror in series, in the focal plane of which there is a reflector of the second piezoelectric deflector 76 (131), a flat mirror with an inclination of 45 ° relative to the optical axis a spherical mirror and a corrective lens [4 p.370]. Blocks 35, 36, 37 (Fig. 12) are identical, they convert the codes coming in from the ADC 29, 30, 31 in parallel to serial ones before they enter the digital information storage 39. Each of the blocks 35, 36, 37 includes eight elements And ₁ ... And ₈ , a self-propelled distributor of pulses of pulses and element OR. The start pulse U _p 5 MHz comes from the first output of block 34. Block 38 of AND elements is similar to block 35, contains 16 AND ₁ ... AND ₁₆ elements, a self-propelled pulser of pulsed pulses and an OR element. The pulse U _p start are pulses of 80 kHz from the second output of block 34. Blocks 48, 53, 58 of the delay are identical (Fig.13), each includes an And 163 element, the first 164 and second 165 keys, the first 166 and second 167 pulse distributors and eight registers 168 ₁ ... 168 ₈ . The register 168 ₁ receives the first video signal level codes in register 168 receives the second level ₂ codes in the register 168 ₃ - third level codes, ... in the register 168 ₈ bits video signal fed eighth codes.

Each of blocks 48, 53, 58 produces a code delay for a line duration of 100 μs. Information inputs are the combined second inputs of the bits of eight registers 168 _1-8 . The first, second and third control inputs are the first, second inputs of the AND element 163 and the combined key inputs 164, 165. The digital information storage device 39 is represented by four solid-state carriers of the corresponding capacity. 1-3 carriers accumulate codes of video signals, respectively, E _R , E _G , E _B , their capacity is up to 18 GB each, 4th carrier accumulates codes of a sound signal, its capacity is up to 4.6 Gb. The rate of arrival of video signal codes is 5 MB / s, audio signal codes are 1.28 Mb / s. For an hour of operation, the amount of information of each color signal is: 5 MB / s × 3600 s = 18 GB / hour. The amount of audio information per hour is: 1.28 Mbit / s × 3600 s = 4.6 Gbit / hour. The sampling frequency of the video signals in the camcorder:

400 _pp × 25 Hz × 500 _count = 5 MHz,

where 400 _pp × 25 Hz = 10 kHz line frequency,

500 _{frame of reference} - the number of samples in the encoded string.

The clock frequency in the camcorder when filling in the codes of the video signals of block 39 is: 5 MHz × 8 _times = 40 MHz,

where: 5 MHz is the sampling frequency of the video signal,

8 _times - the number of bits in the video signal code, times.

The photoelectric Converter 1 (figure 1) generates three analog video signals supplied to the inputs of the ADC 29, 30, 31, converting the analog video signals E _R , E _G , E _B into 8-bit codes. Blocks of elements And 35, 36, 37, 38 convert parallel codes into sequential ones. Units in codes are represented by the presence of an impulse, zeros by their absence. The master oscillator 33 generates sinusoidal oscillations with a stability of 10 ^-6 . A frequency synthesizer 34 generates the required frequencies from the frequency of the master oscillator 33 and outputs: from the first output, 5 MHz sampling pulses of the video signals, which, when the key 41 is open, are fed to the control inputs of the ADC 29, 30, 31 and the control inputs of blocks 35, 36, 37, from the second output - pulses of 80 kHz sampling of the sound signal received at the input of the ADC 32 and at the control input of block 38, from the third output - pulses of horizontal scanning 5 kHz to the input of block 7 and the first input of block 40, from the fourth - pulses of 12.5 Hz at the second input of the block 14 frame scan and on the second input of block 40, from the fifth - pulses of 10 kHz line frequencies to the first input of block 14 and to the third input of block 40, from the sixth - pulses of 1.28 MHz to the second control input of the drive 39, from the seventh - pulses of 40 MHz to the first control input drive 39 digital information. The ADC 32 converts the sound signals into 16-bit codes, which are supplied in parallel to the first inputs of the AND elements of block 38. Block 7 consists of a master oscillator 8 and an output stage 9. The control voltage is triangular and isosceles (Fig. 4) from block 9 amplified in the amplifier 3 and leads the piezoelectric deflector 4 in oscillatory motion with a frequency of 5 kHz, the scan lines with a frequency of 10 kHz without backward strokes (figure 3).

The signal from the amplifier 3 is supplied to the internal electrode 114 (Fig. 7), the voltage from the source 5 is applied to the external electrode 115, and the voltage from the source 6 is applied to the external electrode 116. Deformation occurs with the supply of the control voltage to the internal electrode [3, p.122 ] piezoelectric plates: one lengthens, the second is shortened, a bending moment of forces occurs, the end face with light reflector 118 rotates and deflects the vertical strip of the image, there is a line scan of the image along the reflector of the piezoelectric deflector 11, which produces weave the image vertically, performing the vertical scan. The operation of the piezoelectric deflector 11 is the same as the piezoelectric deflector 4, but it oscillates with a frequency of 12.5 Hz, 25 frames per second. The width of the reflector of the piezoelectric deflector 4 0.02 mm, the length of not less than 8 mm (0.02 mm × 400 lines), the width of the reflector of the piezoelectric deflector 11 0.02 mm, the length of not less than 10 mm (0.02 × 500). Both line and frame sweeps are performed without reverse moves (figure 3). From the output of the summing amplifier 17, a linearly varying step voltage is amplified, amplified by the amplifier 10. When scanning the odd frames, the reflector of the piezoelectric deflector 11 deflects the image down, while scanning the even frames, up. The summing amplifier 17 sums the triangular voltage from the master oscillator 16 with pulses of 10 kHz, which gives a linear step voltage (Fig. 4) for the amplifier 10. Each pulse of the line moves the next line one step at a time when the beam enters the edge of the frame. It turns out 400 lines per frame. A progressive (progressive) line scan. The purpose of blocks 140-145 (Fig. 9) is to feed negative or positive pulses of the corresponding amplitude and duration to the second input of amplifier 146 at the right time. Before the frame scan, the signal U ₀ 12.5 Hz from the And 15 element (FIG. 1) resets the counter 140. The 9-bit counter counts pulses of 10 kHz lines, the counting cycle is 400. At the end of the sweep of the first (or odd) frame with the arrival of 400 of the 1st pulse, counter 140 generates a binary code 110010000, which is decoded by block 141 into a signal, leading edge closing key 142 and opening key 143, transmitting 10 kHz pulses to the second pulse shaper 145, issuing negative pulses to the second input of amplifier 146. The second ( or even) frame. With the arrival of the next pulse of 12.5 Hz at the input of AND element 15, the counter 140 is reset to zero, the next odd frame is scanned, and then the processes are repeated. The reflected rays from the reflector of the piezoelectric deflector 11 arrive: red rays are reflected from the first dichroic mirror 18 and are collected by a micro-lens 20 into a photodetector 23, blue rays are transmitted by a dichroic mirror 18, reflected from a second dichroic mirror 19 and a micro-lens 22 are collected into a photodetector 25, green rays pass through both mirrors 18, 19 and are assembled by a micro-lens into a photodetector 24. From the photodetectors, analog video signals are fed to their pre-amplifiers 26, 27, 28. The ADCs 29, 30, 31 have one conversion principle, which consists in (FIG. .5) in the sweep of the beam from the LED 92, the reflector of the piezoelectric deflector 89 along the plane of the entrance pupils of the line 95 of the multi-element photodetector. The light pulse is converted by a photodetector of line 95 into an electrical signal that excites the corresponding bus of the encoder 96, which generates a code for the instantaneous value of the input video signal. The sampling frequency is 5 MHz, which is fed to the input of the LED 92. The slit aperture 93 and the micro lens 94 form a beam with an aperture equal to the size of the input window of one photodetector in the line 95. The radiation source is an AL402A LED with a pulse rise time of 25 ns, which satisfies the margin of sampling 5 MHz (200 ns). Line 95 includes 255 photodetectors for encoding video signals with an 8-bit code, ^2-8 . Photodetectors are avalanche photodiodes of the APD with a response time of 10 ns. The output of each photodetector is connected to the corresponding input of the encoder 96, which is represented by the K155IV1 chip [5, p.231] with a response time of 20 ns. The encoder generates codes from 00000001 to 11111111. The first photodetector in line 95 corresponds to the code 00000001, the second - 00000010, the third - 00000011, ... 255-y - 11111111. The conversion time consists of the response time of the photodiode 10 ns and the response time of the encoder 20 ns, in the amount of 30 ns, which is 33 · 10 ⁶ prev / s. Codes E _R with ADC 29 are received in parallel form in the block of elements And 35, codes E _G with ADC 30 are received in block 36, codes E _B with ADC 31 are received in block 37 with a frequency of 5 MHz. The information creation speed by each ADC is: 5 MHz × 8 _bits. = 40 Mbps or 5 MB / s.

The ADC 32 (Fig.6) converts the audio signal into 16-bit codes. The sampling frequency is 80 kHz. The line 107 multi-element photodetector contains 1024 photodetector and converts the audio signal into 10-bit codes 2 ¹⁰ , the resolution is adopted 10 μV. The coding range of the ruler is 0-0.01024 V. The conversion of signals exceeding 2 ¹⁰ into the code is performed by a decoder 108, a second decoder 111, a voltage divider 97 and a key block 98. With their application, the coding range is 0-0.65536 V, i.e. 2 ¹⁶ . From the encoder 109, 16-bit codes are sent to the register 110, from which they are issued in parallel form by 80 kHz sampling signals to block 38. Blocks 35, 36, 37, 38 convert the parallel codes of video signals and sound into serial ones. Codes of video signals E _R , E _G , E _B in sequential form are received in 1-3 solid-state carriers of block 39, codes of audio signals are received in 4th solid-state carrier. At the first control input of block 39, clock pulses U _T 40 MHz are received from the 7th output of block 34, and 1.28 MHz pulses are received from the 6th output of block 34 from the 6th output of block 39. When playing back to the same inputs of block 39, pulses U _t 40 MG and pulses 1.28 MHz from the device 42 playback are received. When shooting, the codes of video signals from the ADC 29, 30, 31 are also received in blocks 119, 120, 121 of the pulse amplifiers of the video detector 40 (Fig. 8), from which they are fed into the emitter of three colors of the radiation modulation unit 122, the beam is scanned horizontally from the block 122 horizontally a piezoelectric deflector 124, to the input of which a triangular control voltage is supplied from a horizontal scanning unit 127, which operates similarly to block 7. A frame scan of the beam is performed by a piezoelectric deflector 131 according to control signals from a vertical scanning unit 134, which operates similarly to block 14. Scanning the program frame essivnaya of 400 lines of 500 samples each, the frame rate of 25 Hz. The width of the piezoelectric reflector reflector 124 0.02 mm, the length of 8 mm (0.02 × 400), the width of the piezoelectric reflector reflector 131 is also 0.02 mm, the length is at least 10 mm (0.02 × 500). The projection optical system magnifies the image by 5 times. The emitter of the three primary colors in block 122 represents a matrix of 24 LEDs, in which 8 LEDs are red, 8 green, and 8 blue. The maximum code of one color signal 11111111, which includes 8 LEDs, the minimum code 00000001 includes one LED to cure. Block 122 modulation of radiation performs luminance modulation of three colors, the distribution of LEDs of the same color according to the weight of the digits in the code are presented in table 1.

Table 1 Discharge number in code 1 senior rank 2 3 four 5 6 7 8 younger discharge LEDs in discharge one one one one one one one one Multiplicity of the filter - 2 ^x 4 ^x 8 ^x 16 ^x 32 ^x 64 ^x 128 ^x

As LEDs, LEDs of the HL MP type, manufactured by the Hewlett-Packard company, are used [6 p. 71]. For red radiation, LEDs HL MP-AL 00 with a light intensity of 0.4 cd, a wavelength of 0.59 cd and a current of 0.02 A are adopted. For green radiation, LEDs HL MP-AM00 with a light intensity of 0.8 cd, a wavelength of 0.526 μm and a current of 0.02 A, for blue radiation - HL MP-AB00 LEDs with a light intensity of 0.3 cd, a wavelength of 0.475 μm and a current of 0.02 A. The brightness modulation is performed by switching on the number of light-emitting diodes corresponding to the discharge weights according to table 1. The brightness, saturation and hue of the resulting color on the screen 139 are determined by the total energy and the mutual ratio of the components of the three colors R, G, B. The total luminous intensity of the emitter of block 122, taking into account that the LEDs of all colors have a light intensity of the blue LED 0.3 cd, is : 3 × 0.3 cd (1 + 0.5 + 0.25 + 0.125 + 0.0625 + 0.03125 + 0.015625 + 0.0078125) = 1.79 cd,

where 3 is the number of colors in the emitter,

0.3 cd - light intensity of the blue LED,

1 ... 0,0078125 - the coefficients of binary bits in the code.

The light intensity of the red and green LEDs with blue is removed either by filters of the corresponding density or by the number of LEDs added to blue. The magnification factor of the image by the projection optical system 139 is adopted 5 times, the screen size of the video detector 40 is:

horizontal 5 · (0.02 mm × 500) = 50 mm = 5 cm,

vertical 5 · (0.02 mm × 400) = 40 mm = 4 cm.

The area of the resolution element on the screen is:

5 × 0.02 mm × 5 × 0.02 mm = 0.1 × 0.1 mm = 0.01 mm ²

or 0.01 · 10 ^-6 m ² .

Given the loss of radiation power when projecting from the emitter of block 122 onto the screen 139 by 20 times, the maximum brightness of the deploying light element (pixel) on a screen with an area of 0.01 · 10 ^-6 m ² is:

where 1.79 cd is the total light intensity of the emitter,

20 - the ratio of the attenuation of light when projected

0.01 · 10 ^-6 m ² - the area of the resolving element on the screen.

The device 42 playback is designed to view the shot material (film) and replaces a digital tape recorder and television. The timing generator 43 outputs a sinusoidal oscillation with the stability of 10. The synthesizer 44 outputs a frequency: from the first output clock of 40 MHz at the input key 45 from the second output pulses U _vyd 1.28 MHz to the second control input of accumulator 39 and digital information to the first control input block 85, from the third - pulses of 80 kHz issuing sound codes from block 85, from the fourth - sampling pulses of 5 MHz (issuing codes from registers 46, 51, 56 and issuing codes from adders 49, 54, 59), from the fifth - pulses 25 Hz to the second control inputs of delay units 48, 53, 58, from the sixth - 10 MHz pulses to the third control inputs of delay units 48, 53, 58, from the seventh - 10 kHz pulses to the first control inputs of blocks 48, 53, 58 and to the first input of the frame 79 block 79, from the eighth - 5 kHz pulses to block 72 horizontal scan, from the ninth - 12.5 Hz pulses to the second input of the frame scan unit 79.

With the power on in block 42, a 12.5 Hz pulse from block 80, which is an odd-frame scan pulse, opens a key 45, which passes clock pulses U _T 40 MHz to the first control inputs of drive 39 (Fig. 2), to the second control input of the block 39, pulses of 80 kHz are received, issuing codes of the audio signal to block 85. Codes of video signals and sound are sent to registers 46, 51, 56, 85, filling in the bits of which take a parallel form. The key 45 in the playback device 42 and the key 41 (Fig. 1) synchronize the filling of the block 39, starting from the first odd frame, and play from the same odd frame in the device 42. The key 41 determines the delivery of codes from the ADC 29, 30, 31 s every odd shot when shooting. Key 45 (figure 2) determines the playback on the screen not from any random place in the frame, but from the beginning of each odd frame. From registers 46, 51, 56, codes of video signals in parallel are issued (by 5 MHz signals supplied to the second control input of the registers) to the inputs of code processing units 47, 52, 57, which double the samples in a row from 500 to 1000. The process of doubling samples in the line in blocks 47, 52, 57 is identical. Doubling is carried out by obtaining intermediate (average) codes between each passing code and the one following it. Block 47 (52, 57) performs the addition (figure 10) of the previous and subsequent codes and dividing the sum code in half. Each code is used twice: the first time as the next, the second time as the previous, so in block 47 (52, 97) there are four registers 150, 151, 152, 153. With the arrival of the first pulse (5 MHz) in trigger 147, the pulse from its first output U _{vyd1 we} issue "0 code" from the register 151 and "0 code" from the register 152 and zero them. The code from register 151 goes to the first inputs of the adder 159, the code from register 152 goes directly to the sixth register 158 and through diodes to the second inputs of the adder 159. At the same time, _Uout1 is a signal U _from1 for key block 148, and _Uoutput1 gives the contents (00000000) register 157 to block 48. The public keys of block 148 pass a “1 code” through delay block 154 to registers 150, 151. Each delay block 154, 155, 156 includes eight delay elements. Block 154 delays the codes by 10 ns so that there is no overlap of the incoming code and issued from the registers 150, 151. “1 code” fills the registers 150, 151. Block 155 delays the codes by 210 ns: 200 ns to restore the succession of the codes one after another and 10 ns to prevent overlapping incoming code issued from registers 152, 153. Adder 159 performs the addition of two codes of the previous and subsequent. As an adder, the K555IM6 microcircuit is used [5 p. 258] with an addition time of 24 ns. The division of the sum of codes by two is performed by shifting the sum code when issuing from the adder by one bit so that the least significant bit in the sum code is discarded, as when dividing the decimal number by ten. A shift by one bit is performed by the corresponding connection of the outputs of the adder 159 to the inputs of the block 156 delays:

после задержки в блоке на 76 нс выдается в блок 48 (53, 58) и в блок 50 (55, 60) задержек. С приходом второго импульса 5 МГц в триггер 147 сигнал U_выд2 со второго выхода выдает из регистра 158 код №2 "0 код" в блок 48. Одновременно с регистра 153 выдается "0 код" в сумматор 159 и "1 код" из регистра 150 в регистр 157 и через диоды в сумматор 159, и открывается сигналом U_от2 блок 149 ключей. Регистры 152, 153 заполняются кодом "2 код". Код №2 из регистра 158 выдается за кодом 1 через 100 нс, регистр 158 хранил код №2 "0 код" 200 нс, но первая половина хранения уходит на сложение в сумматоре (24 нс) и задержку кода в блоке 156 (76 нс). Далее сумматор 159 производит сложение 0 код+1 код, при выходе кода суммы с сумматора в блок 156 сумма делится на два, код №3

выдается на выход блока 47. С приходом 3-го импульса в триггер 147 сигнал U_выд1 (он же U_выд3 последовательному счету) выдает из регистра 157 код №4 "1 код", параллельно выдает из регистра 152 "2 код" в регистр 158 и через диоды в сумматор 159, с регистра 151 "1 код" в сумматор, и сигнал U_от1 открывает ключи блока 148. Регистры 150, 151 заполняются кодом "3 код". Следует сложение в суматоре 1 код+2 код, деление шпалам, и с блока 156 выдается код №5

. В триггер приходит 4-й импульс 5 МГц, с выхода триггера сигнал U_выд2 (он же U_выд4) выдает с регистра 158 код №6 "2 код", из регистра 150 выдает код "3 код" в регистр 157 и в сумматор 159 и открывает сигналом U_от2 ключи в блоке 149, регистры 152, 153 заполняются кодом "4 код", следует сложение 2 код+3 код, деление на два, и с блока 156 выдается код №7

. С приходом в триггер 147 5-го импульса сигнал U_выд1 (он же U_выд5) выдает из регистра 152 "4 код" в регистр 158 и в сумматор 159, из регистра 151 "3 код" в сумматор и открывает ключи в блоке 148. Регистры 150, 151 заполняются кодом "5 код". Идет сложение 3 код + 4 код, деление на два, и о блока 156 выдается код №9

. С приходом 6-го импульса в триггер 147 выдается с регистра 157 код №10 "4 код". Далее процессы повторяются. Выходы регистров 157, 158 и блока 156 поразрядно объединены. Коды с блоков 47, 52, 57 в параллельном виде поступают в блоки 48, 50, 53, 55, 58, 60 с частотой 10 МГц (10 Мбайт/с). Блоки 48, 53, 58 производят задержку кодов на длительность строки 100 нс, работают идентично. С приходом на вход элемента И 163 импульсов 25 Гц и 10 кГц (фиг.13) сигнал U_от с него открывает ключ 164, пропускающий импульсы 10 МГц в распределитель 166 импульсов. Импульсы с распределителя 166 последовательно поступают на первые (тактовые) входы с 1-го по 1000-й разряды восьми регистров 168_1-8. На 1-8 информационные входы блока 48 поступают коды первой строки с блока 47: сигналы первых разрядов кодов строки поступают на вторые входы разрядов (информационные) первого регистра 168₁, сигналы вторых разрядов кодов строки поступают на вторые (информационные) входы разрядов второго регистра 168₂ и т.д., сигналы восьмых разрядов кодов строки поступают на вторые входы разрядов восьмого регистра 168₈. По окончании первой строки все 1000 разрядов восьми регистров заполнены сигналами 1000 кодов строки. В следующие 100 мкс идет выдача 1000 кодов из этих регистров 168_1-8 в сумматор 49 (54, 59) при одновременном заполнении разрядов регистров 168 с сигналами 1000 кодов второй строки. Сигнал с 1000-го выхода распределителя 166 импульсов закрывает ключ 164 и открывает ключ 165. Импульсы 10 МГц через ключ 165 поступают во второй распределитель 167 импульсов, выходы которого подключены к первым входам (тактовым) регистров 168, начиная не с первого, а с 1000-го разряда. В связи с тем, что развертка второй строки идет (фиг.13) встречно первой строке, выдача кодов с регистров 168 производится не с 1-го разряда регистров 168, а с 1000-х разрядов, т.е. в обратном порядке. Это выполняется вторым распределителем 168 импульсов, выходы которого подключены. к первым входам разрядов регистров 168_1-8 в обратном порядке: первый выход подключен к 1000-м разрядам, а 1000-й выход подключен к первым разрядам регистров 168_1-8. При развертке нечетных строк выдача кодов с регистров 168 начинается с первых разрядов, при развертке четных строк выдача кодов начинается с 1000-х разрядов регистров 168. На первые входы сумматора 49 (54, 59) приходит код текущей строки с блока 47, на вторые входы сумматора 49 приходит с блока 48 код того же отсчета, но задержанный на 100 мкс (длительность строки). Сумматоры 49, 54, 59 идентичны, представлены микросхемами К555ИМ6, выполняют сложение кодов одних и тех же отсчетов предыдущей и последующей строк, деление суммы на два выполняется подключением выходов сумматора и входов блоков импульсных усилителей 61, 63, 65, как описано на с. 20 описания. Блоки 50, 55, 60 задержек выполняют задержку кодов на время сложения в сумматорах 49, 54, 59, т.е. на 24 нс. С выходов блоков 50, 55, 60 выдаются коды удвоенных отсчетов 400 строк, с выходов блоков 49, 54, 59 выдаются коды удвоенных отсчетов промежуточных 400 строк, что в сумме в кадре на экране составляют 800 строк. Блоки импульсных усилителей 61-66 представлены микросхемами 533AП6 с временем срабатывания 18 нс [5, с.128]. Каждый блок включает по 12 импульсных усилителей.Bit 0 is a carry bit when summing codes. When doubling the samples, they are followed with a sampling not of 5 MHz, but of 10 MHz, i.e. after 100 ns. Addition takes 24 ns; therefore, block 156 must delay the codes for another 76 ns (100 ns - 24 ns). After adding the codes, the code of the sum is divided by two, and code No. 1

after a delay of 76 ns in the block, it is issued in block 48 (53, 58) and in block 50 (55, 60) of delays. With the arrival of the second 5 MHz pulse in trigger 147, the signal U _vy2 from the second output gives code No. 2 "0 code" from block 158 to block 48. At the same time, "0 code" is sent to adder 159 from register 153 and "1 code" from register 150 to the register 157 and through the diodes to the adder 159, and is opened by a signal U from ₂ block 149 keys. Registers 152, 153 are filled with the code "2 code". Code No. 2 from register 158 is issued for code 1 after 100 ns, register 158 stored code No. 2 "0 code" 200 ns, but the first half of storage is spent on addition in the adder (24 ns) and code delay in block 156 (76 ns) . Next, the adder 159 adds 0 code + 1 code, when the sum code from the adder goes to block 156, the amount is divided into two, code No. 3

is issued to the output of block 47. With the arrival of the third pulse in trigger 147, the signal U _add1 (aka U _{add3 to the} sequential account) generates code No. 4 "1 code" from register 157, and simultaneously issues 152 "2 code" from register 158 to register 158 and through the diodes to the adder 159, from register 151 "1 code" to the adder, and the signal U _{from 1} opens the keys of block 148. Registers 150, 151 are filled with the code "3 code". Addition follows in the adder 1 code + 2 code, the division of sleepers, and from block 156 issued code number 5

. The 4th pulse of 5 MHz comes into the trigger, from the output of the trigger the signal U _out2 (aka U _out4 ) gives code number 6 "2 code" from register 158, from the register 150 it gives the code "3 code" to register 157 and to the adder 159 and opens with a signal U from _{2 the} keys in block 149, the registers 152, 153 are filled with the code "4 code", followed by the addition of 2 code + 3 code, division by two, and code No. 7 is issued from block 156

. With the arrival of the 5th pulse in trigger 147, the signal U _add1 (aka U _output5 ) issues from register 152 a “4 code” to register 158 and to adder 159, from a register 151 “3 code” to an adder and opens the keys in block 148. Registers 150, 151 are filled with the code "5 code". There is addition 3 code + 4 code, division by two, and about block 156 code number 9 is issued

. With the arrival of the 6th pulse in the trigger 147 is issued from the register 157 code No. 10 "4 code". Next, the processes are repeated. The outputs of the registers 157, 158 and block 156 are bitwise combined. Codes from blocks 47, 52, 57 in parallel are received in blocks 48, 50, 53, 55, 58, 60 with a frequency of 10 MHz (10 MB / s). Blocks 48, 53, 58 delay the codes for a line duration of 100 ns; they work identically. With the arrival of the input element And 163 pulses of 25 Hz and 10 kHz (Fig) signal U _from it opens the key 164, transmitting 10 MHz pulses to the pulse distributor 166. The pulses from the distributor 166 sequentially arrive at the first (clock) inputs from the 1st to the 1000th bits of eight registers 168 _1-8 . Codes of the first line from block 47 are received at 1-8 information inputs of block 48: the signals of the first bits of the code of the line are sent to the second inputs of the bits (information) of the first register 168 ₁ , the signals of the second bits of code of the line are sent to the second (information) inputs of the bits of the second register 168 ₂ , etc., the signals of the eighth bits of the line codes are fed to the second inputs of the bits of the eighth register 168 ₈ . At the end of the first line, all 1000 bits of eight registers are filled with signals of 1000 line codes. In the next 100 μs, 1000 codes from these registers 168 _1-8 are output to the adder 49 (54, 59) while filling in the bits of the registers 168 with the signals of 1000 codes of the second line. The signal from the 1000th output of the pulse distributor 166 closes the key 164 and opens the key 165. 10 MHz pulses through the key 165 enter the second pulse distributor 167, the outputs of which are connected to the first inputs (clock) of the registers 168, starting not from the first, but from 1000 th category. Due to the fact that the second line is scanned (Fig. 13) opposite the first line, codes from registers 168 are not issued from the first digit of registers 168, but from 1000 digits, i.e. in reverse order. This is done by a second pulse distributor 168, the outputs of which are connected. to the first inputs of the bits of the registers 168 _1-8 in the reverse order: the first output is connected to the 1000th bits, and the 1000th output is connected to the first bits of the registers 168 _1-8 . When developing odd lines, the issuance of codes from registers 168 starts from the first digits, when developing even lines, the issuance of codes starts from 1000 digits of registers 168. The code of the current line from block 47 comes to the first inputs of adder 49 (54, 59), to the second inputs adder 49 comes from block 48 code of the same count, but delayed by 100 μs (line length). Adders 49, 54, 59 are identical, represented by K555IM6 microcircuits, perform the addition of codes of the same samples of the previous and subsequent lines, dividing the sum by two is done by connecting the outputs of the adder and the inputs of the pulse amplifier modules 61, 63, 65, as described on page. 20 descriptions. Blocks 50, 55, 60 of the delays perform code delay for the addition time in adders 49, 54, 59, i.e. at 24 ns. From the outputs of blocks 50, 55, 60, codes of doubled samples of 400 lines are issued, from the outputs of blocks 49, 54, 59 codes of doubled samples of intermediate 400 lines are given, which total 800 lines in a frame on the screen. Blocks of pulse amplifiers 61-66 are represented by 533AP6 microcircuits with a response time of 18 ns [5, p.128]. Each unit includes 12 pulse amplifiers.

The radiation modulation unit 67 performs luminance modulation of three colors of two lines simultaneously, respectively, of the code values. The first emitter 160 brightness modulated beam reproduces 400 lines obtained during shooting. The second emitter 161 modulated in brightness beam reproduces another 400 lines of intermediate, the codes of which are obtained by adders 49, 54, 59 (Fig.14). The 84 frames reproduced on the screen include 800 lines with 1000 samples in each, which is 800,000 pixels, each of the emitters 160, 161 contains 36 LEDs: 12 LEDs of red radiation, 12 - green and 12 - blue radiation, all types of HLMP companies Hewlett-Packard "[6 p. 71].

The total radiation of the LEDs of three colors from each emitter is mixed by the optical system 162 when focusing in two color spots on the reflector of the first piezoelectric deflector 69 (Fig.2). The brightness, saturation and hue of the resulting color on the screen 84 is determined by the total energy and the mutual ratio of the three colors from each emitter. The distribution of LEDs of the same color among the digits in the code is given in table 2.

table 2 Discharge number in code 1 senior rank 2 3 four 5 6 7 8 young. bit LEDs in code four 2 one one one one one one Multiplicity of the filter - - - 2 ^x 4 ^x 8 ^x 16 ^x 32 ^x

Brightness modulation is performed by switching on the LEDs according to the weights of the bits of the code according to Table 2. Horizontal scanning of the image is performed by the piezoelectric deflector 69, the width of the reflector is 0.04 mm. A vertical scan with a step of two lines is performed by a piezoelectric deflector 76, the width of its reflector is not less than 0.08 mm (0.04 × 2), length not less than 40 mm, 0.04 mm × 1000 counts. The maximum luminous intensity of a deploying element from one emitter, taking into account that all LEDs have a light intensity of 0.3 cd blue LEDs, is:

3 × 3 cd (4 + 2 + 1 + 0.5 + 0.25 + 0.125 + 0.0625 + 0.03125) = 0.9 cd × 7.97 = 7.17 cd

where 0.5-0.03125 - the coefficients of the binary code in 4-8 bits.

Given the loss of radiation power of one emitter when projecting to the screen 30 times, the maximum brightness of one deploying element (pixel) with an area increased by a factor of 10 by 0.4 × 0.4 mm, 0.16 mm ^{2 by the} projection optical system is:

where in the numerator the total light intensity of one emitter,

0.16 mm ² = 0.16 · 10 ^-6 m ² - the area of the resolving element on the screen.

The magnification of the image by the projection system 83 is adopted 10 times, the dimensions of the screen 84 are:

horizontal 10 × (0.04 mm × 1000) = 400 mm = 40 cm,

vertical 10 × (0.04 mm × 800) = 320 ml = 32 cm,

diagonal 51 cm or 20 inches.

The piezoelectric deflector 69 according to the control voltage from the amplifier 68 produces a line scan of two beams on the reflector of the piezoelectric deflector 76 (Fig. 2), performing a frame scan along with the line scan on the screen 84. The piezoelectric deflectors are controlled by the control voltages from block 72 and 79. The piezoelectric deflector 69 oscillates with a frequency of 5 kHz, creating a line frequency of 10 kHz. The piezoelectric deflector 76 oscillates at a frequency of 12.5 Hz, creating a frame rate of 25 Hz. Line scanning is progressive without reverse moves. The operation of the summing amplifier 82 is similar to the operation of the summing amplifier 17. The sound codes from the 4th output of the digital information storage 39 enter the sound signal register 85, where the codes take a parallel form and are output from it into block 86, in which the codes are converted into analog signals, pass filtering in a low-pass filter, amplified by power and supplied to the loudspeaker 87. Technical parameters of the inventive device in table 3.

Table 3 Technical specifications Values Imaging Color coding of video signals 4: 4: 4, E _R , E _G , E _B Clock frequency 40 MHz Frame frequency 25 Hz Number of lines / number of encoded lines 400/400 The number of encoded samples in the lad 500 Line Scan / Line Frequency 5 kHz / 10 kHz Line scan in frame progressive without reverse gears Video Sampling 5 MHz (400 · 25 · 500) Video coding 255 level, 8 bits, 2 ⁸ Line length 200 μs Video Encoding Method separate, linear PCM ADC conversion speed 33 · 10 ⁶ prev / s Audio sampling 80 kHz Sound coding 65536 level, 16 times, 2 ¹⁶ Play Frame frequency 25 Hz The number of lines in the frame 800 (400 × 2) The number of samples per line 1000 (500 × 2) Video Sampling 10 MHz (5 MHz × 2) Frame scan two lines at a time Frame resolution 800,000 pixels Frame format 1.25: 1 Imaging on a matte screen no picture tube, optoelectronic scan and projection with 10 ^x magnification Screen size 40 × 32 cm
diagonal 51 cm Maximum brightness of one expanding element on the screen 1.4 × 10 ⁶ cd / m ²

The operation of a digital video camera.

With the power on, the 12.5 Hz pulse opens the key 41 (Fig. 1), the 5 MHz sampling pulses are sent from the key 41 to the ADC clock inputs 29, 30, 31. The video signal codes are sent to blocks 35, 36, 37, where they are converted from parallel to serial and fed to 1-3 inputs of the drive 39 digital information. With the ADC 29, 30, 31, the codes also enter the video detector 40, normalizing the image of the frame 5 × 4 cm on the screen (Fig. 8). When the movie is played by the playback device 42 (FIG. 2), 12.5 Hz pulses from block 80 open the key 45, and codes from block 39 are issued to registers 46, 51, 56, 85, from which they are issued in parallel to blocks 47, 52 , 57, where the samples of the video signals are doubled in each row. Codes of lines from block 39 through blocks of delay 50, 55, 60 (for 24 ns) arrive at blocks 62, 64, 66 of pulse amplifiers, are amplified to the required value, and are fed to the inputs of emitter 160 LEDs at block 67. Codes of the intermediate segment obtained by adders 49, 54, 59, are supplied to pulse amplifier units 61, 63, 65, the signals are amplified and fed to the corresponding LEDs of the second emitter 161 of block 67. The brightness-modulated radiation of two rays is focused by the optical system 162 (Fig. 11) on the piezoelectric reflector 69, performing lowercase Wrapping simultaneously two lines on the reflector of the piezoelectric deflector 76. The projection optical system 83 projects the image of the frame with a magnification of 10 times on the matte screen 84.

The result of the claimed device is a 2-fold increase in the resolution of the image against the prototype and the replacement by the playback device of two devices necessary for viewing the captured material by the prototype: a digital video recorder and a TV.

Information sources

1. Murakhovsky V.I. Computer device. M .: AST-PRVSS book, 2003, p. 546, prototype.

2. On.N. Partala. Camcorders M.: Science and Technology, 2000, p. 179, table 10.3.

3. Fridland M.V., Soshnikov V.G. Automatic control systems in video recording devices. M., 1988, p.118 fig.5.5, p.122 fig.5.10.

4. Samoilov V.F., Lame B.P. The television. M., 1975, p. 370.

5. Digital integrated circuits. Directory. Minsk, 1991, p. 128, 231, 258.

6. "Radio" No. 7, 1998, p. 71.

Claims (1)

A digital video camera containing a lens, a photoelectric converter, a first ADC of a video signal, a digital information storage device and a video detector, characterized in that a driving oscillator and a frequency synthesizer are inserted into it, a key whose input is connected to the first output of the frequency synthesizer, the second and third ADCs video signal, ADC of a sound signal, to the input of which a sound signal is supplied and its control input is connected to the second output of the frequency synthesizer, the control inputs of the first, second, third ADC video drove connected to the key output, 1-4 blocks of AND elements and a playback device are introduced, inputs of 1-3 blocks of elements AND are connected respectively to the outputs 1-3 of the ADC of the video signal, the inputs of the fourth block of elements And are connected to the outputs of the ADC of the sound signal, outputs 1-4 blocks of elements And are connected to the corresponding 1-4 information inputs of the digital information storage device, the first and second control inputs of which are connected to the seventh and sixth outputs of the frequency synthesizer and to the first and second outputs of the playback device, 1-4 information the input inputs of which are connected to 1-4 outputs of the digital information storage device, the control inputs of 1-3 blocks of elements And are connected to the first output of the frequency synthesizer, the control input of the fourth block of elements And is connected to the second output of the frequency synthesizer, the photoelectric converter contains a first amplifier and a first connected in series a piezoelectric deflector with a reflector at the end located in the rear focal plane of the lens, the first source of positive reference voltage, the output of which is connected to the second input m of the first amplifier and the first piezoelectric deflector, the second source of negative reference voltage, the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector, serially connected to the second amplifier and the second piezoelectric reflector at the end, which is optically connected to the reflector of the first piezoelectric deflector, the third source of positive reference voltage the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector, the fourth source of negative reference voltage the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector, the first and second dichroic mirrors located one after another and opposite the reflector of the second piezoelectric deflector, 1-3 micro lenses, 1-3 photodetectors, the input windows of which are located in the focal planes of the first, the second and third micro-lenses, three pre-amplifiers, the inputs of which are connected to the outputs of the respective photodetectors, and their outputs are the outputs of the photoelectric converter and connected to the input m, respectively, 1-3 ADCs of a video signal, a horizontal scanning unit including a master oscillator and an output stage, the output of which is connected to the first input of the first amplifier, and the master oscillator input is connected to the third output of the frequency synthesizer, a vertical scanner, the first and second inputs of which are connected to the fifth and fourth outputs of the frequency synthesizer, the output of the frame scan unit is connected to the first input of the second amplifier, the input window of the first photodetector is optically connected through the first micro lens and the first dichroic a mirror with a reflector of the second piezoelectric deflector, the input window of the second photodetector is optically connected through the second micro-lens and through both dichroic mirrors with a reflector of the second piezoelectric reflector, the input window of the third photodetector is optically connected through the third micro-lens, the second dichroic mirror and through the first dichroic mirror with the reflector of the second piezoelectric deflector the frame scan contains a series-connected element And, the master oscillator and the summing amplifier, the second input of which is connected to the first input of the And element, the control input of the summing amplifier is connected to the output of the And element and to the control input of the key, the output of the summing amplifier is connected to the first input of the second amplifier of the photoelectric converter, the first, second, third ADCs of the video signal are identical, each includes a series-connected video amplifier and a piezoelectric deflector with reflector at the end, a source of positive reference voltage and a source of negative reference voltage, the outputs of which are connected respectively to the second and to the three inputs of the video amplifier and piezoelectric deflector, an emitter from a pulsed LED, a slit diaphragm, and a micro lens, the array of a multi-element photodetector and an encoder connected in series, the outputs of which are the ADC outputs of the video signal, the input windows of the line of a multi-element photodetector are optically connected through a piezoelectric reflector, and the input the control input is the pulse LED input, the ADC of the sound signal contains series-connected divide voltage, key block, matching amplifier, audio amplifier and piezoelectric deflector with a reflector at the end, a source of positive reference voltage, a source of negative reference voltage, the outputs of which are connected to the second and third inputs of the audio frequency amplifier and piezoelectric deflector, emitter from a pulsed LED, slot aperture and micro lens, series-connected array of multi-element photodetector, the first decoder, encoder and register, the outputs of which are the output The ADC of the sound signal contains a second decoder, the inputs of which are connected to the encoder outputs and the outputs are connected to the corresponding inputs of the first decoder and the key block inputs, the input windows of the multi-element photodetector line are optically connected to the emitter through the piezoelectric reflector, and the voltage divider input is the input of the ADC the input is the input of a pulsed LED, combined with the control input of the register, 1-3 blocks of AND elements are identical, each includes 1-8 AND elements, the first inputs of which are are the inputs of the unit and are connected respectively to 1-8 outputs of their ADC video signal, a self-propelled pulse distributor, 1-8 outputs of which are connected to the second inputs of 1-8 AND elements, and an OR element, 1-8 inputs of which are connected to the outputs of 1-8 elements And, and the output of the OR element is the output of the block, the control input of which is the input of the self-propelled pulse distributor, connected to the first output of the frequency synthesizer, the fourth block of elements And includes 1-16 elements And, the first inputs of which are the inputs of the block and are connected to 1-16 the ADC of the sound signal, a self-propelling pulse distributor, 1-16 outputs of which are connected to the second inputs of 1-16 AND elements, and an OR element, whose inputs are connected to the outputs of 1-16 AND elements, and the output is the output of the unit, the input of which is the input a self-propelled pulse distributor connected to the second output of the frequency synthesizer, the video detector contains the first, second, third blocks of pulse amplifiers, the outputs of which are connected to the corresponding inputs of the radiation modulation unit, which includes an emitter of three bases colors and an optical system, the first amplifier and the first piezoelectric deflector in series with the end reflector, the first positive reference voltage source, the second negative reference voltage source, the outputs of which are connected to the second and third inputs of the first amplifier and the first piezoelectric deflector, the second amplifier and a second piezoelectric deflector with a reflector at the end, a third source of positive reference voltage, a fourth source of negative reference voltage, the outputs of which are connected respectively to the second and third inputs of the second amplifier and the second piezoelectric deflector, a projection optical system of sequentially spherical mirrors, in the focal plane of which there is a reflector of the second piezoelectric deflector, a flat mirror with an inclination of 45 ° relative to the axis of the spherical mirror and a corrective lens, matte a screen located in the external focal plane of the projection optical system, and through it, the reflectors of the second and first piezoelectric deflectors, the optical system of the radiation modulation unit is optically connected to the emitter of three primary colors, includes a line scan unit from a master oscillator, the input of which is the input of the unit, and an output stage, the output of which is connected to the first input of the first amplifier, a frame scan unit from a series-connected element And defining generator and summing amplifier, the output of which is connected to the first input of the second amplifier, and the control input is connected to the output of the element And, the first input of which is the second the frame scan unit, the second input of the And element and the second input of the summing amplifier are combined and are the first input of the frame scan unit, the information inputs of the video detector are the inputs of 1-3 pulse amplifier units, 1-3 the control inputs are the horizontal scan input, second and first frame scan inputs, the playback device contains a serially connected master oscillator, a frequency synthesizer and a key whose output is connected to the first control inputs Delya digital information, channel processing E codes _R including serially connected register E _R , the information input of which is connected to the first output of the digital information storage device, a code processing unit, a first delay unit and an adder, and a second delay unit, whose inputs are connected to the outputs of the code processing unit and to the first inputs of the adder, an E code processing channel _G including serially connected register E _G , the information input of which is connected to the second output of the digital information storage device, a code processing unit, a first delay unit and an adder, and a second delay unit, whose inputs are connected to the outputs of the code processing unit, and to the first inputs of the adder, an E code processing channel _B including serially connected register E _B the information input of which is connected to the third output of the digital information storage device, the code processing unit, the first delay unit and the adder, and the second delay unit, whose inputs are connected to the outputs of the code processing unit and to the first inputs of the adder, the first control inputs of the E registers _R , E _G , E _B 1-3 channels are connected in parallel to the key output, the second control inputs of the E registers _R , E _G , E _B and the control inputs of the processing units of codes 1-3 channels are connected to the fourth output of the frequency synthesizer, the first, second, third control inputs of the first delay blocks are connected to the seventh, fifth and sixth outputs of the frequency synthesizer, the control inputs of the adders are connected to the fourth output of the frequency synthesizer, contains 1-6 blocks of pulse amplifiers, a radiation modulation block, the corresponding inputs of which are connected to the outputs of the blocks of pulse amplifiers, the inputs of which are connected to the outputs of the corresponding sum orov and second delay units, the first amplifier and the first piezoelectric deflector in series with the reflector at the end, the first source of positive reference voltage, the second source of negative reference voltage, the outputs of which are connected respectively to the second and third inputs of the first amplifier and the first piezoelectric deflector, the second amplifier and a second piezoelectric deflector with a reflector at the end, a third source of positive reference voltage, a fourth source of negative reference voltage lines whose outputs are connected respectively to the second and third inputs of the second amplifier and the second piezoelectric deflector, a horizontal scanning unit from the master oscillator and the output stage, the output of which is connected to the first input of the first amplifier, the input of the horizontal scanning unit is connected to the eighth output of the frequency synthesizer, the frame scanning unit identical to the vertical scanning unit in the photoelectric converter, its first input is connected to the seventh output of the frequency synthesizer, the second input is connected to the ninth output of the synthesizer frequencies, the first output of the vertical scanning unit is connected to the first input of the second amplifier, the second output is connected to the control input of the key, includes a projection optical system containing a consecutive spherical mirror, a flat mirror with an inclination of 45 ° relative to the axis of the spherical mirror and a correction lens in the external focal the plane of the projection optical system has a matte screen, in the focal plane of the spherical mirror there is a reflector of the second piezoelectric deflector, which through The first piezoelectric deflector is optically connected to the radiating side of the radiation modulation unit, and it contains serially connected sound signal register, analog audio signal generating unit and loudspeaker, the sound signal register information input is connected to the fourth output of the digital information storage device, the first control input is connected to the second output of the frequency synthesizer , the second control input is connected to the third output of the frequency synthesizer, the code processing units are identical, each contains a trigger ep, first and second key blocks, 1-6 registers, 1-3 delay blocks, adder and the corresponding number of diodes, information inputs of the first and second registers are combined and through the first block of delays connected to the outputs of the first key block, information inputs of the third and fourth registers combined and through the second block of delays connected to the outputs of the second block of keys, the information input of the block of code processing are bitwise combined inputs of the first and second blocks of keys, the control input is the trigger input, connect connected to the fourth output of the frequency synthesizer, the first trigger output is connected to the control inputs of the second and third registers, the first key block and the fifth register, the second trigger output is connected to the control inputs of the first, fourth registers, the second key block and the sixth register, the first inputs of the adder are connected to the outputs of the second register and through the diodes to the outputs of the first register, the second inputs of the adder are connected to the outputs of the fourth register and through the diodes to the outputs of the third register, the control input of the adder is connected to the trigger input, the outputs of the adder are appropriately connected to the inputs of the third delay block, the inputs of the fifth register are connected to the outputs of the first register, the inputs of the sixth register are connected to the outputs of the third register, the outputs of the fifth, sixth registers and the third delay block are bitwise combined and are outputs of the code processing unit , the first delay blocks are identical, each includes a first key and a first pulse distributor connected in series, a second key and a second distributor connected in series pulse train, eight registers and an element And, the first and second inputs of which are the first and second control inputs of the delay unit and are connected to the seventh and fifth outputs of the frequency synthesizer, the signal inputs of the first and second keys are combined, are the third control input that is connected to the sixth output frequency synthesizer, the output of the And element is connected to the first control input of the first key and to the second control input of the second key, the outputs of the first pulse distributor are connected in series to the first (so merchandise) inputs of the bits of eight registers, the first output connected to the first inputs of the first bits of eight registers, and the last output connected to the second control input of the first key and the first control input of the second key and connected through the diode to the first inputs of the last (1000s) bits of eight registers, the outputs of the second pulse distributor are connected in series to the first (clock) control inputs of the bits of eight registers, and the first output is connected to the first control inputs of the last (1000's) bits of eight registers, the last output is connected through a diode to the first inputs of the first bits of eight registers and through a diode connected to the first control input of the second key, the second inputs of the bits of each register are combined and are 1-8 information inputs of the first delay block, the outputs of the bits in each register are combined and are 1-8 outputs of the first delay unit, the radiation modulation unit contains an optical system in the rear focal plane of which are the first and second emitters of three primary colors, each containing the corresponding number of LEDs of red, green, and blue radiation, the reflector of the first piezoelectric deflector is located in the front focal plane of the optical system, the inputs of the radiation modulation block are the inputs of the first and second emitters connected to the outputs of the pulse amplifier blocks, summing the amplifiers of the vertical scan units of the photoelectric converter, the playback device, and the video finder is identical, each includes a serially connected pulse counter, decoder, first and second to yuchi, the first and second pulse shapers and the output amplifier, the inputs are the counting input of the pulse counter and the first input of the output amplifier, the output of which is the output of the summing amplifier, the decoder output is connected to the second control input of the first key and to the first control input of the second key, signal inputs of the keys combined and connected to the input of the pulse counter, the control input of which, the first control input of the first key and the second control input of the second key are combined and are control input of the summing amplifier, the first switch output is connected to the input of the first pulse generator, the second switch output is connected to the input of the second pulse generator, the outputs of the first and second pulse generator are combined and connected to the second input of the output amplifier.

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