NO995556L - Fremgangsmåte og anordning for å forbinde en prosessor med en ASIC - Google Patents

Fremgangsmåte og anordning for å forbinde en prosessor med en ASIC

Info

Publication number
NO995556L
NO995556L NO995556A NO995556A NO995556L NO 995556 L NO995556 L NO 995556L NO 995556 A NO995556 A NO 995556A NO 995556 A NO995556 A NO 995556A NO 995556 L NO995556 L NO 995556L
Authority
NO
Norway
Prior art keywords
processor
asic
arrangement
signals
state
Prior art date
Application number
NO995556A
Other languages
English (en)
Norwegian (no)
Other versions
NO995556D0 (no
Inventor
Olli Piirainen
Aki Happonen
Original Assignee
Nokia Networks Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Networks Oy filed Critical Nokia Networks Oy
Publication of NO995556L publication Critical patent/NO995556L/no
Publication of NO995556D0 publication Critical patent/NO995556D0/no

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Electrotherapy Devices (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Small-Scale Networks (AREA)
  • Hardware Redundancy (AREA)
NO995556A 1997-05-15 1999-11-12 Fremgangsmåte og anordning for å forbinde en prosessor med en ASIC NO995556D0 (no)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI972091A FI105727B (fi) 1997-05-15 1997-05-15 Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin
PCT/FI1998/000402 WO1998052123A2 (fr) 1997-05-15 1998-05-12 Procede et agencement de connexion d'un processeur a un circuit integre specifique

Publications (2)

Publication Number Publication Date
NO995556L true NO995556L (no) 1999-11-12
NO995556D0 NO995556D0 (no) 1999-11-12

Family

ID=8548861

Family Applications (1)

Application Number Title Priority Date Filing Date
NO995556A NO995556D0 (no) 1997-05-15 1999-11-12 Fremgangsmåte og anordning for å forbinde en prosessor med en ASIC

Country Status (10)

Country Link
US (1) US6654844B1 (fr)
EP (1) EP0988603B1 (fr)
JP (1) JP2001526810A (fr)
CN (1) CN1256769A (fr)
AT (1) ATE231256T1 (fr)
AU (1) AU736765B2 (fr)
DE (1) DE69810769T2 (fr)
FI (1) FI105727B (fr)
NO (1) NO995556D0 (fr)
WO (1) WO1998052123A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1295685A (zh) 1998-06-17 2001-05-16 诺基亚网络有限公司 连接以不同时钟速度速率工作的设备的接口装置,和操作该接口的方法
US6789153B1 (en) * 2001-02-20 2004-09-07 Lsi Logic Corporation Bridge for coupling digital signal processor to on-chip bus as slave

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0340901A3 (fr) 1988-03-23 1992-12-30 Du Pont Pixel Systems Limited Système d'accès pour mémoire à double porte
GB2217064A (en) 1988-03-23 1989-10-18 Benchmark Technologies Interfacing asynchronous processors
US5335338A (en) 1991-05-31 1994-08-02 Micro Solutions, Inc. General purpose parallel port interface
US5255375A (en) * 1992-01-10 1993-10-19 Digital Equipment Corporation High performance interface between an asynchronous bus and one or more processors or the like
US5339395A (en) * 1992-09-17 1994-08-16 Delco Electronics Corporation Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode
US5325491A (en) * 1993-04-13 1994-06-28 International Business Machines Corporation Method and apparatus for extending a computer bus
US5428623A (en) * 1993-07-01 1995-06-27 Tandem Computers Incorporated Scannable interface to nonscannable microprocessor
US5758107A (en) * 1994-02-14 1998-05-26 Motorola Inc. System for offloading external bus by coupling peripheral device to data processor through interface logic that emulate the characteristics of the external bus
US5680594A (en) 1995-05-24 1997-10-21 Eastman Kodak Company Asic bus interface having a master state machine and a plurality of synchronizing state machines for controlling subsystems operating at different clock frequencies
US5987590A (en) * 1996-04-02 1999-11-16 Texas Instruments Incorporated PC circuits, systems and methods

Also Published As

Publication number Publication date
WO1998052123A3 (fr) 1999-02-04
US6654844B1 (en) 2003-11-25
ATE231256T1 (de) 2003-02-15
WO1998052123A2 (fr) 1998-11-19
DE69810769D1 (de) 2003-02-20
AU736765B2 (en) 2001-08-02
FI972091A (fi) 1998-11-16
EP0988603A2 (fr) 2000-03-29
FI105727B (fi) 2000-09-29
CN1256769A (zh) 2000-06-14
EP0988603B1 (fr) 2003-01-15
NO995556D0 (no) 1999-11-12
FI972091A0 (fi) 1997-05-15
AU7433898A (en) 1998-12-08
JP2001526810A (ja) 2001-12-18
DE69810769T2 (de) 2003-09-25

Similar Documents

Publication Publication Date Title
EP1024663A3 (fr) Dispositif de traitement d'image
EP0936785A3 (fr) Compensation de décalage pour transmission en parallèle
CA2065853A1 (fr) Circuit d'extraction de signaux asyndrones
DK0470140T3 (da) Apparat og metode til kalibrering af et sensorsystem
TW353176B (en) A semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor
EP0334357A3 (fr) Dispositif pour l'insertion d'impulsion
US6055248A (en) Transmission frame format converter circuit
NO995556D0 (no) Fremgangsmåte og anordning for å forbinde en prosessor med en ASIC
KR930008666A (ko) 보조 문서에 의해 운반된 자기 스트라이프 상에 기록된 기존의 코드화 메시지 대신에 새로운 코드화 메시지를 상기 문서의 수동 변위에 의해 기록하는 방법 및 시스템
KR970008379B1 (en) Method and apparatus for decreasing side blank of wide screen
JPS5628560A (en) Compression data restoration system
HUP9902497A2 (hu) Optikai felvételi eljárás és készülék az eljárás foganatosítására
MY137731A (en) Recording and reproducing apparatus
KR100215437B1 (ko) 디지탈비데오디스크플레이어의 아이, 디 데이타 전송방법
JPS6448175A (en) Address control method for picture memory
JP2850875B2 (ja) 位相調整用メモリ
KR980004783A (ko) 디지탈 신호처리장치
TW362180B (en) Method and apparatus for time pulse signal of the synchronized data processing system
KR940017476A (ko) 디지탈 전송시스템의 선로지연 보상회로
NO911215D0 (no) Programmator for aa avgi binaere utgangssignaler i samsvar med et taktsignal.
KR970003104A (ko) 디지탈 비데오 디스크용 동기 패턴 검출 장치
ATE128295T1 (de) Verfahren und einrichtung zur adaptation eines signals, welches zwischen zwei digitalen netzwerken übermittelt wird.
KR960024803A (ko) 동기식 기억 소자의 클럭신호 입력장치
KR970050780A (ko) 칼라벌스트 위상틀어짐 검출장치
JPS5352408A (en) Memory information reproduction system

Legal Events

Date Code Title Description
FC2A Withdrawal, rejection or dismissal of laid open patent application