FI972091A - Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin - Google Patents
Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin Download PDFInfo
- Publication number
- FI972091A FI972091A FI972091A FI972091A FI972091A FI 972091 A FI972091 A FI 972091A FI 972091 A FI972091 A FI 972091A FI 972091 A FI972091 A FI 972091A FI 972091 A FI972091 A FI 972091A
- Authority
- FI
- Finland
- Prior art keywords
- processor
- arrangement
- asic
- signals
- state
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Multi Processors (AREA)
- Exchange Systems With Centralized Control (AREA)
- Small-Scale Networks (AREA)
- Hardware Redundancy (AREA)
- Diaphragms For Electromechanical Transducers (AREA)
- Electrotherapy Devices (AREA)
Priority Applications (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI972091A FI105727B (fi) | 1997-05-15 | 1997-05-15 | Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin |
EP98921512A EP0988603B1 (en) | 1997-05-15 | 1998-05-12 | Method and arrangement for connecting processor to asic |
JP54884098A JP2001526810A (ja) | 1997-05-15 | 1998-05-12 | プロセッサをasicに接続する方法及び構成体 |
US09/423,134 US6654844B1 (en) | 1997-05-15 | 1998-05-12 | Method and arrangement for connecting processor to ASIC |
CN98805140A CN1256769A (zh) | 1997-05-15 | 1998-05-12 | 将处理器连接到asic的方法和装置 |
AU74338/98A AU736765B2 (en) | 1997-05-15 | 1998-05-12 | Method and arrangement for connecting processor to ASIC |
AT98921512T ATE231256T1 (de) | 1997-05-15 | 1998-05-12 | Verfahren und vorrichtung zur verbindung eines prozessors mit einer anwendungsspezifischen integrierten schaltung (asic) |
PCT/FI1998/000402 WO1998052123A2 (en) | 1997-05-15 | 1998-05-12 | Method and arrangement for connecting processor to asic |
DE69810769T DE69810769T2 (de) | 1997-05-15 | 1998-05-12 | Verfahren und vorrichtung zur verbindung eines prozessors mit einer anwendungsspezifischen integrierten schaltung (asic) |
NO995556A NO995556L (no) | 1997-05-15 | 1999-11-12 | Fremgangsmåte og anordning for å forbinde en prosessor med en ASIC |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI972091 | 1997-05-15 | ||
FI972091A FI105727B (fi) | 1997-05-15 | 1997-05-15 | Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin |
Publications (3)
Publication Number | Publication Date |
---|---|
FI972091A0 FI972091A0 (fi) | 1997-05-15 |
FI972091A true FI972091A (fi) | 1998-11-16 |
FI105727B FI105727B (fi) | 2000-09-29 |
Family
ID=8548861
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI972091A FI105727B (fi) | 1997-05-15 | 1997-05-15 | Menetelmä ja järjestely prosessorin liittämiseksi ASIC-piiriin |
Country Status (10)
Country | Link |
---|---|
US (1) | US6654844B1 (fi) |
EP (1) | EP0988603B1 (fi) |
JP (1) | JP2001526810A (fi) |
CN (1) | CN1256769A (fi) |
AT (1) | ATE231256T1 (fi) |
AU (1) | AU736765B2 (fi) |
DE (1) | DE69810769T2 (fi) |
FI (1) | FI105727B (fi) |
NO (1) | NO995556L (fi) |
WO (1) | WO1998052123A2 (fi) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU756039B2 (en) | 1998-06-17 | 2003-01-02 | Nokia Corporation | An interface apparatus for connecting devices operating at different clock rates, and a method of operating the interface |
US6789153B1 (en) * | 2001-02-20 | 2004-09-07 | Lsi Logic Corporation | Bridge for coupling digital signal processor to on-chip bus as slave |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0340901A3 (en) | 1988-03-23 | 1992-12-30 | Du Pont Pixel Systems Limited | Access system for dual port memory |
GB2217064A (en) | 1988-03-23 | 1989-10-18 | Benchmark Technologies | Interfacing asynchronous processors |
US5335338A (en) | 1991-05-31 | 1994-08-02 | Micro Solutions, Inc. | General purpose parallel port interface |
US5255375A (en) * | 1992-01-10 | 1993-10-19 | Digital Equipment Corporation | High performance interface between an asynchronous bus and one or more processors or the like |
US5339395A (en) * | 1992-09-17 | 1994-08-16 | Delco Electronics Corporation | Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode |
US5325491A (en) * | 1993-04-13 | 1994-06-28 | International Business Machines Corporation | Method and apparatus for extending a computer bus |
US5428623A (en) * | 1993-07-01 | 1995-06-27 | Tandem Computers Incorporated | Scannable interface to nonscannable microprocessor |
US5758107A (en) * | 1994-02-14 | 1998-05-26 | Motorola Inc. | System for offloading external bus by coupling peripheral device to data processor through interface logic that emulate the characteristics of the external bus |
US5680594A (en) | 1995-05-24 | 1997-10-21 | Eastman Kodak Company | Asic bus interface having a master state machine and a plurality of synchronizing state machines for controlling subsystems operating at different clock frequencies |
US5987590A (en) * | 1996-04-02 | 1999-11-16 | Texas Instruments Incorporated | PC circuits, systems and methods |
-
1997
- 1997-05-15 FI FI972091A patent/FI105727B/fi active
-
1998
- 1998-05-12 CN CN98805140A patent/CN1256769A/zh active Pending
- 1998-05-12 JP JP54884098A patent/JP2001526810A/ja active Pending
- 1998-05-12 DE DE69810769T patent/DE69810769T2/de not_active Expired - Lifetime
- 1998-05-12 EP EP98921512A patent/EP0988603B1/en not_active Expired - Lifetime
- 1998-05-12 US US09/423,134 patent/US6654844B1/en not_active Expired - Fee Related
- 1998-05-12 WO PCT/FI1998/000402 patent/WO1998052123A2/en active IP Right Grant
- 1998-05-12 AT AT98921512T patent/ATE231256T1/de not_active IP Right Cessation
- 1998-05-12 AU AU74338/98A patent/AU736765B2/en not_active Ceased
-
1999
- 1999-11-12 NO NO995556A patent/NO995556L/no not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
AU736765B2 (en) | 2001-08-02 |
ATE231256T1 (de) | 2003-02-15 |
EP0988603B1 (en) | 2003-01-15 |
NO995556D0 (no) | 1999-11-12 |
DE69810769D1 (de) | 2003-02-20 |
US6654844B1 (en) | 2003-11-25 |
CN1256769A (zh) | 2000-06-14 |
NO995556L (no) | 1999-11-12 |
EP0988603A2 (en) | 2000-03-29 |
FI105727B (fi) | 2000-09-29 |
WO1998052123A3 (en) | 1999-02-04 |
JP2001526810A (ja) | 2001-12-18 |
WO1998052123A2 (en) | 1998-11-19 |
FI972091A0 (fi) | 1997-05-15 |
DE69810769T2 (de) | 2003-09-25 |
AU7433898A (en) | 1998-12-08 |
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