GB2298064A - Transferring data between processors - Google Patents
Transferring data between processorsInfo
- Publication number
- GB2298064A GB2298064A GB9607540A GB9607540A GB2298064A GB 2298064 A GB2298064 A GB 2298064A GB 9607540 A GB9607540 A GB 9607540A GB 9607540 A GB9607540 A GB 9607540A GB 2298064 A GB2298064 A GB 2298064A
- Authority
- GB
- United Kingdom
- Prior art keywords
- processors
- interruption
- time domain
- processor
- memory area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
Abstract
The present invention relates to a method for transferring data between at least two processors (11, 12). In this method, the processors communicate with each other by means of a common memory area such as a register, at least one of the processors writing to said memory area and at least one of the processors reading from said memory area. In order to avoid the transmission of erroneous data between the processors in the simplest possible manner, (a) an interruption signal is applied to the interruption input (INT_IN) of each reading or writing processor (11, 12), the mutual order in time domain of the interruptions produced by all interruption signals being constantly kept the same, and the interval between them being also kept within predetermined limits, and (b) the significant moments of read and write operations (RD/WR) of different processors are determined at predetermined points in time domain with respect to the interruption moments of said interruption signals, a read operation performed by each processor being separate in time domain from the write operations performed by the other processors and a write operation performed by each processor being separate in time domain from the read and write operations performed by the other processors.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI934523A FI94190C (en) | 1993-10-13 | 1993-10-13 | A method and system for transferring information between processors |
PCT/FI1994/000459 WO1995010811A1 (en) | 1993-10-13 | 1994-10-12 | Method and system for transferring data between processors |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9607540D0 GB9607540D0 (en) | 1996-06-26 |
GB2298064A true GB2298064A (en) | 1996-08-21 |
GB2298064B GB2298064B (en) | 1998-01-14 |
Family
ID=8538771
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9607540A Expired - Fee Related GB2298064B (en) | 1993-10-13 | 1994-10-12 | Method and system for transferring data between processors |
Country Status (6)
Country | Link |
---|---|
AU (1) | AU7815094A (en) |
DE (2) | DE4497671B4 (en) |
FI (1) | FI94190C (en) |
GB (1) | GB2298064B (en) |
SE (1) | SE515581C2 (en) |
WO (1) | WO1995010811A1 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4209839A (en) * | 1978-06-16 | 1980-06-24 | International Business Machines Corporation | Shared synchronous memory multiprocessing arrangement |
EP0368655A2 (en) * | 1988-11-09 | 1990-05-16 | Fujitsu Limited | Communication system using a common memory |
DE4129809A1 (en) * | 1991-01-28 | 1992-07-30 | Bosch Gmbh Robert | Master-slave computer system with divided transfer memory - enables any computation to be performed by either processor with all data available equally to both |
-
1993
- 1993-10-13 FI FI934523A patent/FI94190C/en active
-
1994
- 1994-10-12 WO PCT/FI1994/000459 patent/WO1995010811A1/en active Application Filing
- 1994-10-12 DE DE4497671A patent/DE4497671B4/en not_active Expired - Fee Related
- 1994-10-12 DE DE4497671T patent/DE4497671T1/en active Pending
- 1994-10-12 GB GB9607540A patent/GB2298064B/en not_active Expired - Fee Related
- 1994-10-12 AU AU78150/94A patent/AU7815094A/en not_active Abandoned
-
1996
- 1996-04-10 SE SE9601346A patent/SE515581C2/en not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4209839A (en) * | 1978-06-16 | 1980-06-24 | International Business Machines Corporation | Shared synchronous memory multiprocessing arrangement |
EP0368655A2 (en) * | 1988-11-09 | 1990-05-16 | Fujitsu Limited | Communication system using a common memory |
DE4129809A1 (en) * | 1991-01-28 | 1992-07-30 | Bosch Gmbh Robert | Master-slave computer system with divided transfer memory - enables any computation to be performed by either processor with all data available equally to both |
Also Published As
Publication number | Publication date |
---|---|
GB2298064B (en) | 1998-01-14 |
AU7815094A (en) | 1995-05-04 |
FI934523A0 (en) | 1993-10-13 |
DE4497671T1 (en) | 1996-11-21 |
WO1995010811A1 (en) | 1995-04-20 |
SE9601346L (en) | 1996-04-10 |
DE4497671B4 (en) | 2004-02-05 |
FI94190C (en) | 1995-07-25 |
FI94190B (en) | 1995-04-13 |
GB9607540D0 (en) | 1996-06-26 |
SE515581C2 (en) | 2001-09-03 |
SE9601346D0 (en) | 1996-04-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20081012 |