FI94190C - A method and system for transferring information between processors - Google Patents

Description

94190

The invention relates to a method for transferring data between at least two processors according to the preamble of appended claim 1. The invention also relates to a multiprocessor system according to the preamble of appended claim 4, wherein at least two processors communicate with each other via a common memory area. (Processor in this context generally refers to any device that operates under an external or internal program.)

In multiprocessor systems such as those described above, in which the processors communicate with each other via a common memory area, such as a parallel register, the state of them is such that at least one of the processors writes to that memory area and at least one processor reads from said memory area. Writing and reading usually take place via different data buses, keeping the load on the data bus 20 of each processor to a minimum.

It is often justified that at least some of the processors have different clock signals that are not synchronized with each other. In this case, their significant moments slide in time with respect to each other.

25 If the times of the read and write events of the processors are in no way synchronized with each other, sooner or later simultaneous reading and writing to the same register or memory location will take place. In this case, it depends on the phase of the clock signals whether the value in the register • · 30 or the memory location was before or after writing. There may not be any mistake here. In the extreme case, however, it is possible that some of the parallel bits in the register or memory location may have changed before the chapter, but 35 parts are still in accordance with the old content. In this case, the number gives 94190 2 incorrect information about the contents of the register. Although such a phenomenon is rare and may, depending on the clock frequencies and the frequencies of read and write events, occur only once in a hundred years, it will in any case sooner or later, unless the read and write events are in any way synchronized.

The effect of an erroneous reading event depends essentially on the case. Communication between processors can be ensured so that one erroneous number does not cause a malfunction in the device. However, this requires a more complex communication protocol used by the processors, which in turn slows down the operation of the device (the digital device in which the processors are used).

15 The above error situation can be avoided by synchronizing the operation of the processors in such a way that simultaneous reading and writing are prevented. There are several possibilities for this.

In some cases, synchronization can be done with a hardware solution. In general, such a solution increases the complexity of the implementation and thus brings additional costs. It is also often the case that different processors provide the control signals used for reading and writing themselves, in which case it may be impossible to synchronize them with the hardware solution or involve its own risk of malfunction.

The object of the present invention is to overcome the drawbacks described above and to provide a solution by means of which the transmission of erroneous information can be avoided in the simplest possible way.

This object is achieved by a method and a system according to the invention, which method is characterized by what is described in the characterizing part of the appended claim 1. The features of the system according to the invention are in turn apparent from the features of the appended claim 4.

The idea of the invention is to use one or more interrupt signals for the mutual scheduling of write and read events, wherein (a) in the case of one common interrupt signal, the program of each processor handles read and write events performed by different processors with respect to the common interrupt moment, thus , there is no simultaneous read and write, or (b) in the case of several interrupt signals, the the mutual chronological order of the signals is kept constantly the same and their mutual Interval is additionally within predetermined limits, whereby a read and / or write operation of at least one, but preferably all, processors can be performed immediately. after the corresponding pause time of the processor. Since a simultaneous reading operation performed by several processors, depending on the device structure, does not necessarily cause a malfunction, it can be allowed under certain conditions.

In many cases, the system according to the invention can be implemented completely without additional equipment, in which case its application does not cause the need for additional components. In the following, the invention and its preferred embodiments and advantages will be described in more detail with reference to the accompanying drawings, in which Fig. 1 shows a multiprocessor system according to a first embodiment of the invention, Fig. 2 shows the timing of read and write events in a multiprocessor system shown, which in this case operates according to a second embodiment of the invention, and ... Fig. 4 shows the timing of read and write events in the system shown in Fig. 3.

Figures 1 and 2 show by way of example a solution according to the invention applied to the exchange of messages between a master controller (e.g. 35 MC68302) belonging to the applicant's DYNACARD® product family and a digital signal processor (e.g. DSP16) 4 94190.

The main controller 11 and the DSP circuit 12 communicate with each other via the parallel interface 13 of the DSP circuit. The parallel interface of the DSP circuit has two internal registers.

5 The internal computing unit of the DSP circuit writes to one of these registers and reads the contents of one of them. The parallel bus PB of the main controller 11 is connected to the parallel interface 13 of the DSP circuit. The master controller writes to the register from which the internal computing unit 10 of the DSP circuit reads, and the main controller reads from the register to which the internal computing unit of the DSP circuit writes.

Both the master controller and the DSP circuit operate in step with their own clock signal (CLK1 and CLK2, respectively). Clock signals are not synchronized. The interrupt input INT_IN of both controllers 15 is supplied with the same interrupt signal INTR (in this example) causing an interrupt every 125 microseconds (Fig. 2). The master controller 11 is programmed to operate and write to and read from the parallel registers of the DSP circuit for a short time, e.g., less than 50 microseconds, within an interrupt, i.e., well before the next interrupt occurs. The DSP circuit, in turn, is programmed to operate in such a way that, after receiving an interruption, it performs various calculation and other operations for such a long time that the time in question of 125 microseconds elapses almost. In practice, this could mean, for example, that at least 100 microseconds have elapsed since the time of 125 microseconds. The DSP circuit then reads one of its parallel registers and writes to the other. Fig. 2 illustrates the timing of the read and write operations performed by the master controller 11 with respect to the common interrupt signal on the time axis ha-30 denoted by RD / WR / 11 and the read and write operations performed by the DSP circuit 12 on the time axis denoted by RD / WR / 12, respectively. the timing of the write operations to the interrupt signal. The read and write events themselves are marked with the reference 5 94190 RD / WR. In practice, the time duration of a read and write event is of the order of 1 microsecond.

As described above, it is ensured that simultaneous writing and reading cannot occur in the communication between the master controller 5 and the DSP circuit. Using the above-mentioned example values, there is a time interval of at least 50 microseconds between the read and write operations performed by the master controller and the DSP circuit, which is almost half the time between two interrupts.

10 Alternatively, separate interrupt signals may be used so that the relative chronological order of all interrupts caused by the interrupt signals is kept constant and their mutual Interval within predetermined limits selected taking into account the operating speeds of the processors. Figures 3 and 4 show such an alternative to the multiprocessor system of Figure 1. The embodiment of Figures 3 and 4 thus otherwise corresponds to the embodiment of Figures 1 and 2, but now each processor is provided with its own interrupt signal; an interrupt signal INTR1 to the master controller 11 and an interrupt signal INTR2 to the DSP circuit 12. In this case, the interrupt signal INTR1 causes the master controller to perform read and write operations, and the interrupt signal INTR2 the DSP circuit to perform its own read and write operations, respectively.

The first embodiment presented above is more difficult to implement in that it has to ensure by means of a program that the DSP circuit performs calculation and other operations for a sufficiently long time after the interruption, while in the latter alternative its own interrupt signal INTR2 ensures that the DSP circuit cannot perform reading and writing too early (allowed only after the moment of interruption), and reading and writing operations can be performed immediately after the interruption (there is no need to programmatically ensure that the desired time has elapsed). On the other hand, the first embodiment presented above is more advantageous in that it does not have to worry about the mutual timing of the different interrupt signals.

However, it depends on the particular application used whether it is advisable to use one or more interrupt signals. If the system has more than two processors, the options described above can also be used in combination so that some of the processors have a common interrupt signal and some have their own interrupt signals, synchronized with each other and with the common interrupt signal as described above.

Although the invention has been described above with reference to the examples according to the accompanying drawings, it is clear that the invention is not limited thereto, but can be modified within the scope of the inventive idea set forth above and in the appended claims. For example, when using a common interrupt signal, the the signal is connected via delay branches of different lengths to the interrupt inputs of different processors, whereby the situation corresponds in principle to the use of 20 separate interrupt signals.

Claims (5)

A method of transferring data between at least two processors (11, 12), according to which the processors communicate with each other by means of a common memory area, such as a register, such that at least one of the processors inscribes in said memory area and at least one of the processors reads from said memory area, characterized in that an interrupt signal is inserted into the interrupt input (INT_IN) in each read or write processor (11, 12), so that the inter-order between all interrupt interrupt signals causes identical continuous interruptions. moreover, the interval between them within predetermined limits, and the significant moments in the read and write events (RD / WR) of the various processors are determined at time intervals relative to the interrupting moment of the interrupt signals, so that each reading performed by one processor is performed. schedule different from the other processors' write permission rder and each formed of a processor write operation is in timing different from the other processor's read and skrivätgärder. 2. A method according to claim 1, characterized in that the same interrupt signal (INTR) is applied to the interrupt input (INT_IN) of each reading or writing processor (11, 12) and the significant moment of the processor read or write event is determined. in relation to a common interruption moment by means of the processor's program. . Method according to claim 1, characterized in that a separate interrupt signal (INTR1; INTR2) is applied to each reading or writing process sequence (11, 12) and at least one processor, preferably all of the processors, read and write operation is executed immediately after a said processor corresponding to interrupt moments. Multiprocessor systems, comprising at least two processors (11, 12), which communicate with each other by means of a common memory area, such as a register, such that at least one of the processors inscribes into said memory area and at least one of the processors reads from said memory area, each processor being provided with its own interrupt input (INT_IN), characterized by a interrupt signal being coupled to the interrupt input (INT_IN) in each reading or writing processor (11, 12), the interdependence between all interrupts the interrupt signals causes the pours to be continuously identical and additionally the interval between them within predetermined limits, and that each processor is arranged to execute a read or write operation at a time of its own interrupt, in a timely determined place, a reading operation performed by a processor is separated from the other processor's writing operations in a schedule and a 20 A write operation performed by a processor is in schedule different from the read and write operations of the other processors. System according to claim 1, characterized in that the same interrupt signal (INT) is coupled to the interrupt input (INT_IN) in each read or write processor (11, 12), and the significant moment of the processor read or writing event is arranged in the story to a common interrupt moment with the aid of the processor program.