SE9601346L - Process and system for transferring data between processors - Google Patents

Process and system for transferring data between processors

Info

Publication number
SE9601346L
SE9601346L SE9601346A SE9601346A SE9601346L SE 9601346 L SE9601346 L SE 9601346L SE 9601346 A SE9601346 A SE 9601346A SE 9601346 A SE9601346 A SE 9601346A SE 9601346 L SE9601346 L SE 9601346L
Authority
SE
Sweden
Prior art keywords
processors
interruption
time domain
processor
memory area
Prior art date
Application number
SE9601346A
Other languages
Unknown language ( )
Swedish (sv)
Other versions
SE515581C2 (en
SE9601346D0 (en
Inventor
Esko Rautanen
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Publication of SE9601346L publication Critical patent/SE9601346L/en
Publication of SE9601346D0 publication Critical patent/SE9601346D0/en
Publication of SE515581C2 publication Critical patent/SE515581C2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Abstract

The present invention relates to a method for transferring data between at least two processors (11, 12). In this method, the processors communicate with each other by means of a common memory area such as a register, at least one of the processors writing to said memory area and at least one of the processors reading from said memory area. In order to avoid the transmission of erroneous data between the processors in the simplest possible manner, (a) an interruption signal is applied to the interruption input (INT_IN) of each reading or writing processor (11, 12), the mutual order in time domain of the interruptions produced by all interruption signals being constantly kept the same, and the interval between them being also kept within predetermined limits, and (b) the significant moments of read and write operations (RD/WR) of different processors are determined at predetermined points in time domain with respect to the interruption moments of said interruption signals, a read operation performed by each processor being separate in time domain from the write operations performed by the other processors and a write operation performed by each processor being separate in time domain from the read and write operations performed by the other processors.
SE9601346A 1993-10-13 1996-04-10 Process and system for transferring data between processors SE515581C2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI934523A FI94190C (en) 1993-10-13 1993-10-13 A method and system for transferring information between processors
PCT/FI1994/000459 WO1995010811A1 (en) 1993-10-13 1994-10-12 Method and system for transferring data between processors

Publications (3)

Publication Number Publication Date
SE9601346L true SE9601346L (en) 1996-04-10
SE9601346D0 SE9601346D0 (en) 1996-04-10
SE515581C2 SE515581C2 (en) 2001-09-03

Family

ID=8538771

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9601346A SE515581C2 (en) 1993-10-13 1996-04-10 Process and system for transferring data between processors

Country Status (6)

Country Link
AU (1) AU7815094A (en)
DE (2) DE4497671T1 (en)
FI (1) FI94190C (en)
GB (1) GB2298064B (en)
SE (1) SE515581C2 (en)
WO (1) WO1995010811A1 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4209839A (en) * 1978-06-16 1980-06-24 International Business Machines Corporation Shared synchronous memory multiprocessing arrangement
JPH02128267A (en) * 1988-11-09 1990-05-16 Fujitsu Ltd Communication system by sharing memory
DE4129809C2 (en) * 1991-01-28 2000-08-17 Bosch Gmbh Robert Multi-computer system

Also Published As

Publication number Publication date
DE4497671B4 (en) 2004-02-05
FI934523A0 (en) 1993-10-13
GB9607540D0 (en) 1996-06-26
SE515581C2 (en) 2001-09-03
GB2298064A (en) 1996-08-21
WO1995010811A1 (en) 1995-04-20
SE9601346D0 (en) 1996-04-10
FI94190B (en) 1995-04-13
DE4497671T1 (en) 1996-11-21
FI94190C (en) 1995-07-25
GB2298064B (en) 1998-01-14
AU7815094A (en) 1995-05-04

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Legal Events

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