JPS55146550A - High speed branch controlling system - Google Patents

High speed branch controlling system

Info

Publication number
JPS55146550A
JPS55146550A JP5152079A JP5152079A JPS55146550A JP S55146550 A JPS55146550 A JP S55146550A JP 5152079 A JP5152079 A JP 5152079A JP 5152079 A JP5152079 A JP 5152079A JP S55146550 A JPS55146550 A JP S55146550A
Authority
JP
Japan
Prior art keywords
instruction
branch
register
array
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5152079A
Other languages
Japanese (ja)
Inventor
Katsuro Wakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5152079A priority Critical patent/JPS55146550A/en
Publication of JPS55146550A publication Critical patent/JPS55146550A/en
Pending legal-status Critical Current

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  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To make it possible not to perform an unnecessary instruction reading, by checking up the contents of a field R1 swiftly and deciding whether the branch is successful or not, when an advance control of a conditional branch instruction (BCT instruction) is started.
CONSTITUTION: In a register array 16 having a bit corresponding to each register No. of a register array 15 which forms a general register group is written through a "1" detection circuit 14 the check result showing whether branch of a data written in the afore-said array 15 is allowed or not. When a BCT instruction is detected by a field OP of an instruction of an instruction register 1, an address of a branch destination is operated by a data of the register array 15 which has been read out by the value of fields X2 and B2, and the value of a field D2. Moreover, the array 16 is read out by a field R1, and it is input to AND gates 19, 20. As a result of the foregoing, a branch unsuccessful signal 24 or a branch sucessful signal 25 is output.
COPYRIGHT: (C)1980,JPO&Japio
JP5152079A 1979-04-27 1979-04-27 High speed branch controlling system Pending JPS55146550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5152079A JPS55146550A (en) 1979-04-27 1979-04-27 High speed branch controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5152079A JPS55146550A (en) 1979-04-27 1979-04-27 High speed branch controlling system

Publications (1)

Publication Number Publication Date
JPS55146550A true JPS55146550A (en) 1980-11-14

Family

ID=12889279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5152079A Pending JPS55146550A (en) 1979-04-27 1979-04-27 High speed branch controlling system

Country Status (1)

Country Link
JP (1) JPS55146550A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6341932A (en) * 1985-08-22 1988-02-23 Nec Corp Branching instruction processing device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS522140A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Information processing apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS522140A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Information processing apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6341932A (en) * 1985-08-22 1988-02-23 Nec Corp Branching instruction processing device

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