GB1478513A - Memory system - Google Patents

Abstract

1478513 Data transfer PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 1 July 1974 29028/74 Heading G4A A memory system includes first and second memories MEM3, MEM4 (Fig. 1) each having addressable word locations comprising a plurality of byte locations, the memories being interconnected by a word width data path, the first memory being simultaneously addressable at two consecutive word locations, control signals indicating the position of the first byte location and the number of bytes to be tranferred being fed to a rotator in the data path so that a word for transfer is correctly aligned. As described a control unit CONTR supplies on leads 208 an operand address in memory MEM3. The two least significant bits represent the byte location of the most significant byte, these being fed on line 210, 211 to shift control SC1, rotation control RC and selector SEL2. The word address and this address incremented by 1 are fed on lines 204, 205 respectively to drivers DR6. The control unit also supplies (1) signals representing the number of bytes on lines 209 to shift control SC1 and selector SEL2 to control the address of the memory 3, (2) a read/write signal on line 206 and (3) an address for memory MEM4 on lines 201. Rotators SROT and LROT via which data is transferred to and from memory MEM3 are controlled by signals from rotator control RC and comprise a plurality of AND gates (Fig. 2, not shown) receiving control signals on one set of inputs and rotation information on a second set.