NO964401L - Fremgangsmåte og anordning ved styring av et lager - Google Patents

Fremgangsmåte og anordning ved styring av et lager

Info

Publication number
NO964401L
NO964401L NO964401A NO964401A NO964401L NO 964401 L NO964401 L NO 964401L NO 964401 A NO964401 A NO 964401A NO 964401 A NO964401 A NO 964401A NO 964401 L NO964401 L NO 964401L
Authority
NO
Norway
Prior art keywords
bit positions
control
digital information
memory
warehouse
Prior art date
Application number
NO964401A
Other languages
English (en)
Other versions
NO964401D0 (no
Inventor
Eva Charlotte Alvenkrona
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of NO964401D0 publication Critical patent/NO964401D0/no
Publication of NO964401L publication Critical patent/NO964401L/no

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Electrotherapy Devices (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Debugging And Monitoring (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Sliding-Contact Bearings (AREA)
  • Warehouses Or Storage Devices (AREA)
  • Selective Calling Equipment (AREA)
  • Communication Control (AREA)

Abstract

En fremgangsmåte og en kretsanordning for å styre innsetting og lagring av digital informasjon (A) i et lager (51) og uthenting av informasjonen fra lageret. Fremgangsmåten og kretsanordningen sikrer at den digitale informasjon (A') blir korrekt lest ut av lageret i form av et antall koordinerte bit-posisjoner, og den digitale informasjon blir brukt til å styre en eller flere funksjoner (f). Informasjonen som skal settes inn i lageret, gis en adresse som tilhører lageret. Første kontrollsumbærende bit-posisjoner blir beregnet (53a) fra bit-posisjonene til den digitale informasjon og deres verdier som kommer inn i lageret i henhold til en valgt evaluer-. , ingsfunksjon (f(x)). Bit-posisjonene til den digitale informasjon () blir lagret i en adresse i lageret (51), og de første kontrollsumbærende bit-posisjoner er lagret i en adresse i et styrelager (55). Andre kontrollsumbærende bit-posisjoner blir beregnet når bit-posisjonene til den digitale informasjonen lagret i adressen i lageret (51) leses ut i henhold til den valgte evalueringsfunksjon (62). Bit-posisjonene til den leste informasjon, og deres verdier, aksepteres som korrekte, og en krets (60). i. aktiveres gjennom et signal på en leder (57), hvis en etterfølgende sammenligning (63) mellom de første og de andre kontrollsumbærende bit-posisjoner viser at de er identiske.
NO964401A 1994-04-19 1996-10-16 Fremgangsmåte og anordning ved styring av et lager NO964401L (no)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9401318A SE503316C2 (sv) 1994-04-19 1994-04-19 Förfarande för övervakning av ett minne samt kretsanordning härför
PCT/SE1995/000420 WO1995028674A2 (en) 1994-04-19 1995-04-18 Method and device to control a memory

Publications (2)

Publication Number Publication Date
NO964401D0 NO964401D0 (no) 1996-10-16
NO964401L true NO964401L (no) 1996-12-13

Family

ID=20393700

Family Applications (1)

Application Number Title Priority Date Filing Date
NO964401A NO964401L (no) 1994-04-19 1996-10-16 Fremgangsmåte og anordning ved styring av et lager

Country Status (14)

Country Link
US (1) US5577055A (no)
EP (1) EP0756727B1 (no)
JP (1) JP2989669B2 (no)
KR (1) KR100301098B1 (no)
CN (1) CN1146248A (no)
AT (1) ATE212455T1 (no)
AU (1) AU682767B2 (no)
BR (1) BR9507465A (no)
CA (1) CA2186977C (no)
DE (1) DE69525154T2 (no)
FI (1) FI964196A7 (no)
NO (1) NO964401L (no)
SE (1) SE503316C2 (no)
WO (1) WO1995028674A2 (no)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19650993A1 (de) * 1996-11-26 1998-05-28 Francotyp Postalia Gmbh Anordnung und Verfahren zur Verbesserung der Datensicherheit mittels Ringpuffer
US6904552B2 (en) * 2001-03-15 2005-06-07 Micron Technolgy, Inc. Circuit and method for test and repair
US20020133769A1 (en) * 2001-03-15 2002-09-19 Cowles Timothy B. Circuit and method for test and repair
JP2002288041A (ja) * 2001-03-23 2002-10-04 Sony Corp 情報処理装置および方法、プログラム格納媒体、並びにプログラム
CN100338600C (zh) * 2003-01-03 2007-09-19 宇东科技股份有限公司 读取传感器的方法
US8583971B2 (en) * 2010-12-23 2013-11-12 Advanced Micro Devices, Inc. Error detection in FIFO queues using signature bits
US9311975B1 (en) * 2014-10-07 2016-04-12 Stmicroelectronics S.R.L. Bi-synchronous electronic device and FIFO memory circuit with jump candidates and related methods
JP2016167210A (ja) * 2015-03-10 2016-09-15 株式会社東芝 メモリコントローラ、データストレージデバイス、及び、データ書き込み方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4019033A (en) * 1975-12-29 1977-04-19 Honeywell Information Systems, Inc. Control store checking system and method
US4271521A (en) * 1979-07-09 1981-06-02 The Anaconda Company Address parity check system
IL67664A (en) * 1982-01-19 1987-01-30 Tandem Computers Inc Computer memory system with data,address and operation error detection
US4692893A (en) * 1984-12-24 1987-09-08 International Business Machines Corp. Buffer system using parity checking of address counter bit for detection of read/write failures
US4809278A (en) * 1986-04-21 1989-02-28 Unisys Corporation Specialized parity detection system for wide memory structure
US5047927A (en) * 1988-10-28 1991-09-10 National Semiconductor Corporation Memory management in packet data mode systems
DE69019822T2 (de) * 1990-06-27 1995-12-14 Ibm Verfahren und Vorrichtung zur Prüfung des Inhalts und der Adresse einer Speicheranordnung.
DE4104198A1 (de) * 1991-02-12 1992-08-13 Basf Ag Verfahren zur herstellung von formteilen mit guten oberflaecheneigenschaften
DE69129851T2 (de) * 1991-09-13 1999-03-25 International Business Machines Corp., Armonk, N.Y. Konfigurierbare gigabit/s Vermittlunganpassungseinrichtung
EP0544964B1 (en) * 1991-11-29 1997-02-19 International Business Machines Corporation Store and forward apparatus and method of maintaining integrity of data during storage
US5426639A (en) * 1991-11-29 1995-06-20 At&T Corp. Multiple virtual FIFO arrangement
US5477553A (en) * 1994-07-22 1995-12-19 Professional Computer Systems, Inc. Compressed memory address parity checking apparatus and method

Also Published As

Publication number Publication date
BR9507465A (pt) 1997-09-16
ATE212455T1 (de) 2002-02-15
US5577055A (en) 1996-11-19
NO964401D0 (no) 1996-10-16
WO1995028674A3 (en) 1995-11-30
CA2186977A1 (en) 1995-10-26
EP0756727A1 (en) 1997-02-05
AU2378495A (en) 1995-11-10
CN1146248A (zh) 1997-03-26
WO1995028674A2 (en) 1995-10-26
CA2186977C (en) 2000-10-03
FI964196A0 (fi) 1996-10-18
SE9401318L (sv) 1995-10-20
DE69525154T2 (de) 2002-09-05
FI964196A7 (fi) 1996-10-18
AU682767B2 (en) 1997-10-16
DE69525154D1 (de) 2002-03-14
JPH09505680A (ja) 1997-06-03
EP0756727B1 (en) 2002-01-23
KR970702525A (ko) 1997-05-13
KR100301098B1 (ko) 2001-10-26
SE503316C2 (sv) 1996-05-13
JP2989669B2 (ja) 1999-12-13
SE9401318D0 (sv) 1994-04-19

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