SE9401318L - Förfarande för övervakning av ett minne samt kretsanordning härför - Google Patents

Förfarande för övervakning av ett minne samt kretsanordning härför

Info

Publication number
SE9401318L
SE9401318L SE9401318A SE9401318A SE9401318L SE 9401318 L SE9401318 L SE 9401318L SE 9401318 A SE9401318 A SE 9401318A SE 9401318 A SE9401318 A SE 9401318A SE 9401318 L SE9401318 L SE 9401318L
Authority
SE
Sweden
Prior art keywords
memory
bit positions
control
digital information
sum
Prior art date
Application number
SE9401318A
Other languages
English (en)
Other versions
SE9401318D0 (sv
SE503316C2 (sv
Inventor
Eva Charlotte Westerlund
Original Assignee
Ellemtel Utvecklings Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ellemtel Utvecklings Ab filed Critical Ellemtel Utvecklings Ab
Priority to SE9401318A priority Critical patent/SE503316C2/sv
Publication of SE9401318D0 publication Critical patent/SE9401318D0/sv
Priority to CN95192669A priority patent/CN1146248A/zh
Priority to KR1019960705871A priority patent/KR100301098B1/ko
Priority to US08/421,972 priority patent/US5577055A/en
Priority to EP95916905A priority patent/EP0756727B1/en
Priority to AU23784/95A priority patent/AU682767B2/en
Priority to DE69525154T priority patent/DE69525154T2/de
Priority to BR9507465A priority patent/BR9507465A/pt
Priority to AT95916905T priority patent/ATE212455T1/de
Priority to CA002186977A priority patent/CA2186977C/en
Priority to JP7526910A priority patent/JP2989669B2/ja
Priority to PCT/SE1995/000420 priority patent/WO1995028674A2/en
Publication of SE9401318L publication Critical patent/SE9401318L/sv
Publication of SE503316C2 publication Critical patent/SE503316C2/sv
Priority to NO964401A priority patent/NO964401L/no
Priority to FI964196A priority patent/FI964196A0/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Electrotherapy Devices (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Debugging And Monitoring (AREA)
  • Selective Calling Equipment (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Sliding-Contact Bearings (AREA)
  • Communication Control (AREA)
  • Warehouses Or Storage Devices (AREA)
SE9401318A 1994-04-19 1994-04-19 Förfarande för övervakning av ett minne samt kretsanordning härför SE503316C2 (sv)

Priority Applications (14)

Application Number Priority Date Filing Date Title
SE9401318A SE503316C2 (sv) 1994-04-19 1994-04-19 Förfarande för övervakning av ett minne samt kretsanordning härför
CN95192669A CN1146248A (zh) 1994-04-19 1995-03-18 控制存储器的方法和装置
KR1019960705871A KR100301098B1 (ko) 1994-04-19 1995-03-18 메모리제어방법및장치
US08/421,972 US5577055A (en) 1994-04-19 1995-04-14 Method and circuit device to control a memory
PCT/SE1995/000420 WO1995028674A2 (en) 1994-04-19 1995-04-18 Method and device to control a memory
DE69525154T DE69525154T2 (de) 1994-04-19 1995-04-18 Speichersteuerungsverfahren und vorrichtung
AU23784/95A AU682767B2 (en) 1994-04-19 1995-04-18 Method and device to control a memory
EP95916905A EP0756727B1 (en) 1994-04-19 1995-04-18 Method and device to control a memory
BR9507465A BR9507465A (pt) 1994-04-19 1995-04-18 Processo e dispositivo de circuito para controlar que uma informação digital que é inserida em e armazenada dentro de uma memória principal seja corretamente lida-emitida
AT95916905T ATE212455T1 (de) 1994-04-19 1995-04-18 Speichersteuerungsverfahren und vorrichtung
CA002186977A CA2186977C (en) 1994-04-19 1995-04-18 Method and device to control a memory
JP7526910A JP2989669B2 (ja) 1994-04-19 1995-04-18 メモリを制御する方法およびデバイス
NO964401A NO964401L (no) 1994-04-19 1996-10-16 Fremgangsmåte og anordning ved styring av et lager
FI964196A FI964196A0 (sv) 1994-04-19 1996-10-18 Förfarande och anordning för styrning av ett minne

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9401318A SE503316C2 (sv) 1994-04-19 1994-04-19 Förfarande för övervakning av ett minne samt kretsanordning härför

Publications (3)

Publication Number Publication Date
SE9401318D0 SE9401318D0 (sv) 1994-04-19
SE9401318L true SE9401318L (sv) 1995-10-20
SE503316C2 SE503316C2 (sv) 1996-05-13

Family

ID=20393700

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9401318A SE503316C2 (sv) 1994-04-19 1994-04-19 Förfarande för övervakning av ett minne samt kretsanordning härför

Country Status (14)

Country Link
US (1) US5577055A (sv)
EP (1) EP0756727B1 (sv)
JP (1) JP2989669B2 (sv)
KR (1) KR100301098B1 (sv)
CN (1) CN1146248A (sv)
AT (1) ATE212455T1 (sv)
AU (1) AU682767B2 (sv)
BR (1) BR9507465A (sv)
CA (1) CA2186977C (sv)
DE (1) DE69525154T2 (sv)
FI (1) FI964196A0 (sv)
NO (1) NO964401L (sv)
SE (1) SE503316C2 (sv)
WO (1) WO1995028674A2 (sv)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19650993A1 (de) * 1996-11-26 1998-05-28 Francotyp Postalia Gmbh Anordnung und Verfahren zur Verbesserung der Datensicherheit mittels Ringpuffer
US20020133769A1 (en) * 2001-03-15 2002-09-19 Cowles Timothy B. Circuit and method for test and repair
US6904552B2 (en) * 2001-03-15 2005-06-07 Micron Technolgy, Inc. Circuit and method for test and repair
JP2002288041A (ja) * 2001-03-23 2002-10-04 Sony Corp 情報処理装置および方法、プログラム格納媒体、並びにプログラム
CN100338600C (zh) * 2003-01-03 2007-09-19 宇东科技股份有限公司 读取传感器的方法
US8583971B2 (en) * 2010-12-23 2013-11-12 Advanced Micro Devices, Inc. Error detection in FIFO queues using signature bits
US9311975B1 (en) * 2014-10-07 2016-04-12 Stmicroelectronics S.R.L. Bi-synchronous electronic device and FIFO memory circuit with jump candidates and related methods
JP2016167210A (ja) * 2015-03-10 2016-09-15 株式会社東芝 メモリコントローラ、データストレージデバイス、及び、データ書き込み方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4019033A (en) * 1975-12-29 1977-04-19 Honeywell Information Systems, Inc. Control store checking system and method
US4271521A (en) * 1979-07-09 1981-06-02 The Anaconda Company Address parity check system
IL67664A (en) * 1982-01-19 1987-01-30 Tandem Computers Inc Computer memory system with data,address and operation error detection
US4692893A (en) * 1984-12-24 1987-09-08 International Business Machines Corp. Buffer system using parity checking of address counter bit for detection of read/write failures
US4809278A (en) * 1986-04-21 1989-02-28 Unisys Corporation Specialized parity detection system for wide memory structure
US5047927A (en) * 1988-10-28 1991-09-10 National Semiconductor Corporation Memory management in packet data mode systems
EP0463210B1 (en) * 1990-06-27 1995-05-31 International Business Machines Corporation Method and apparatus for checking the address and contents of a memory array
DE4104198A1 (de) * 1991-02-12 1992-08-13 Basf Ag Verfahren zur herstellung von formteilen mit guten oberflaecheneigenschaften
DE69129851T2 (de) * 1991-09-13 1999-03-25 International Business Machines Corp., Armonk, N.Y. Konfigurierbare gigabit/s Vermittlunganpassungseinrichtung
US5426639A (en) * 1991-11-29 1995-06-20 At&T Corp. Multiple virtual FIFO arrangement
DE69124743T2 (de) * 1991-11-29 1997-08-14 Ibm Vorrichtung zur Speicherung und Durchschaltung und Verfahren zur Datensicherung während der Speicherung
US5477553A (en) * 1994-07-22 1995-12-19 Professional Computer Systems, Inc. Compressed memory address parity checking apparatus and method

Also Published As

Publication number Publication date
EP0756727A1 (en) 1997-02-05
DE69525154D1 (de) 2002-03-14
CN1146248A (zh) 1997-03-26
WO1995028674A2 (en) 1995-10-26
SE9401318D0 (sv) 1994-04-19
AU682767B2 (en) 1997-10-16
US5577055A (en) 1996-11-19
EP0756727B1 (en) 2002-01-23
CA2186977A1 (en) 1995-10-26
BR9507465A (pt) 1997-09-16
CA2186977C (en) 2000-10-03
AU2378495A (en) 1995-11-10
JP2989669B2 (ja) 1999-12-13
NO964401D0 (no) 1996-10-16
DE69525154T2 (de) 2002-09-05
WO1995028674A3 (en) 1995-11-30
JPH09505680A (ja) 1997-06-03
ATE212455T1 (de) 2002-02-15
KR970702525A (ko) 1997-05-13
FI964196A (sv) 1996-10-18
KR100301098B1 (ko) 2001-10-26
SE503316C2 (sv) 1996-05-13
FI964196A0 (sv) 1996-10-18
NO964401L (no) 1996-12-13

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Legal Events

Date Code Title Description
NUG Patent has lapsed