NL8701717A - Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een geplanariseerde opbouw. - Google Patents
Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een geplanariseerde opbouw. Download PDFInfo
- Publication number
- NL8701717A NL8701717A NL8701717A NL8701717A NL8701717A NL 8701717 A NL8701717 A NL 8701717A NL 8701717 A NL8701717 A NL 8701717A NL 8701717 A NL8701717 A NL 8701717A NL 8701717 A NL8701717 A NL 8701717A
- Authority
- NL
- Netherlands
- Prior art keywords
- layer
- planarized
- floors
- filling
- etching
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000000034 method Methods 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000463 material Substances 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 25
- 239000000945 filler Substances 0.000 claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 239000011261 inert gas Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 125
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 229910052814 silicon oxide Inorganic materials 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 150000002148 esters Chemical class 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL8701717A NL8701717A (nl) | 1987-07-21 | 1987-07-21 | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een geplanariseerde opbouw. |
EP88201515A EP0300569B1 (fr) | 1987-07-21 | 1988-07-14 | Procédé de fabrication d'un dispositif semiconducteur planarisé |
DE3852583T DE3852583T2 (de) | 1987-07-21 | 1988-07-14 | Verfahren zum Herstellen einer Halbleiteranordnung mit einem planarisierten Aufbau. |
JP63177255A JPS6437840A (en) | 1987-07-21 | 1988-07-18 | Manufacture of semiconductor device with planar structure |
KR1019880009112A KR890003005A (ko) | 1987-07-21 | 1988-07-21 | 반도체장치 제조방법 |
US07/522,490 US5015602A (en) | 1987-07-21 | 1990-05-10 | Method of manufacturing a semiconductor device having a planarized construction |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL8701717A NL8701717A (nl) | 1987-07-21 | 1987-07-21 | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een geplanariseerde opbouw. |
NL8701717 | 1987-07-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
NL8701717A true NL8701717A (nl) | 1989-02-16 |
Family
ID=19850350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NL8701717A NL8701717A (nl) | 1987-07-21 | 1987-07-21 | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een geplanariseerde opbouw. |
Country Status (6)
Country | Link |
---|---|
US (1) | US5015602A (fr) |
EP (1) | EP0300569B1 (fr) |
JP (1) | JPS6437840A (fr) |
KR (1) | KR890003005A (fr) |
DE (1) | DE3852583T2 (fr) |
NL (1) | NL8701717A (fr) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4836885A (en) * | 1988-05-03 | 1989-06-06 | International Business Machines Corporation | Planarization process for wide trench isolation |
US4954459A (en) * | 1988-05-12 | 1990-09-04 | Advanced Micro Devices, Inc. | Method of planarization of topologies in integrated circuit structures |
US4962064A (en) * | 1988-05-12 | 1990-10-09 | Advanced Micro Devices, Inc. | Method of planarization of topologies in integrated circuit structures |
EP0416165B1 (fr) * | 1989-09-08 | 1994-12-14 | Siemens Aktiengesellschaft | Procédé d' aplanissement global de surfaces pour circuits semi-conducteurs integrés |
EP0424608B1 (fr) * | 1989-10-25 | 1993-12-01 | International Business Machines Corporation | Formation de rainures d'isolation larges remplies de diélectrique pour dispositifs semi-conducteurs |
US5173439A (en) * | 1989-10-25 | 1992-12-22 | International Business Machines Corporation | Forming wide dielectric-filled isolation trenches in semi-conductors |
US5290396A (en) * | 1991-06-06 | 1994-03-01 | Lsi Logic Corporation | Trench planarization techniques |
US5413966A (en) * | 1990-12-20 | 1995-05-09 | Lsi Logic Corporation | Shallow trench etch |
US5248625A (en) * | 1991-06-06 | 1993-09-28 | Lsi Logic Corporation | Techniques for forming isolation structures |
US5252503A (en) * | 1991-06-06 | 1993-10-12 | Lsi Logic Corporation | Techniques for forming isolation structures |
US5225358A (en) * | 1991-06-06 | 1993-07-06 | Lsi Logic Corporation | Method of forming late isolation with polishing |
US5382541A (en) * | 1992-08-26 | 1995-01-17 | Harris Corporation | Method for forming recessed oxide isolation containing deep and shallow trenches |
FR2717307B1 (fr) * | 1994-03-11 | 1996-07-19 | Maryse Paoli | Procede d'isolement de zones actives d'un substrat semi-conducteur par tranchees peu profondes quasi planes, et dispositif correspondant |
FR2717306B1 (fr) * | 1994-03-11 | 1996-07-19 | Maryse Paoli | Procédé d'isolement de zones actives d'un substrat semi-conducteur par tranchées peu profondes, notamment étroites, et dispositif correspondant. |
US5532188A (en) * | 1994-03-30 | 1996-07-02 | Wright; Peter J. | Global planarization of multiple layers |
US5459096A (en) * | 1994-07-05 | 1995-10-17 | Motorola Inc. | Process for fabricating a semiconductor device using dual planarization layers |
DE19538005A1 (de) * | 1995-10-12 | 1997-04-17 | Fraunhofer Ges Forschung | Verfahren zum Erzeugen einer Grabenisolation in einem Substrat |
US5904539A (en) * | 1996-03-21 | 1999-05-18 | Advanced Micro Devices, Inc. | Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties |
WO1997038442A1 (fr) * | 1996-04-10 | 1997-10-16 | Advanced Micro Devices, Inc. | Isolement de tranchee de semi-conducteur associe a une methodologie amelioree de planarisation |
US5926713A (en) * | 1996-04-17 | 1999-07-20 | Advanced Micro Devices, Inc. | Method for achieving global planarization by forming minimum mesas in large field areas |
US5899727A (en) | 1996-05-02 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization |
KR100236097B1 (ko) * | 1996-10-30 | 1999-12-15 | 김영환 | 반도체 장치의 격리막 형성방법 |
US5721172A (en) * | 1996-12-02 | 1998-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers |
US6063702A (en) * | 1997-01-27 | 2000-05-16 | Chartered Semiconductor Manufacturing, Ltd. | Global planarization method for inter level dielectric layers using IDL blocks |
US5792707A (en) * | 1997-01-27 | 1998-08-11 | Chartered Semiconductor Manufacturing Ltd. | Global planarization method for inter level dielectric layers of integrated circuits |
US6025270A (en) * | 1997-02-03 | 2000-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Planarization process using tailored etchback and CMP |
US5804490A (en) * | 1997-04-14 | 1998-09-08 | International Business Machines Corporation | Method of filling shallow trenches |
KR100458475B1 (ko) * | 1997-06-30 | 2005-02-23 | 주식회사 하이닉스반도체 | 반도체소자의평탄화방법 |
KR100363093B1 (ko) * | 2000-07-28 | 2002-12-05 | 삼성전자 주식회사 | 반도체 소자의 층간 절연막 평탄화 방법 |
US6531265B2 (en) | 2000-12-14 | 2003-03-11 | International Business Machines Corporation | Method to planarize semiconductor surface |
US6559009B2 (en) * | 2001-03-29 | 2003-05-06 | Macronix International Co. Ltd. | Method of fabricating a high-coupling ratio flash memory |
DE10123509A1 (de) * | 2001-05-15 | 2002-11-28 | Infineon Technologies Ag | Verfahren zur Planarisierung einer Halbleiterstruktur |
US6617241B1 (en) | 2003-01-15 | 2003-09-09 | Institute Of Microelectronics | Method of thick film planarization |
US7323417B2 (en) * | 2004-09-21 | 2008-01-29 | Molecular Imprints, Inc. | Method of forming a recessed structure employing a reverse tone process |
US7262070B2 (en) * | 2003-09-29 | 2007-08-28 | Intel Corporation | Method to make a weight compensating/tuning layer on a substrate |
US7205244B2 (en) * | 2004-09-21 | 2007-04-17 | Molecular Imprints | Patterning substrates employing multi-film layers defining etch-differential interfaces |
US7547504B2 (en) | 2004-09-21 | 2009-06-16 | Molecular Imprints, Inc. | Pattern reversal employing thick residual layers |
US7259102B2 (en) * | 2005-09-30 | 2007-08-21 | Molecular Imprints, Inc. | Etching technique to planarize a multi-layer structure |
US8728891B2 (en) | 2010-09-21 | 2014-05-20 | Infineon Technologies Austria Ag | Method for producing contact openings in a semiconductor body and self-aligned contact structures on a semiconductor body |
DE102010046213B3 (de) * | 2010-09-21 | 2012-02-09 | Infineon Technologies Austria Ag | Verfahren zur Herstellung eines Strukturelements und Halbleiterbauelement mit einem Strukturelement |
US8409986B2 (en) * | 2011-01-11 | 2013-04-02 | Institute of Microelectronics, Chinese Academy of Sciences | Method for improving within die uniformity of metal plug chemical mechanical planarization process in gate last route |
US11201426B2 (en) * | 2018-08-13 | 2021-12-14 | Apple Inc. | Electrical contact appearance and protection |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4038110A (en) * | 1974-06-17 | 1977-07-26 | Ibm Corporation | Planarization of integrated circuit surfaces through selective photoresist masking |
US3976524A (en) * | 1974-06-17 | 1976-08-24 | Ibm Corporation | Planarization of integrated circuit surfaces through selective photoresist masking |
US4199384A (en) * | 1979-01-29 | 1980-04-22 | Rca Corporation | Method of making a planar semiconductor on insulating substrate device utilizing the deposition of a dual dielectric layer between device islands |
JPS5893327A (ja) * | 1981-11-30 | 1983-06-03 | Toshiba Corp | 微細加工法 |
DE3228399A1 (de) * | 1982-07-29 | 1984-02-02 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen einer monolithisch integrierten schaltung |
US4470874A (en) * | 1983-12-15 | 1984-09-11 | International Business Machines Corporation | Planarization of multi-level interconnected metallization system |
US4481070A (en) * | 1984-04-04 | 1984-11-06 | Advanced Micro Devices, Inc. | Double planarization process for multilayer metallization of integrated circuit structures |
US4594769A (en) * | 1984-06-15 | 1986-06-17 | Signetics Corporation | Method of forming insulator of selectively varying thickness on patterned conductive layer |
US4545852A (en) * | 1984-06-20 | 1985-10-08 | Hewlett-Packard Company | Planarization of dielectric films on integrated circuits |
US4708767A (en) * | 1984-10-05 | 1987-11-24 | Signetics Corporation | Method for providing a semiconductor device with planarized contacts |
US4541169A (en) * | 1984-10-29 | 1985-09-17 | International Business Machines Corporation | Method for making studs for interconnecting metallization layers at different levels in a semiconductor chip |
JPH0642482B2 (ja) * | 1984-11-15 | 1994-06-01 | 株式会社東芝 | 半導体装置の製造方法 |
US4789760A (en) * | 1985-04-30 | 1988-12-06 | Advanced Micro Devices, Inc. | Via in a planarized dielectric and process for producing same |
US4605470A (en) * | 1985-06-10 | 1986-08-12 | Advanced Micro Devices, Inc. | Method for interconnecting conducting layers of an integrated circuit device |
JPS61287245A (ja) * | 1985-06-14 | 1986-12-17 | Hitachi Ltd | 多層配線法 |
US4662064A (en) * | 1985-08-05 | 1987-05-05 | Rca Corporation | Method of forming multi-level metallization |
JPS62169442A (ja) * | 1986-01-22 | 1987-07-25 | Nec Corp | 素子分離領域の形成方法 |
FR2599892B1 (fr) * | 1986-06-10 | 1988-08-26 | Schiltz Andre | Procede d'aplanissement d'un substrat semiconducteur revetu d'une couche dielectrique |
JPS6430243A (en) * | 1987-07-24 | 1989-02-01 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
US4836885A (en) * | 1988-05-03 | 1989-06-06 | International Business Machines Corporation | Planarization process for wide trench isolation |
-
1987
- 1987-07-21 NL NL8701717A patent/NL8701717A/nl not_active Application Discontinuation
-
1988
- 1988-07-14 EP EP88201515A patent/EP0300569B1/fr not_active Expired - Lifetime
- 1988-07-14 DE DE3852583T patent/DE3852583T2/de not_active Expired - Fee Related
- 1988-07-18 JP JP63177255A patent/JPS6437840A/ja active Pending
- 1988-07-21 KR KR1019880009112A patent/KR890003005A/ko not_active Application Discontinuation
-
1990
- 1990-05-10 US US07/522,490 patent/US5015602A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR890003005A (ko) | 1989-04-12 |
EP0300569A1 (fr) | 1989-01-25 |
JPS6437840A (en) | 1989-02-08 |
DE3852583T2 (de) | 1995-07-13 |
US5015602A (en) | 1991-05-14 |
DE3852583D1 (de) | 1995-02-09 |
EP0300569B1 (fr) | 1994-12-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A1B | A search report has been drawn up | ||
BV | The patent application has lapsed |