NL8400960A - Werkwijze voor het vervaardigen van een constructie met geintegreerd circuit van het mos-type met een zelf-richtende dubbele laag van polykristallijn silicium. - Google Patents

Werkwijze voor het vervaardigen van een constructie met geintegreerd circuit van het mos-type met een zelf-richtende dubbele laag van polykristallijn silicium. Download PDF

Info

Publication number
NL8400960A
NL8400960A NL8400960A NL8400960A NL8400960A NL 8400960 A NL8400960 A NL 8400960A NL 8400960 A NL8400960 A NL 8400960A NL 8400960 A NL8400960 A NL 8400960A NL 8400960 A NL8400960 A NL 8400960A
Authority
NL
Netherlands
Prior art keywords
layer
polycrystalline silicon
silicon
dioxide
region
Prior art date
Application number
NL8400960A
Other languages
English (en)
Dutch (nl)
Original Assignee
Ates Componenti Elettron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ates Componenti Elettron filed Critical Ates Componenti Elettron
Publication of NL8400960A publication Critical patent/NL8400960A/nl

Links

Classifications

    • H10P76/40—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
NL8400960A 1983-03-31 1984-03-27 Werkwijze voor het vervaardigen van een constructie met geintegreerd circuit van het mos-type met een zelf-richtende dubbele laag van polykristallijn silicium. NL8400960A (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT2039183 1983-03-31
IT20391/83A IT1218344B (it) 1983-03-31 1983-03-31 Processo per l'autoallineamento di un doppio strato di silicio policristallino,in un dispositivo a circuito integrato,mediante un' operazione di ossidazione

Publications (1)

Publication Number Publication Date
NL8400960A true NL8400960A (nl) 1984-10-16

Family

ID=11166285

Family Applications (1)

Application Number Title Priority Date Filing Date
NL8400960A NL8400960A (nl) 1983-03-31 1984-03-27 Werkwijze voor het vervaardigen van een constructie met geintegreerd circuit van het mos-type met een zelf-richtende dubbele laag van polykristallijn silicium.

Country Status (7)

Country Link
US (1) US4488931A (member.php)
JP (1) JPS59211282A (member.php)
DE (1) DE3411960A1 (member.php)
FR (1) FR2543738B1 (member.php)
GB (1) GB2138632B (member.php)
IT (1) IT1218344B (member.php)
NL (1) NL8400960A (member.php)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1213192B (it) * 1984-07-19 1989-12-14 Ates Componenti Elettron Processo per la fabbricazione di transistori ad effetto di campo agate isolato (igfet) ad elevata velocita' di risposta in circuiti integrati ad alta densita'.
JPS61136274A (ja) * 1984-12-07 1986-06-24 Toshiba Corp 半導体装置
US4735919A (en) * 1986-04-15 1988-04-05 General Electric Company Method of making a floating gate memory cell
US4683640A (en) * 1986-04-15 1987-08-04 Rca Corporation Method of making a floating gate memory cell
US4808555A (en) * 1986-07-10 1989-02-28 Motorola, Inc. Multiple step formation of conductive material layers
US5089863A (en) * 1988-09-08 1992-02-18 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with T-shaped gate electrode
US5272100A (en) * 1988-09-08 1993-12-21 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with T-shaped gate electrode and manufacturing method therefor
US5543646A (en) * 1988-09-08 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with a shaped gate electrode

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1540450A (en) * 1975-10-29 1979-02-14 Intel Corp Self-aligning double polycrystalline silicon etching process
US4142926A (en) * 1977-02-24 1979-03-06 Intel Corporation Self-aligning double polycrystalline silicon etching process
EP0002107A3 (en) * 1977-11-17 1979-09-05 Rca Corporation Method of making a planar semiconductor device
US4190466A (en) * 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
US4239559A (en) * 1978-04-21 1980-12-16 Hitachi, Ltd. Method for fabricating a semiconductor device by controlled diffusion between adjacent layers
US4234362A (en) * 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4355455A (en) * 1979-07-19 1982-10-26 National Semiconductor Corporation Method of manufacture for self-aligned floating gate memory cell
FR2468185A1 (fr) * 1980-10-17 1981-04-30 Intel Corp Procede de fabrication d'une matrice de memoire electriquement programmable a haute densite

Also Published As

Publication number Publication date
GB8408434D0 (en) 1984-05-10
DE3411960A1 (de) 1984-10-04
FR2543738A1 (fr) 1984-10-05
GB2138632A (en) 1984-10-24
DE3411960C2 (member.php) 1992-04-02
US4488931A (en) 1984-12-18
IT1218344B (it) 1990-04-12
GB2138632B (en) 1986-10-15
FR2543738B1 (fr) 1986-06-20
JPS59211282A (ja) 1984-11-30
IT8320391A0 (it) 1983-03-31

Similar Documents

Publication Publication Date Title
US4142926A (en) Self-aligning double polycrystalline silicon etching process
US6171916B1 (en) Semiconductor device having buried gate electrode with silicide layer and manufacture method thereof
US4743953A (en) Random access memory cell with MIS capacitor having insulator of oxide of doped metal
US5872035A (en) Method of forming a floating gate in a flash memory device
JP2904533B2 (ja) 半導体装置の製造方法
JP2749750B2 (ja) 集積回路チップの製造方法
US5679595A (en) Self-registered capacitor bottom plate-local interconnect scheme for DRAM
JPH06260497A (ja) 半導体装置及びその製造方法
NL8400960A (nl) Werkwijze voor het vervaardigen van een constructie met geintegreerd circuit van het mos-type met een zelf-richtende dubbele laag van polykristallijn silicium.
US4261772A (en) Method for forming voltage-invariant capacitors for MOS type integrated circuit device utilizing oxidation and reflow techniques
US4892845A (en) Method for forming contacts through a thick oxide layer on a semiconductive device
JPH0330982B2 (member.php)
JPS5980966A (ja) ゲ−ト−絶縁体−半導体形素子を含む集積回路のゲ−ト構造及び該構造を用いる集積回路製造法
US5972777A (en) Method of forming isolation by nitrogen implant to reduce bird's beak
JPS58220445A (ja) 半導体集積回路の製造方法
US5447881A (en) Method for the fabrication of capacitor in semiconductor device
EP0034508A1 (en) Self-aligned buried contact and method of making
US4499653A (en) Small dimension field effect transistor using phosphorous doped silicon glass reflow process
JPH06209085A (ja) スタック形ｄｒａｍコンデンサ構造体とその製造方法
KR100382397B1 (ko) 기판내에 부분적으로 연장된 와이어링을 갖춘 반도체소자의 제조 방법 및 상기 방법에 따라 제조된 반도체 소자
JP3471884B2 (ja) 半導体装置の製造方法
JPH05299599A (ja) 半導体装置およびその製造方法
JPH0393233A (ja) 半導体装置の製造方法
JPH01201940A (ja) 半導体装置の電極配線形成方法
JPH06302778A (ja) 半導体装置とその製造方法

Legal Events

Date Code Title Description
A85 Still pending on 85-01-01
BA A request for search or an international-type search has been filed
BB A search report has been drawn up
BC A request for examination has been filed
BV The patent application has lapsed