NL7601304A - Alleen-lees geheugen met halfgeleiders. - Google Patents

Alleen-lees geheugen met halfgeleiders.

Info

Publication number
NL7601304A
NL7601304A NL7601304A NL7601304A NL7601304A NL 7601304 A NL7601304 A NL 7601304A NL 7601304 A NL7601304 A NL 7601304A NL 7601304 A NL7601304 A NL 7601304A NL 7601304 A NL7601304 A NL 7601304A
Authority
NL
Netherlands
Prior art keywords
semiconductors
read
memory
Prior art date
Application number
NL7601304A
Other languages
English (en)
Dutch (nl)
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of NL7601304A publication Critical patent/NL7601304A/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G11C17/123—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices comprising cells having several storage transistors connected in series

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
NL7601304A 1975-02-10 1976-02-09 Alleen-lees geheugen met halfgeleiders. NL7601304A (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1628075A JPS5713079B2 (ja) 1975-02-10 1975-02-10

Publications (1)

Publication Number Publication Date
NL7601304A true NL7601304A (nl) 1976-08-12

Family

ID=11912127

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7601304A NL7601304A (nl) 1975-02-10 1976-02-09 Alleen-lees geheugen met halfgeleiders.

Country Status (10)

Country Link
US (1) US4240151A (ja)
JP (1) JPS5713079B2 (ja)
CA (1) CA1070428A (ja)
DE (1) DE2605184C3 (ja)
FR (1) FR2300390A1 (ja)
GB (1) GB1534336A (ja)
HK (1) HK57381A (ja)
IT (1) IT1055161B (ja)
MY (1) MY8200177A (ja)
NL (1) NL7601304A (ja)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2740154A1 (de) * 1977-09-06 1979-03-15 Siemens Ag Monolithisch integrierte halbleiteranordnung
JPS54133037A (en) * 1978-04-06 1979-10-16 Nec Corp Memory circuit
JPS5820507Y2 (ja) * 1978-10-27 1983-04-28 三洋電機株式会社 包装用密封器
US4340943A (en) * 1979-05-31 1982-07-20 Tokyo Shibaura Denki Kabushiki Kaisha Memory device utilizing MOS FETs
US4476478A (en) * 1980-04-24 1984-10-09 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor read only memory and method of making the same
JPS5736498A (en) * 1980-08-13 1982-02-27 Hitachi Ltd Multisplit longitudinal type rom
US4395646A (en) * 1980-11-03 1983-07-26 International Business Machines Corp. Logic performing cell for use in array structures
EP0054102A3 (en) * 1980-12-11 1983-07-27 Rockwell International Corporation Very high density cells comprising a rom and method of manufacturing same
JPS57189389A (en) * 1981-05-18 1982-11-20 Hitachi Ltd Mos integrated circuit device
JPS586589A (ja) * 1981-07-01 1983-01-14 Hitachi Ltd 論理回路
US4725986A (en) * 1983-09-20 1988-02-16 International Business Machines Corporation FET read only memory cell with word line augmented precharging of the bit lines
US4633220A (en) * 1984-11-29 1986-12-30 American Microsystems, Inc. Decoder using pass-transistor networks
US4845679A (en) * 1987-03-30 1989-07-04 Honeywell Inc. Diode-FET logic circuitry
US5459692A (en) * 1992-07-07 1995-10-17 Oki Electric Industry Co., Ltd. Semiconductor memory device and method for reading data therefrom
US5761700A (en) * 1994-12-27 1998-06-02 Motorola Inc. ROM mapping and inversion apparatus and method
US5889694A (en) * 1996-03-05 1999-03-30 Shepard; Daniel R. Dual-addressed rectifier storage device
US5673218A (en) * 1996-03-05 1997-09-30 Shepard; Daniel R. Dual-addressed rectifier storage device
US6956757B2 (en) 2000-06-22 2005-10-18 Contour Semiconductor, Inc. Low cost high density rectifier matrix memory
US7649787B2 (en) * 2006-09-05 2010-01-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7623367B2 (en) * 2006-10-13 2009-11-24 Agere Systems Inc. Read-only memory device and related method of design
US7813157B2 (en) 2007-10-29 2010-10-12 Contour Semiconductor, Inc. Non-linear conductor memory
US8325556B2 (en) 2008-10-07 2012-12-04 Contour Semiconductor, Inc. Sequencing decoder circuit
WO2011118351A1 (en) 2010-03-25 2011-09-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3618050A (en) * 1969-05-07 1971-11-02 Teletype Corp Read-only memory arrays in which a portion of the memory-addressing circuitry is integral to the array
JPS5117370B2 (ja) * 1971-09-10 1976-06-02
GB1357515A (en) * 1972-03-10 1974-06-26 Matsushita Electronics Corp Method for manufacturing an mos integrated circuit
JPS5332661B2 (ja) * 1972-05-16 1978-09-09
JPS5317022B2 (ja) * 1972-05-29 1978-06-05
US3866186A (en) * 1972-05-16 1975-02-11 Tokyo Shibaura Electric Co Logic circuit arrangement employing insulated gate field effect transistors
JPS4943559A (ja) * 1972-08-31 1974-04-24
US3934233A (en) * 1973-09-24 1976-01-20 Texas Instruments Incorporated Read-only-memory for electronic calculator
JPS531626B2 (ja) * 1975-01-06 1978-01-20
US4023122A (en) * 1975-01-28 1977-05-10 Nippon Electric Company, Ltd. Signal generating circuit
JPS5258452A (en) * 1975-11-10 1977-05-13 Hitachi Ltd Mis logic circuit

Also Published As

Publication number Publication date
IT1055161B (it) 1981-12-21
HK57381A (en) 1981-12-04
CA1070428A (en) 1980-01-22
DE2605184C3 (de) 1982-07-22
DE2605184B2 (de) 1979-11-29
JPS5713079B2 (ja) 1982-03-15
JPS5192134A (ja) 1976-08-12
MY8200177A (en) 1982-12-31
US4240151A (en) 1980-12-16
GB1534336A (en) 1978-12-06
DE2605184A1 (de) 1976-12-23
FR2300390A1 (fr) 1976-09-03
FR2300390B1 (ja) 1980-07-25

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Legal Events

Date Code Title Description
BC A request for examination has been filed
A85 Still pending on 85-01-01
BV The patent application has lapsed