JPS57189389A - Mos integrated circuit device - Google Patents
Mos integrated circuit deviceInfo
- Publication number
- JPS57189389A JPS57189389A JP56073498A JP7349881A JPS57189389A JP S57189389 A JPS57189389 A JP S57189389A JP 56073498 A JP56073498 A JP 56073498A JP 7349881 A JP7349881 A JP 7349881A JP S57189389 A JPS57189389 A JP S57189389A
- Authority
- JP
- Japan
- Prior art keywords
- mosfets
- address
- signals
- phip
- precharge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To synchronize precharge timings and address input timings surely by providing gate means that transmit signals in sychronization with precharge pulses on the input side of an address decoder. CONSTITUTION:Timing signals phip are applied commonly to (p) channels MOSFETs Q4-Q6 for precharging and (n) channels MOSFETs Q1-Q3 for discharging, and an X address signal Ax is applied to the ROM of the part shown by the mark O. p Channel MOSFETs Q7-Q10 for precharging are also provided to the data lines D1, D'1, D2, D'2 of a memory array MAR, and are controlled by the signals phip. The (p) channel transmission gates MOSFETs Q15-Q17 controlled by the signals phip are provided to the input side of an X address decoder X-DCR, and the sure synchronization with the precharge period of the ROM constituting the decoder X-DCR and the address input signal Ax is accomplished.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56073498A JPS57189389A (en) | 1981-05-18 | 1981-05-18 | Mos integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56073498A JPS57189389A (en) | 1981-05-18 | 1981-05-18 | Mos integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57189389A true JPS57189389A (en) | 1982-11-20 |
Family
ID=13519973
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56073498A Pending JPS57189389A (en) | 1981-05-18 | 1981-05-18 | Mos integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57189389A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5192134A (en) * | 1975-02-10 | 1976-08-12 |
-
1981
- 1981-05-18 JP JP56073498A patent/JPS57189389A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5192134A (en) * | 1975-02-10 | 1976-08-12 |
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