JPS6457488A - Dynamic type ram - Google Patents

Dynamic type ram

Info

Publication number
JPS6457488A
JPS6457488A JP62212824A JP21282487A JPS6457488A JP S6457488 A JPS6457488 A JP S6457488A JP 62212824 A JP62212824 A JP 62212824A JP 21282487 A JP21282487 A JP 21282487A JP S6457488 A JPS6457488 A JP S6457488A
Authority
JP
Japan
Prior art keywords
word lines
plural
selecting
decoder
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62212824A
Other languages
Japanese (ja)
Inventor
Shinichi Miyatake
Shinji Udo
Hiromi Saito
Yasuhiro Kasama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP62212824A priority Critical patent/JPS6457488A/en
Publication of JPS6457488A publication Critical patent/JPS6457488A/en
Pending legal-status Critical Current

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  • Dram (AREA)

Abstract

PURPOSE:To highly accurately offset the coupling noise of a data line, by disposing plural dummy word lines correspondingly to plural word lines assigned to the decoder of a unit and using plural word line selecting timing signals as selecting signals thereof. CONSTITUTION:As the dummy word line for offsetting the coupling of the word lines W0-W3 and the data lines D, the inverse of D through a memory cell, the plural dummy word lines DW0-DW3 are disposed correspondingly to the plural word lines assigned to the decoder of the unit and as the selecting signal, the plural word line selecting timing signals supplied to the decoder UDCR of the unit are used. Accordingly, the word lines and the dummy word lines can be controlled by the same selecting timing signal. Thereby, the coupling noise appearing on the data line can be offset at high accuracy to increase the level margin of a reading signal from the memory cell.
JP62212824A 1987-08-28 1987-08-28 Dynamic type ram Pending JPS6457488A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62212824A JPS6457488A (en) 1987-08-28 1987-08-28 Dynamic type ram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62212824A JPS6457488A (en) 1987-08-28 1987-08-28 Dynamic type ram

Publications (1)

Publication Number Publication Date
JPS6457488A true JPS6457488A (en) 1989-03-03

Family

ID=16628965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62212824A Pending JPS6457488A (en) 1987-08-28 1987-08-28 Dynamic type ram

Country Status (1)

Country Link
JP (1) JPS6457488A (en)

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