JPS54133037A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS54133037A
JPS54133037A JP4098178A JP4098178A JPS54133037A JP S54133037 A JPS54133037 A JP S54133037A JP 4098178 A JP4098178 A JP 4098178A JP 4098178 A JP4098178 A JP 4098178A JP S54133037 A JPS54133037 A JP S54133037A
Authority
JP
Japan
Prior art keywords
row
circuit
making
line
high potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4098178A
Other languages
Japanese (ja)
Other versions
JPS6131559B2 (en
Inventor
Tsutomu Iima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4098178A priority Critical patent/JPS54133037A/en
Publication of JPS54133037A publication Critical patent/JPS54133037A/en
Publication of JPS6131559B2 publication Critical patent/JPS6131559B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G11C17/123—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices comprising cells having several storage transistors connected in series

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To prevent the lowering in the readout speed and malfunction due to the capacitive coupling of MOSFET, by adding the second row selection circuit operated almost in synchronizing with the row selection circuit. CONSTITUTION:The line selection lines A1 to A64 are precharged by making high potential the line precharge signal phiAP. Simultaneously, FETMmp is conducted by making the row precharge signal phiMP high potential. The precharge of the memory cell circuit 12 and the second row selection circuit 14 are made by conducting one FET in the first row selection circuit 13 by the row selection lines C1 to C4. Further, the line decoder circuit 11 selects one NAND logic by making low potential for phiAP and making high potential for the discharge signal phiAd. Next, when FETMmd is conducted by making low potential for phiMP and making high potential for the row discharge signal phiMd, the content of the memory cell as the row address designated is outputted to the OUT 1. Thus, the circuit 14 prevents the potential drop of line selection lines caused by the coupling capacitance between the memory cell and the line selection lines.
JP4098178A 1978-04-06 1978-04-06 Memory circuit Granted JPS54133037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4098178A JPS54133037A (en) 1978-04-06 1978-04-06 Memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4098178A JPS54133037A (en) 1978-04-06 1978-04-06 Memory circuit

Publications (2)

Publication Number Publication Date
JPS54133037A true JPS54133037A (en) 1979-10-16
JPS6131559B2 JPS6131559B2 (en) 1986-07-21

Family

ID=12595600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4098178A Granted JPS54133037A (en) 1978-04-06 1978-04-06 Memory circuit

Country Status (1)

Country Link
JP (1) JPS54133037A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61113197A (en) * 1985-10-31 1986-05-31 Nec Corp Memory circuit
JPS62229596A (en) * 1986-03-31 1987-10-08 Toshiba Corp Semiconductor memory device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5192134A (en) * 1975-02-10 1976-08-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5192134A (en) * 1975-02-10 1976-08-12

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61113197A (en) * 1985-10-31 1986-05-31 Nec Corp Memory circuit
JPS6363999B2 (en) * 1985-10-31 1988-12-09
JPS62229596A (en) * 1986-03-31 1987-10-08 Toshiba Corp Semiconductor memory device

Also Published As

Publication number Publication date
JPS6131559B2 (en) 1986-07-21

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