NL163903C - Halfgeleiderinrichting, waarbij een deel van het oppervlak is bedekt met een isolerende laag en een op de isolerende laag aangebrachte beschermende laag van gedoteerd siliciumdioxyde. - Google Patents

Halfgeleiderinrichting, waarbij een deel van het oppervlak is bedekt met een isolerende laag en een op de isolerende laag aangebrachte beschermende laag van gedoteerd siliciumdioxyde.

Info

Publication number
NL163903C
NL163903C NL7014340.A NL7014340A NL163903C NL 163903 C NL163903 C NL 163903C NL 7014340 A NL7014340 A NL 7014340A NL 163903 C NL163903 C NL 163903C
Authority
NL
Netherlands
Prior art keywords
insulating layer
semiconductor device
silicon dioxide
doped silicon
surface covered
Prior art date
Application number
NL7014340.A
Other languages
English (en)
Dutch (nl)
Other versions
NL7014340A (cg-RX-API-DMAC7.html
NL163903B (nl
Original Assignee
Tokyo Shibaura Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP45025373A external-priority patent/JPS4926474B1/ja
Priority claimed from JP45054335A external-priority patent/JPS4926750B1/ja
Application filed by Tokyo Shibaura Electric Co filed Critical Tokyo Shibaura Electric Co
Publication of NL7014340A publication Critical patent/NL7014340A/xx
Publication of NL163903B publication Critical patent/NL163903B/xx
Application granted granted Critical
Publication of NL163903C publication Critical patent/NL163903C/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Thyristors (AREA)
  • Bipolar Transistors (AREA)
NL7014340.A 1970-03-27 1970-09-30 Halfgeleiderinrichting, waarbij een deel van het oppervlak is bedekt met een isolerende laag en een op de isolerende laag aangebrachte beschermende laag van gedoteerd siliciumdioxyde. NL163903C (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP45025373A JPS4926474B1 (cg-RX-API-DMAC7.html) 1970-03-27 1970-03-27
JP45054335A JPS4926750B1 (cg-RX-API-DMAC7.html) 1970-06-24 1970-06-24

Publications (3)

Publication Number Publication Date
NL7014340A NL7014340A (cg-RX-API-DMAC7.html) 1971-09-29
NL163903B NL163903B (nl) 1980-05-16
NL163903C true NL163903C (nl) 1980-10-15

Family

ID=26362969

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7014340.A NL163903C (nl) 1970-03-27 1970-09-30 Halfgeleiderinrichting, waarbij een deel van het oppervlak is bedekt met een isolerende laag en een op de isolerende laag aangebrachte beschermende laag van gedoteerd siliciumdioxyde.

Country Status (6)

Country Link
US (1) US3694707A (cg-RX-API-DMAC7.html)
DE (1) DE2048201B2 (cg-RX-API-DMAC7.html)
ES (1) ES384149A1 (cg-RX-API-DMAC7.html)
FR (1) FR2083799A5 (cg-RX-API-DMAC7.html)
GB (1) GB1272033A (cg-RX-API-DMAC7.html)
NL (1) NL163903C (cg-RX-API-DMAC7.html)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2326314C2 (de) * 1973-05-23 1983-10-27 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung von Reliefstrukturen
JPS55108763A (en) 1979-01-24 1980-08-21 Toshiba Corp Schottky barrier compound semiconductor device
DE3213988A1 (de) * 1982-04-16 1983-10-20 L. & C. Steinmüller GmbH, 5270 Gummersbach Verfahren zur reinigung von gasdurchstroemten waermetauschern
US5171716A (en) * 1986-12-19 1992-12-15 North American Philips Corp. Method of manufacturing semiconductor device with reduced packaging stress
US5045918A (en) * 1986-12-19 1991-09-03 North American Philips Corp. Semiconductor device with reduced packaging stress
US5068205A (en) * 1989-05-26 1991-11-26 General Signal Corporation Header mounted chemically sensitive ISFET and method of manufacture

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1544318C3 (de) * 1965-10-16 1973-10-31 Telefunken Patentverwertungs Gmbh, 7900 Ulm Verfahren zum Erzeugen dotierter Zonen in Halbleiterkörpern
US3455020A (en) * 1966-10-13 1969-07-15 Rca Corp Method of fabricating insulated-gate field-effect devices
US3485684A (en) * 1967-03-30 1969-12-23 Trw Semiconductors Inc Dislocation enhancement control of silicon by introduction of large diameter atomic metals

Also Published As

Publication number Publication date
ES384149A1 (es) 1973-06-01
NL7014340A (cg-RX-API-DMAC7.html) 1971-09-29
DE2048201A1 (de) 1971-10-14
DE2048201B2 (de) 1976-08-05
US3694707A (en) 1972-09-26
FR2083799A5 (cg-RX-API-DMAC7.html) 1971-12-17
GB1272033A (en) 1972-04-26
NL163903B (nl) 1980-05-16

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Legal Events

Date Code Title Description
V4 Discontinued because of reaching the maximum lifetime of a patent