NL1010203C2 - Sperlaag en fabricagewerkwijze hiervoor. - Google Patents

Sperlaag en fabricagewerkwijze hiervoor. Download PDF

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Publication number
NL1010203C2
NL1010203C2 NL1010203A NL1010203A NL1010203C2 NL 1010203 C2 NL1010203 C2 NL 1010203C2 NL 1010203 A NL1010203 A NL 1010203A NL 1010203 A NL1010203 A NL 1010203A NL 1010203 C2 NL1010203 C2 NL 1010203C2
Authority
NL
Netherlands
Prior art keywords
layer
barrier layer
forming
barrier
conductive
Prior art date
Application number
NL1010203A
Other languages
English (en)
Dutch (nl)
Inventor
Tri-Rung Yew
Water Lur
Shih-Wei Sun
Yimin Huang
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW087101691A external-priority patent/TW365698B/zh
Priority to US09/052,608 priority Critical patent/US6025264A/en
Priority to GB9819997A priority patent/GB2341484B/en
Priority to JP27038298A priority patent/JP3184159B2/ja
Priority to FR9812017A priority patent/FR2774809B1/fr
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to NL1010203A priority patent/NL1010203C2/nl
Priority to DE19844451A priority patent/DE19844451A1/de
Application granted granted Critical
Publication of NL1010203C2 publication Critical patent/NL1010203C2/nl

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
NL1010203A 1998-02-09 1998-09-28 Sperlaag en fabricagewerkwijze hiervoor. NL1010203C2 (nl)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US09/052,608 US6025264A (en) 1998-02-09 1998-03-31 Fabricating method of a barrier layer
GB9819997A GB2341484B (en) 1998-02-09 1998-09-14 Barrier layer and fabricating method of the same
JP27038298A JP3184159B2 (ja) 1998-02-09 1998-09-24 バリヤ層及びその製造方法
FR9812017A FR2774809B1 (fr) 1998-02-09 1998-09-25 Structure de couches barriere comportant deux couches et procede de fabrication
NL1010203A NL1010203C2 (nl) 1998-02-09 1998-09-28 Sperlaag en fabricagewerkwijze hiervoor.
DE19844451A DE19844451A1 (de) 1998-02-09 1998-09-28 Sperrschicht und Herstellungsverfahren dafür

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
TW087101691A TW365698B (en) 1998-02-09 1998-02-09 Structure of barrier layer and the manufacturing method thereof
TW87101691 1998-02-09
GB9819997A GB2341484B (en) 1998-02-09 1998-09-14 Barrier layer and fabricating method of the same
GB9819997 1998-09-14
NL1010203A NL1010203C2 (nl) 1998-02-09 1998-09-28 Sperlaag en fabricagewerkwijze hiervoor.
NL1010203 1998-09-28

Publications (1)

Publication Number Publication Date
NL1010203C2 true NL1010203C2 (nl) 2000-03-30

Family

ID=27269479

Family Applications (1)

Application Number Title Priority Date Filing Date
NL1010203A NL1010203C2 (nl) 1998-02-09 1998-09-28 Sperlaag en fabricagewerkwijze hiervoor.

Country Status (6)

Country Link
US (1) US6025264A (de)
JP (1) JP3184159B2 (de)
DE (1) DE19844451A1 (de)
FR (1) FR2774809B1 (de)
GB (1) GB2341484B (de)
NL (1) NL1010203C2 (de)

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TW374948B (en) * 1998-07-28 1999-11-21 United Microelectronics Corp Method of prevention of poisoning trenches in dual damascene process structures and dielectric layer windows
US6265779B1 (en) * 1998-08-11 2001-07-24 International Business Machines Corporation Method and material for integration of fuorine-containing low-k dielectrics
US6559050B1 (en) 1998-09-29 2003-05-06 Texas Instruments Incorporated Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices
JP4095731B2 (ja) 1998-11-09 2008-06-04 株式会社ルネサステクノロジ 半導体装置の製造方法及び半導体装置
TW400619B (en) * 1999-03-05 2000-08-01 United Microelectronics Corp The manufacture method of dual damascene structure
US6410457B1 (en) * 1999-09-01 2002-06-25 Applied Materials, Inc. Method for improving barrier layer adhesion to HDP-FSG thin films
KR20010053894A (ko) * 1999-12-02 2001-07-02 박종섭 반도체소자의 배리어층 형성방법
KR100749970B1 (ko) * 2000-03-20 2007-08-16 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 반도체 디바이스 및 그 제조 방법
US6444136B1 (en) * 2000-04-25 2002-09-03 Newport Fab, Llc Fabrication of improved low-k dielectric structures
US6297158B1 (en) 2000-05-31 2001-10-02 Taiwan Semiconductor Manufacturing Company Stress management of barrier metal for resolving CU line corrosion
US6528432B1 (en) * 2000-12-05 2003-03-04 Advanced Micro Devices, Inc. H2-or H2/N2-plasma treatment to prevent organic ILD degradation
US6689684B1 (en) * 2001-02-15 2004-02-10 Advanced Micro Devices, Inc. Cu damascene interconnections using barrier/capping layer
US7087997B2 (en) 2001-03-12 2006-08-08 International Business Machines Corporation Copper to aluminum interlayer interconnect using stud and via liner
US6879046B2 (en) 2001-06-28 2005-04-12 Agere Systems Inc. Split barrier layer including nitrogen-containing portion and oxygen-containing portion
DE10134900B4 (de) * 2001-07-18 2007-03-15 Infineon Technologies Ag Haltevorrichtung mit Diffusionssperrschicht für Halbleitereinrichtungen
KR100458768B1 (ko) * 2002-12-09 2004-12-03 주식회사 하이닉스반도체 반도체 소자의 금속 배선 형성 방법
US7262133B2 (en) * 2003-01-07 2007-08-28 Applied Materials, Inc. Enhancement of copper line reliability using thin ALD tan film to cap the copper line
CN1317745C (zh) * 2003-06-13 2007-05-23 联华电子股份有限公司 形成阻障层的方法与结构
KR100652317B1 (ko) * 2005-08-11 2006-11-29 동부일렉트로닉스 주식회사 반도체 소자의 금속 패드 제조 방법
KR100699859B1 (ko) * 2005-08-11 2007-03-27 삼성전자주식회사 반도체 설비의 캘리브레이션용 기준 웨이퍼
DE102005052001B4 (de) * 2005-10-31 2015-04-30 Advanced Micro Devices, Inc. Halbleiterbauelement mit einem Kontaktpfropfen auf Kupferbasis und ein Verfahren zur Herstellung desselben
DE102007046851B4 (de) * 2007-09-29 2019-01-10 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterstruktur mit einem elektrisch leitfähigen Strukturelement und Verfahren zum Ausbilden einer Halbleiterstruktur
JP2012114233A (ja) * 2010-11-24 2012-06-14 Ulvac Japan Ltd 半導体装置の製造方法
DE102010063294B4 (de) * 2010-12-16 2019-07-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung von Metallisierungssystemen von Halbleiterbauelementen, die eine Kupfer/Silizium-Verbindung als ein Barrierenmaterial aufweisen
US9466524B2 (en) 2012-01-31 2016-10-11 Applied Materials, Inc. Method of depositing metals using high frequency plasma
CN108063117B (zh) * 2016-11-09 2020-12-01 中芯国际集成电路制造(上海)有限公司 互连结构及其形成方法
TW201840903A (zh) * 2016-11-20 2018-11-16 美商應用材料股份有限公司 選擇性沉積無腐蝕金屬觸點之方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992020099A1 (en) * 1991-05-02 1992-11-12 Mitel Corporation Stabilization of the interface between aluminum and titanium nitride
US5466971A (en) * 1992-07-08 1995-11-14 Seiko Epson Corporation Semiconductor device having a multilayer interconnection layer
EP0799903A2 (de) * 1996-04-05 1997-10-08 Applied Materials, Inc. Verfahren zum Sputtern eines Metalls auf ein Substrat und Vorrichtung zur Behandlung von Halbleitern
WO1998019330A1 (en) * 1996-10-29 1998-05-07 Micron Technology, Inc. Doped silicon diffusion barrier region

Family Cites Families (10)

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US4987562A (en) * 1987-08-28 1991-01-22 Fujitsu Limited Semiconductor layer structure having an aluminum-silicon alloy layer
JP2548957B2 (ja) * 1987-11-05 1996-10-30 富士通株式会社 半導体記憶装置の製造方法
JPH0430516A (ja) * 1990-05-28 1992-02-03 Canon Inc 半導体装置及びその製造方法
DE69127347T2 (de) * 1990-11-29 1998-02-05 At & T Corp Verfahren zur Herstellung eines Kontakts für integrierte Schaltungen
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
KR0138305B1 (ko) * 1994-11-30 1998-06-01 김광호 반도체소자 배선형성방법
US5744376A (en) * 1996-04-08 1998-04-28 Chartered Semiconductor Manufacturing Pte, Ltd Method of manufacturing copper interconnect with top barrier layer
US5814557A (en) * 1996-05-20 1998-09-29 Motorola, Inc. Method of forming an interconnect structure
KR100250744B1 (ko) * 1996-06-21 2000-05-01 김영환 반도체 소자의 폴리사이드층 형성 방법
US5989623A (en) * 1997-08-19 1999-11-23 Applied Materials, Inc. Dual damascene metallization

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992020099A1 (en) * 1991-05-02 1992-11-12 Mitel Corporation Stabilization of the interface between aluminum and titanium nitride
US5466971A (en) * 1992-07-08 1995-11-14 Seiko Epson Corporation Semiconductor device having a multilayer interconnection layer
EP0799903A2 (de) * 1996-04-05 1997-10-08 Applied Materials, Inc. Verfahren zum Sputtern eines Metalls auf ein Substrat und Vorrichtung zur Behandlung von Halbleitern
WO1998019330A1 (en) * 1996-10-29 1998-05-07 Micron Technology, Inc. Doped silicon diffusion barrier region

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"COPPER MULTILEVEL INTERCONNECTIONS", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 33, no. 11, 1 April 1991 (1991-04-01), pages 299/300, XP000110405 *
PRICE D T ET AL: "Damascene copper interconnects with polymer ILDs", THIN SOLID FILMS, vol. 308-309, no. 1-4, 31 October 1997 (1997-10-31), pages 523-528, XP004110329 *

Also Published As

Publication number Publication date
GB2341484B (en) 2000-12-06
JPH11260917A (ja) 1999-09-24
JP3184159B2 (ja) 2001-07-09
US6025264A (en) 2000-02-15
FR2774809A1 (fr) 1999-08-13
GB9819997D0 (en) 1998-11-04
GB2341484A (en) 2000-03-15
FR2774809B1 (fr) 2002-07-12
DE19844451A1 (de) 1999-08-26

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