MX9306826A - Aparato de seleccion automatica de reloj de prueba. - Google Patents

Aparato de seleccion automatica de reloj de prueba.

Info

Publication number
MX9306826A
MX9306826A MX9306826A MX9306826A MX9306826A MX 9306826 A MX9306826 A MX 9306826A MX 9306826 A MX9306826 A MX 9306826A MX 9306826 A MX9306826 A MX 9306826A MX 9306826 A MX9306826 A MX 9306826A
Authority
MX
Mexico
Prior art keywords
clock signal
mode
test
clock
test clock
Prior art date
Application number
MX9306826A
Other languages
English (en)
Inventor
David Lawrence Albean
John William Gyurek
Christopher Dale Duncan
Original Assignee
Thomson Consumer Electronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Consumer Electronics filed Critical Thomson Consumer Electronics
Publication of MX9306826A publication Critical patent/MX9306826A/es

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31701Arrangements for setting the Unit Under Test [UUT] in a test mode
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318328Generation of test inputs, e.g. test vectors, patterns or sequences for delay tests
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30Marginal testing, e.g. by varying supply voltage
    • G01R31/3016Delay or race condition test, e.g. race hazard test
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922Timing generation or clock distribution

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Un circuito integrado (IC 100) incluye circuitos para generar una señal dereloj (CLOCK) durante un modo normal de operación y durante un modo deoperación de prueba. Durante el modo normal, la señal de reloj de entradaes retardada mediante un corrector de distorsión (135). En el modo deprueba, una señal de reloj de prueba de entrada (TEST CLOCK) deriva elcorrector de distorsión por medio de un selector (150) de fuente de señalde reloj. El selector de fuente de señal de reloj es controladoautomáticamente mediante un detector de modo (140) que responde a lasseñales de reloj de entrada, para determinar el modo de operación de CI.
MX9306826A 1992-11-03 1993-11-03 Aparato de seleccion automatica de reloj de prueba. MX9306826A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US97118392A 1992-11-03 1992-11-03

Publications (1)

Publication Number Publication Date
MX9306826A true MX9306826A (es) 1995-01-31

Family

ID=25518032

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9306826A MX9306826A (es) 1992-11-03 1993-11-03 Aparato de seleccion automatica de reloj de prueba.

Country Status (9)

Country Link
US (1) US5517109A (es)
EP (1) EP0596435A1 (es)
JP (1) JPH06201788A (es)
KR (1) KR940012799A (es)
CN (1) CN1095872A (es)
MX (1) MX9306826A (es)
MY (1) MY109842A (es)
SG (1) SG92594A1 (es)
TW (1) TW255052B (es)

Families Citing this family (25)

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GB2315347B (en) * 1993-08-23 1998-04-01 Advanced Risc Mach Ltd Testing integrated circuits
US5982188A (en) * 1994-07-29 1999-11-09 Stmicroelectronics, Inc. Test mode control circuit of an integrated circuit device
US5614838A (en) * 1995-11-03 1997-03-25 International Business Machines Corporation Reduced power apparatus and method for testing high speed components
DE19615745A1 (de) * 1996-04-20 1997-10-23 Philips Patentverwaltung Meßschaltung
JPH09318704A (ja) * 1996-05-30 1997-12-12 Ando Electric Co Ltd Ic試験装置
US6259674B1 (en) 1998-07-30 2001-07-10 Siemens Information And Communication Networks, Inc. Device and method for automatic initialization of a multi-mode interface controller
US6760857B1 (en) * 2000-02-18 2004-07-06 Rambus Inc. System having both externally and internally generated clock signals being asserted on the same clock pin in normal and test modes of operation respectively
JP4980538B2 (ja) * 2000-03-24 2012-07-18 トムソン ライセンシング 集積回路用の制御および検査が可能な発振器装置
US6794919B1 (en) * 2000-09-29 2004-09-21 Intel Corporation Devices and methods for automatically producing a clock signal that follows the master clock signal
SG108251A1 (en) * 2001-05-03 2005-01-28 Ibm Innovative bypass circuit for circuit testing and modification
US7080304B2 (en) * 2002-02-26 2006-07-18 Teradyne, Inc. Technique for programming clocks in automatic test system
US7284143B2 (en) * 2003-12-29 2007-10-16 Texas Instruments Incorporated System and method for reducing clock skew
US7038506B2 (en) * 2004-03-23 2006-05-02 Stmicroelectronics Pvt. Ltd. Automatic selection of an on-chip ancillary internal clock generator upon resetting a digital system
JP2006039693A (ja) * 2004-07-23 2006-02-09 Matsushita Electric Ind Co Ltd 半導体装置
US20070200597A1 (en) * 2006-02-28 2007-08-30 Oakland Steven F Clock generator having improved deskewer
WO2010056343A2 (en) * 2008-11-14 2010-05-20 Teradyne, Inc. Fast open circuit detection for open power and ground pins
US8461934B1 (en) * 2010-10-26 2013-06-11 Marvell International Ltd. External oscillator detector
JP2015088876A (ja) 2013-10-30 2015-05-07 セイコーエプソン株式会社 振動素子、振動子、電子デバイス、電子機器及び移動体
JP2015088931A (ja) * 2013-10-30 2015-05-07 セイコーエプソン株式会社 発振回路、発振器、発振器の製造方法、電子機器及び移動体
JP6206664B2 (ja) 2013-10-30 2017-10-04 セイコーエプソン株式会社 発振回路、発振器、発振器の製造方法、電子機器及び移動体
JP2015088930A (ja) 2013-10-30 2015-05-07 セイコーエプソン株式会社 発振回路、発振器、発振器の製造方法、電子機器及び移動体
JP6226127B2 (ja) 2013-10-30 2017-11-08 セイコーエプソン株式会社 発振回路、発振器、発振器の製造方法、電子機器及び移動体
JP6344544B2 (ja) * 2013-11-11 2018-06-20 セイコーエプソン株式会社 発振器の製造方法、半導体回路装置の製造方法及び半導体回路装置
JP2015159369A (ja) * 2014-02-21 2015-09-03 アルプス電気株式会社 発振回路及びこれを有する半導体集積回路装置
CN108120917B (zh) * 2016-11-29 2020-05-05 深圳市中兴微电子技术有限公司 测试时钟电路确定方法及装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3675127A (en) * 1970-12-28 1972-07-04 Bell Telephone Labor Inc Gated-clock time measurement apparatus including granularity error elimination
US4293870A (en) * 1980-01-31 1981-10-06 Rca Corporation Circuit arrangement for multiplexing an input function and an output function at a single terminal
US4272777A (en) * 1980-02-08 1981-06-09 Rca Corporation Service switch apparatus
US4365203A (en) * 1981-02-05 1982-12-21 General Electric Company Multi-frequency clock generator with error-free frequency switching
GB8432458D0 (en) * 1984-12-21 1985-02-06 Plessey Co Plc Integrated circuits
US4800564A (en) * 1986-09-29 1989-01-24 International Business Machines Corporation High performance clock system error detection and fault isolation
US5079623A (en) * 1990-04-30 1992-01-07 Thomson Consumer Electronics, Inc. Signal clamp for a dual function input terminal of a "one-chip" television signal processing IC
US5065042A (en) * 1990-08-01 1991-11-12 Vlsi Technology, Inc. Self-configuring clock interface circuit
US5066868A (en) * 1990-08-13 1991-11-19 Thomson Consumer Electronics, Inc. Apparatus for generating phase shifted clock signals
JPH04282913A (ja) * 1991-03-12 1992-10-08 Nec Corp バイパス回路内蔵形半導体集積回路

Also Published As

Publication number Publication date
CN1095872A (zh) 1994-11-30
TW255052B (es) 1995-08-21
EP0596435A1 (en) 1994-05-11
SG92594A1 (en) 2002-11-19
US5517109A (en) 1996-05-14
JPH06201788A (ja) 1994-07-22
KR940012799A (ko) 1994-06-24
MY109842A (en) 1997-08-30

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Legal Events

Date Code Title Description
FG Grant or registration
MM Annulment or lapse due to non-payment of fees