DE69808927D1 - Kostengünstiges cmos testgerät mit hoher kanaldichte - Google Patents

Kostengünstiges cmos testgerät mit hoher kanaldichte

Info

Publication number
DE69808927D1
DE69808927D1 DE69808927T DE69808927T DE69808927D1 DE 69808927 D1 DE69808927 D1 DE 69808927D1 DE 69808927 T DE69808927 T DE 69808927T DE 69808927 T DE69808927 T DE 69808927T DE 69808927 D1 DE69808927 D1 DE 69808927D1
Authority
DE
Germany
Prior art keywords
delay
input
output
stage
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69808927T
Other languages
English (en)
Other versions
DE69808927T2 (de
Inventor
Ronald A Sartschev
Gerald F Muething Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Publication of DE69808927D1 publication Critical patent/DE69808927D1/de
Application granted granted Critical
Publication of DE69808927T2 publication Critical patent/DE69808927T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00065—Variable delay controlled by a digital setting by current control, e.g. by parallel current control transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H03K2005/00208—Layout of the delay element using FET's using differential stages
DE69808927T 1997-08-05 1998-07-22 Kostengünstiges cmos testgerät mit hoher kanaldichte Expired - Fee Related DE69808927T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/906,532 US6073259A (en) 1997-08-05 1997-08-05 Low cost CMOS tester with high channel density
PCT/US1998/015256 WO1999008125A1 (en) 1997-08-05 1998-07-22 Low cost cmos tester with high channel density

Publications (2)

Publication Number Publication Date
DE69808927D1 true DE69808927D1 (de) 2002-11-28
DE69808927T2 DE69808927T2 (de) 2003-08-14

Family

ID=25422613

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69830521T Expired - Fee Related DE69830521T2 (de) 1997-08-05 1998-07-22 Automatisches Schaltkreisprüfgerät für Halbleitervorrichtungen
DE69808927T Expired - Fee Related DE69808927T2 (de) 1997-08-05 1998-07-22 Kostengünstiges cmos testgerät mit hoher kanaldichte

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69830521T Expired - Fee Related DE69830521T2 (de) 1997-08-05 1998-07-22 Automatisches Schaltkreisprüfgerät für Halbleitervorrichtungen

Country Status (7)

Country Link
US (1) US6073259A (de)
EP (3) EP1146641A1 (de)
JP (1) JP4301728B2 (de)
KR (1) KR100600038B1 (de)
CN (1) CN1249447C (de)
DE (2) DE69830521T2 (de)
WO (1) WO1999008125A1 (de)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7564283B1 (en) 1998-06-22 2009-07-21 Xilinx, Inc. Automatic tap delay calibration for precise digital phase shift
US6820234B2 (en) 1998-06-29 2004-11-16 Acuid Limited Skew calibration means and a method of skew calibration
AU9654198A (en) * 1998-06-29 2000-01-17 Iliya Valeryevich Klochkov A skew calibration means and a method of skew calibration
US6853181B1 (en) * 2003-12-31 2005-02-08 Teradyne, Inc. Silicon-on-insulator channel architecture for automatic test equipment
US6363507B1 (en) * 1998-10-19 2002-03-26 Teradyne, Inc. Integrated multi-channel analog test instrument architecture providing flexible triggering
JP4363716B2 (ja) * 1999-06-25 2009-11-11 株式会社東芝 Ｌｓｉの配線構造の設計方法
US6594797B1 (en) * 2000-03-09 2003-07-15 Xilinx, Inc. Methods and circuits for precise edge placement of test signals
US6404218B1 (en) * 2000-04-24 2002-06-11 Advantest Corp. Multiple end of test signal for event based test system
WO2002003146A2 (en) * 2000-07-06 2002-01-10 Igor Anatolievich Abrosimov Interface device with stored data on transmission lines characteristics
US6356127B1 (en) * 2001-01-10 2002-03-12 Adc Telecommunications, Inc. Phase locked loop
JP4008200B2 (ja) * 2001-01-16 2007-11-14 株式会社デンソー フィルタ機能を有する信号レベル検出方法及び装置
JP3619466B2 (ja) * 2001-03-27 2005-02-09 松下電器産業株式会社 半導体装置
CN1293387C (zh) * 2001-05-11 2007-01-03 株式会社鼎新 支持多虚拟逻辑测试仪的半导体测试系统
US6653879B2 (en) * 2001-05-25 2003-11-25 Infineon Technologies Ag Method and system for managing a pulse width of a signal pulse
US6792374B2 (en) * 2001-10-30 2004-09-14 Micron Technology, Inc. Apparatus and method for determining effect of on-chip noise on signal propagation
US6868047B2 (en) * 2001-12-12 2005-03-15 Teradyne, Inc. Compact ATE with time stamp system
US6774694B1 (en) 2001-12-26 2004-08-10 Analog Devices, Inc. Timing vernier architecture for generating high speed, high accuracy timing edges
US6934896B2 (en) * 2001-12-31 2005-08-23 Advantest Corp. Time shift circuit for functional and AC parametric test
US6885961B2 (en) * 2002-02-28 2005-04-26 Teradyne, Inc. Hybrid tester architecture
US6971045B1 (en) 2002-05-20 2005-11-29 Cyress Semiconductor Corp. Reducing tester channels for high pinout integrated circuits
TW558872B (en) * 2002-05-21 2003-10-21 Via Tech Inc Delay-locked loop device and method for generating clock signal
US6999547B2 (en) 2002-11-25 2006-02-14 International Business Machines Corporation Delay-lock-loop with improved accuracy and range
US7266739B2 (en) * 2003-05-07 2007-09-04 Credence Systems Solutions Systems and methods associated with test equipment
US7242257B1 (en) 2003-05-07 2007-07-10 Credence Systems Corporation Calibration-associated systems and methods
TWI316607B (en) * 2003-05-21 2009-11-01 Advantest Corp Electric source device, test device and power supply voltage stabilizer
US20050083095A1 (en) * 2003-10-16 2005-04-21 Tsvika Kurts Adaptive input/output buffer and methods thereof
US7081789B2 (en) * 2003-12-24 2006-07-25 Telefonaktiebolaget Lm Erisson (Publ) Switched capacitor circuit compensation apparatus and method
SG113006A1 (en) * 2004-01-04 2005-07-28 Teradyne Inc Silicon-on-insulator channel architecture of automatic test equipment
US7157951B1 (en) * 2004-04-30 2007-01-02 Xilinx, Inc. Digital clock manager capacitive trim unit
US7149145B2 (en) * 2004-07-19 2006-12-12 Micron Technology, Inc. Delay stage-interweaved analog DLL/PLL
US7088163B1 (en) * 2004-09-24 2006-08-08 National Semiconductor Corporation Circuit for multiplexing a tapped differential delay line to a single output
US20060095221A1 (en) * 2004-11-03 2006-05-04 Teradyne, Inc. Method and apparatus for controlling variable delays in electronic circuitry
US7560947B2 (en) 2005-09-28 2009-07-14 Teradyne, Inc. Pin electronics driver
US7502974B2 (en) * 2006-02-22 2009-03-10 Verigy (Singapore) Pte. Ltd. Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets
US20080238516A1 (en) * 2007-03-30 2008-10-02 Teradyne, Inc. Timing interpolator with improved linearity
US7786718B2 (en) * 2007-12-31 2010-08-31 Teradyne, Inc. Time measurement of periodic signals
US8050148B2 (en) * 2008-07-03 2011-11-01 Texas Instruments Incorporated Flash time stamp apparatus
US9442148B2 (en) 2011-07-15 2016-09-13 Teradyne, Inc. ATE to detect signal characteristics of a DUT
US10120008B2 (en) 2013-08-29 2018-11-06 Keysight Technologies, Inc. Method and apparatus for estimating the noise introduced by a device
US9279857B2 (en) 2013-11-19 2016-03-08 Teradyne, Inc. Automated test system with edge steering
US10756829B1 (en) 2019-12-03 2020-08-25 Teradyne, Inc. Determining error vector magnitude using cross-correlation
US11381225B1 (en) * 2021-05-19 2022-07-05 Nanya Technology Corporation Single ended receiver
CN117097353A (zh) 2022-05-11 2023-11-21 莱特普茵特公司 校正误差矢量幅度测量值
CN117478250A (zh) 2022-07-21 2024-01-30 莱特普茵特公司 校正误差矢量幅度测量值
KR102654686B1 (ko) 2023-11-14 2024-04-04 정강배 다중 롤러를 활용한 척추 마사지용 장치

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3996481A (en) * 1974-11-19 1976-12-07 International Business Machines Corporation FET load gate compensator
US3970875A (en) * 1974-11-21 1976-07-20 International Business Machines Corporation LSI chip compensator for process parameter variations
JPS5772429A (en) * 1980-10-22 1982-05-06 Toshiba Corp Semiconductor integrated circuit device
JPS5832178A (ja) * 1981-08-19 1983-02-25 Advantest Corp Ｉｃテスタ
US4513427A (en) * 1982-08-30 1985-04-23 Xerox Corporation Data and clock recovery system for data communication controller
JPS5972814A (ja) * 1982-10-20 1984-04-24 Sanyo Electric Co Ltd 遅延回路
US4514647A (en) * 1983-08-01 1985-04-30 At&T Bell Laboratories Chipset synchronization arrangement
US4584695A (en) * 1983-11-09 1986-04-22 National Semiconductor Corporation Digital PLL decoder
US4641048A (en) * 1984-08-24 1987-02-03 Tektronix, Inc. Digital integrated circuit propagation delay time controller
US4663541A (en) * 1985-03-18 1987-05-05 Environmental Research Institute Of Michigan Phase-shift stabilized frequency multiplier
JPH01161916A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 半導体集積回路
US4902986B1 (en) * 1989-01-30 1998-09-01 Credence Systems Corp Phased locked loop to provide precise frequency and phase tracking of two signals
JP2831780B2 (ja) * 1990-02-02 1998-12-02 株式会社アドバンテスト Ｉｃ試験装置
US5099196A (en) * 1990-11-09 1992-03-24 Dell Usa Corporation On-chip integrated circuit speed selection
US5097208A (en) * 1990-12-05 1992-03-17 Altera Corporation Apparatus and method for measuring gate delays in integrated circuit wafers
US5317183A (en) * 1991-09-03 1994-05-31 International Business Machines Corporation Substrate noise coupling reduction for VLSI applications with mixed analog and digital circuitry
US5179303A (en) * 1991-10-24 1993-01-12 Northern Telecom Limited Signal delay apparatus employing a phase locked loop
US5146121A (en) * 1991-10-24 1992-09-08 Northern Telecom Limited Signal delay apparatus employing a phase locked loop
US5243227A (en) * 1991-11-01 1993-09-07 Hewlett-Packard Company Fine/coarse wired-or tapped delay line
US5214680A (en) * 1991-11-01 1993-05-25 Hewlett-Packard Company CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration
US5283631A (en) * 1991-11-01 1994-02-01 Hewlett-Packard Co. Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations
US5233637A (en) * 1991-11-01 1993-08-03 Hewlett-Packard Company System for generating an analog regulating voltage
JP2688035B2 (ja) * 1992-02-14 1997-12-08 テキサス インスツルメンツ インコーポレイテッド 温度補償回路及び動作方法
US5406198A (en) * 1992-06-05 1995-04-11 Hitachi, Ltd. Digital circuitry apparatus
US5256964A (en) * 1992-07-31 1993-10-26 International Business Machines Corporation Tester calibration verification device
US5365130A (en) * 1992-08-07 1994-11-15 Vlsi Technology, Inc. Self-compensating output pad for an integrated circuit and method therefor
US5336940A (en) * 1992-08-07 1994-08-09 Vlsi Technology, Inc. Delay-compensated output pad for an integrated circuit and method therefor
US5384541A (en) * 1993-03-05 1995-01-24 Hewlett-Packard Company Precision timed delay measurement using phaselocked CW technique
US5428626A (en) * 1993-10-18 1995-06-27 Tektronix, Inc. Timing analyzer for embedded testing
US5440514A (en) * 1994-03-08 1995-08-08 Motorola Inc. Write control for a memory using a delay locked loop
US5491673A (en) * 1994-06-02 1996-02-13 Advantest Corporation Timing signal generation circuit
US5475255A (en) * 1994-06-30 1995-12-12 Motorola Inc. Circuit die having improved substrate noise isolation
US5486783A (en) * 1994-10-31 1996-01-23 At&T Corp. Method and apparatus for providing clock de-skewing on an integrated circuit board
JP3499051B2 (ja) * 1995-06-22 2004-02-23 株式会社アドバンテスト タイミング信号発生回路
US6469493B1 (en) * 1995-08-01 2002-10-22 Teradyne, Inc. Low cost CMOS tester with edge rate compensation
DE69502827T2 (de) * 1995-08-10 1998-10-15 Hewlett Packard Gmbh Elektronischer Schaltungs- oder Kartenprüfer und Verfahren zur Prüfung einer elektronischen Vorrichtung
US5689515A (en) * 1996-04-26 1997-11-18 Teradyne, Inc. High speed serial data pin for automatic test equipment

Also Published As

Publication number Publication date
CN1266496A (zh) 2000-09-13
WO1999008125A1 (en) 1999-02-18
EP1260822A2 (de) 2002-11-27
EP1000364A1 (de) 2000-05-17
KR20010022616A (ko) 2001-03-26
DE69808927T2 (de) 2003-08-14
EP1000364B1 (de) 2002-10-23
KR100600038B1 (ko) 2006-07-13
JP4301728B2 (ja) 2009-07-22
DE69830521D1 (de) 2005-07-14
EP1146641A1 (de) 2001-10-17
EP1260822B1 (de) 2005-06-08
DE69830521T2 (de) 2006-03-16
EP1260822A3 (de) 2003-06-25
JP2001512838A (ja) 2001-08-28
CN1249447C (zh) 2006-04-05
US6073259A (en) 2000-06-06

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