DE3587686T2 - Verfahren zum einstellen elektronischer schaltungen. - Google Patents

Verfahren zum einstellen elektronischer schaltungen.

Info

Publication number
DE3587686T2
DE3587686T2 DE85902163T DE3587686T DE3587686T2 DE 3587686 T2 DE3587686 T2 DE 3587686T2 DE 85902163 T DE85902163 T DE 85902163T DE 3587686 T DE3587686 T DE 3587686T DE 3587686 T2 DE3587686 T2 DE 3587686T2
Authority
DE
Germany
Prior art keywords
pct
melt
cut
electronic circuit
connection wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE85902163T
Other languages
English (en)
Other versions
DE3587686D1 (de
Inventor
Tsunenobu Ujihara
Takamichi Mitsuhashi
Takehiko Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of DE3587686D1 publication Critical patent/DE3587686D1/de
Publication of DE3587686T2 publication Critical patent/DE3587686T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N17/00—Diagnosis, testing or measuring for television systems or their details
    • H04N17/04—Diagnosis, testing or measuring for television systems or their details for receivers
DE85902163T 1984-05-10 1985-05-09 Verfahren zum einstellen elektronischer schaltungen. Expired - Fee Related DE3587686T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59093729A JPS60236585A (ja) 1984-05-10 1984-05-10 電子回路の調整方法
PCT/JP1985/000261 WO1985005510A1 (en) 1984-05-10 1985-05-09 Method of adjusting electronic circuits

Publications (2)

Publication Number Publication Date
DE3587686D1 DE3587686D1 (de) 1994-01-27
DE3587686T2 true DE3587686T2 (de) 1994-04-07

Family

ID=14090496

Family Applications (1)

Application Number Title Priority Date Filing Date
DE85902163T Expired - Fee Related DE3587686T2 (de) 1984-05-10 1985-05-09 Verfahren zum einstellen elektronischer schaltungen.

Country Status (7)

Country Link
US (1) US4689550A (de)
EP (1) EP0182913B1 (de)
JP (1) JPS60236585A (de)
KR (1) KR860700191A (de)
AT (1) ATE98825T1 (de)
DE (1) DE3587686T2 (de)
WO (1) WO1985005510A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2577897B2 (ja) * 1986-10-31 1997-02-05 日本テキサス・インスツルメンツ 株式会社 定電圧電源回路
US4978904A (en) * 1987-12-15 1990-12-18 Gazelle Microcircuits, Inc. Circuit for generating reference voltage and reference current
US4970415A (en) * 1989-07-18 1990-11-13 Gazelle Microcircuits, Inc. Circuit for generating reference voltages and reference currents
JP2601933B2 (ja) * 1990-04-13 1997-04-23 株式会社東芝 固体撮像装置
US5780918A (en) * 1990-05-22 1998-07-14 Seiko Epson Corporation Semiconductor integrated circuit device having a programmable adjusting element in the form of a fuse mounted on a margin of the device and a method of manufacturing the same
JPH04373148A (ja) * 1991-06-21 1992-12-25 Nippon Steel Corp 半導体装置のヒューズ構造
US5410186A (en) * 1991-12-19 1995-04-25 International Business Machines Company Programmable digital to analog converter
US5367202A (en) * 1992-11-06 1994-11-22 National Semiconductor Corporation Voltage reference ladder having improved linearity
JPH10135756A (ja) * 1996-10-31 1998-05-22 Mitsumi Electric Co Ltd 回路体における回路特性の調整方法
JP3398564B2 (ja) * 1997-04-11 2003-04-21 富士通株式会社 半導体装置
US6822345B2 (en) * 2002-04-09 2004-11-23 Sun Microsystems, Inc. Chip/package resonance damping using controlled package series resistance

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3656115A (en) * 1971-04-19 1972-04-11 Bunker Ramo Fusible link matrix for programmable networks
DE2256688B2 (de) * 1972-11-18 1976-05-06 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zum auftrennen von leiterbahnen auf integrierten schaltkreisen
US4016483A (en) * 1974-06-27 1977-04-05 Rudin Marvin B Microminiature integrated circuit impedance device including weighted elements and contactless switching means for fixing the impedance at a preselected value
JPS529850A (en) * 1975-07-15 1977-01-25 Oki Electric Ind Co Ltd Semiifixed electron variable resistor
US4150366A (en) * 1976-09-01 1979-04-17 Motorola, Inc. Trim network for monolithic circuits and use in trimming a d/a converter
US4201970A (en) * 1978-08-07 1980-05-06 Rca Corporation Method and apparatus for trimming resistors
US4412241A (en) * 1980-11-21 1983-10-25 National Semiconductor Corporation Multiple trim structure

Also Published As

Publication number Publication date
US4689550A (en) 1987-08-25
EP0182913A4 (de) 1988-01-28
WO1985005510A1 (en) 1985-12-05
DE3587686D1 (de) 1994-01-27
KR860700191A (ko) 1986-03-31
EP0182913A1 (de) 1986-06-04
ATE98825T1 (de) 1994-01-15
EP0182913B1 (de) 1993-12-15
JPS60236585A (ja) 1985-11-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee