MX2009012806A - Receptor de entrada ajustable para interfaz de alta velocidad y baja potencia. - Google Patents

Receptor de entrada ajustable para interfaz de alta velocidad y baja potencia.

Info

Publication number
MX2009012806A
MX2009012806A MX2009012806A MX2009012806A MX2009012806A MX 2009012806 A MX2009012806 A MX 2009012806A MX 2009012806 A MX2009012806 A MX 2009012806A MX 2009012806 A MX2009012806 A MX 2009012806A MX 2009012806 A MX2009012806 A MX 2009012806A
Authority
MX
Mexico
Prior art keywords
receiver
vref
input receiver
wide
range
Prior art date
Application number
MX2009012806A
Other languages
English (en)
Inventor
Chang Ki Kwon
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2009012806A publication Critical patent/MX2009012806A/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0021—Modifications of threshold
    • H03K19/0027—Modifications of threshold in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Dram (AREA)
  • Amplifiers (AREA)

Abstract

Se describe un receptor de entrada pseudodiferencial el cual está configurado para soportar un amplio rango de voltaje de referencia Vref y un amplio rango de interfaz de frecuencia sin terminación paralela; las ejecuciones de receptor pseudo-diferencial aquí descritas son muy eficientes en términos de área, potencia y rendimiento; aquí se describe un receptor de entrada con Vref ajustable de amplio rango de frecuencia; el receptor se puede configurar con un FET PMOS auxiliar de monitoreo de Vref o un FET PMOS auxiliar apilado habilitado para permitir que el receptor funcione a Vref=0V tal como un receptor CMOS convencional; el receptor también se puede configurar con un FET NMOS auxiliar de monitoreo de Vref para permitir que un receptor de entrada basado en Vref funcione con programabilidad en corrientes de polarización y punto de disparo a Vref=(0.5~0.7)Vdd, dependiendo de la relación de la impedancia del accionador de salida y la impedancia de terminación de encendido/apagado de pastilla paralela.
MX2009012806A 2007-05-31 2008-05-28 Receptor de entrada ajustable para interfaz de alta velocidad y baja potencia. MX2009012806A (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US94122807P 2007-05-31 2007-05-31
US12/125,760 US8502566B2 (en) 2007-05-31 2008-05-22 Adjustable input receiver for low power high speed interface
PCT/US2008/064968 WO2008150794A1 (en) 2007-05-31 2008-05-28 Adjustable input receiver for low power high speed interface

Publications (1)

Publication Number Publication Date
MX2009012806A true MX2009012806A (es) 2009-12-15

Family

ID=39683717

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2009012806A MX2009012806A (es) 2007-05-31 2008-05-28 Receptor de entrada ajustable para interfaz de alta velocidad y baja potencia.

Country Status (14)

Country Link
US (1) US8502566B2 (es)
EP (1) EP2156559B1 (es)
JP (1) JP5384484B2 (es)
KR (1) KR101123599B1 (es)
CN (1) CN101682327B (es)
AU (1) AU2008260248B2 (es)
BR (1) BRPI0812551A2 (es)
CA (1) CA2686967C (es)
HK (1) HK1138951A1 (es)
IL (1) IL201956A (es)
MX (1) MX2009012806A (es)
RU (1) RU2468509C2 (es)
TW (1) TWI375407B (es)
WO (1) WO2008150794A1 (es)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102792380B (zh) * 2009-12-30 2015-11-25 美光科技公司 控制时钟输入缓冲器
KR101796116B1 (ko) 2010-10-20 2017-11-10 삼성전자 주식회사 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법
KR102171262B1 (ko) 2013-12-26 2020-10-28 삼성전자 주식회사 입력 버퍼와 입력 버퍼를 포함하는 플래쉬 메모리 장치

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1256165A1 (ru) * 1985-03-20 1986-09-07 Организация П/Я В-8466 Преобразователь уровней (его варианты)
DE4127212A1 (de) 1991-08-16 1993-02-18 Licentia Gmbh Schaltungsanordnung zur pegelumsetzung
RU2004073C1 (ru) * 1991-10-28 1993-11-30 Научно-производственный кооператив "Аксон" Преобразователь уровн напр жени
US5687330A (en) 1993-06-18 1997-11-11 Digital Equipment Corporation Semiconductor process, power supply and temperature compensated system bus integrated interface architecture with precision receiver
US5461330A (en) * 1993-06-18 1995-10-24 Digital Equipment Corporation Bus settle time by using previous bus state to condition bus at all receiving locations
US5831472A (en) * 1997-03-31 1998-11-03 Adaptec, Inc. Integrated circuit design for single ended receiver margin tracking
KR100327658B1 (ko) * 1998-06-29 2002-08-13 주식회사 하이닉스반도체 데이타입력버퍼
GB2340682B (en) 1998-08-10 2003-11-05 Sgs Thomson Microelectronics Variable threshold inverter
US6169424B1 (en) * 1998-11-03 2001-01-02 Intel Corporation Self-biasing sense amplifier
US6392453B1 (en) * 2001-06-20 2002-05-21 Micron Technology, Inc. Differential input buffer bias circuit
US7218151B1 (en) 2002-06-28 2007-05-15 University Of Rochester Domino logic with variable threshold voltage keeper
JP4346015B2 (ja) 2003-06-30 2009-10-14 株式会社リコー 高速コンパレータおよびそれを用いたｄｃ／ｄｃコンバータ
JP4026593B2 (ja) * 2003-12-25 2007-12-26 セイコーエプソン株式会社 受信装置
KR100616501B1 (ko) * 2004-07-27 2006-08-25 주식회사 하이닉스반도체 리시버
JP2006060689A (ja) 2004-08-23 2006-03-02 Kitakyushu Foundation For The Advancement Of Industry Science & Technology 信号受信回路及び信号受信方法
JP4538047B2 (ja) * 2007-12-25 2010-09-08 三菱電機株式会社 電力用素子の故障検出装置

Also Published As

Publication number Publication date
TW200908572A (en) 2009-02-16
JP5384484B2 (ja) 2014-01-08
TWI375407B (en) 2012-10-21
US8502566B2 (en) 2013-08-06
IL201956A (en) 2014-06-30
EP2156559B1 (en) 2015-11-11
BRPI0812551A2 (pt) 2015-09-29
EP2156559A1 (en) 2010-02-24
KR20100018592A (ko) 2010-02-17
KR101123599B1 (ko) 2012-03-22
CN101682327B (zh) 2013-12-25
CN101682327A (zh) 2010-03-24
WO2008150794A1 (en) 2008-12-11
AU2008260248A1 (en) 2008-12-11
IL201956A0 (en) 2010-06-16
CA2686967C (en) 2014-11-18
AU2008260248B2 (en) 2011-12-22
RU2009149330A (ru) 2011-07-10
JP2010529747A (ja) 2010-08-26
RU2468509C2 (ru) 2012-11-27
HK1138951A1 (en) 2010-09-03
CA2686967A1 (en) 2008-12-11
US20090051391A1 (en) 2009-02-26

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Legal Events

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HH Correction or change in general
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