KR980700681A - 열처리방법 및 반도체 단결정기판(heat treating method and semiconductor single crystal substrate) - Google Patents

열처리방법 및 반도체 단결정기판(heat treating method and semiconductor single crystal substrate)

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Publication number
KR980700681A
KR980700681A KR1019970704185A KR19970704185A KR980700681A KR 980700681 A KR980700681 A KR 980700681A KR 1019970704185 A KR1019970704185 A KR 1019970704185A KR 19970704185 A KR19970704185 A KR 19970704185A KR 980700681 A KR980700681 A KR 980700681A
Authority
KR
South Korea
Prior art keywords
semiconductor single
crystal substrate
single crystal
substrate
reflectance
Prior art date
Application number
KR1019970704185A
Other languages
English (en)
Inventor
히토시 하부카
Original Assignee
와다 다다시
신 에츠 한도타이 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 와다 다다시, 신 에츠 한도타이 가부시키가이샤 filed Critical 와다 다다시
Publication of KR980700681A publication Critical patent/KR980700681A/ko

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67098Apparatus for thermal treatment
    • H01L21/67115Apparatus for thermal treatment mainly by radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67098Apparatus for thermal treatment
    • H01L21/67109Apparatus for thermal treatment mainly by convection

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

열처리시에 반도체 단결정기판의 도달하는 온도를 일정하게 하고, 열처리하는 반도체 단결정기판의 결정품질을 일정하게 할 수 있도록 한 열처리방법을 제공하는 것을 목적으로 한다.
반도체 단결정기판의 적어도 이면측을 직접적으로 복사가열함으로써 열처리하는 방법에 있어서, 반도체 단결정기판 이면의 반사율에 따라서 가열출력을 제어한다.

Description

열처리방법 및 반도체 단결정기판(HEAT TREATING METHOD AND SEMICONDUCTOR SINGLE CRYSTAL SUBSTRATE)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 실험예 1에서 실리콘 단결정기판의 이면의 반사율과 실리콘 단결정기판의 온도변화폭과의 관계를 나타낸 그래프이다.

Claims (6)

  1. 반도체 단결정기판의 적어도 이면측을 직접적으로 복사가열함으로써 열처리하는 방법에 있어서, 반도체 단결정기판 이면의 반사율에 따라서 가열출력을 제어하는 것을 특징으로 하는 열처리방법.
  2. 제1항에 있어서, 매엽식으로 열처리하는 반도체 단결정기판의 이면 반사율을 미리 측정하고, 열처리마다 교체되는 기판의 이면반사율의 증감폭에 비례시켜 가열출력을 증감시키는 것을 특징으로 하는 열처리방법.
  3. 제1항 또는 제2항에 있어서, 상기 반도체 단결정기판이 실리콘이고, 기판의 이면반사율의 증감폭이 최대 33%인 것을 특징으로 하는 열처리방법.
  4. 반도체 단결정기판의 적어도 이면측을 직접적으로 복사가열함으로써 열처리하는 방법에 있어서, 열처리하는 반도체 단결정기판 이면의 반사율을 기판마다 일정하게 유지하는 것을 특징으로 하는 열처리방법.
  5. 반도체 단결정기판의 이면반사율이, 그 기판의 중심부에 비해서 주변부에서 낮은 것을 특징으로 하는 반도체 단결정기판.
  6. 제5항에 있어서, 상기 반도체 단결정기판이 실리콘이고, 기판의 이면반사율이 최대 33%범위내이며, 또 그 반사율이 기판의 반경방향으로 주변을 향해서 감소하는 것을 특징으로 하는 반도체 단결정기판.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970704185A 1996-03-07 1997-01-23 열처리방법 및 반도체 단결정기판(heat treating method and semiconductor single crystal substrate) KR980700681A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP96-49697 1996-03-07
JP8049697A JPH09246202A (ja) 1996-03-07 1996-03-07 熱処理方法および半導体単結晶基板

Publications (1)

Publication Number Publication Date
KR980700681A true KR980700681A (ko) 1998-03-30

Family

ID=12838380

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970704185A KR980700681A (ko) 1996-03-07 1997-01-23 열처리방법 및 반도체 단결정기판(heat treating method and semiconductor single crystal substrate)

Country Status (5)

Country Link
US (1) US5913974A (ko)
EP (1) EP0831519A1 (ko)
JP (1) JPH09246202A (ko)
KR (1) KR980700681A (ko)
WO (1) WO1997033306A1 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19753477A1 (de) * 1997-12-02 1999-06-10 Wacker Siltronic Halbleitermat Verfahren und Heizvorrichtung zum Aufschmelzen von Halbleitermaterial
US6643604B1 (en) 2000-06-30 2003-11-04 Advanced Micro Devices, Inc. System for uniformly heating photoresist
US7015422B2 (en) * 2000-12-21 2006-03-21 Mattson Technology, Inc. System and process for heating semiconductor wafers by optimizing absorption of electromagnetic energy
US6970644B2 (en) * 2000-12-21 2005-11-29 Mattson Technology, Inc. Heating configuration for use in thermal processing chambers
JP4806856B2 (ja) * 2001-03-30 2011-11-02 東京エレクトロン株式会社 熱処理方法及び熱処理装置
US7198671B2 (en) * 2001-07-11 2007-04-03 Matsushita Electric Industrial Co., Ltd. Layered substrates for epitaxial processing, and device
US6849831B2 (en) 2002-03-29 2005-02-01 Mattson Technology, Inc. Pulsed processing semiconductor heating methods using combinations of heating sources
JP2006093302A (ja) * 2004-09-22 2006-04-06 Fujitsu Ltd 急速熱処理装置及び半導体装置の製造方法
JP4712371B2 (ja) 2004-12-24 2011-06-29 富士通セミコンダクター株式会社 半導体装置の製造方法
CN101258387A (zh) * 2005-07-05 2008-09-03 马特森技术公司 确定半导体晶片的光学属性的方法与系统
JP4864396B2 (ja) * 2005-09-13 2012-02-01 株式会社東芝 半導体素子の製造方法、及び、半導体素子の製造装置
FR2914488B1 (fr) * 2007-03-30 2010-08-27 Soitec Silicon On Insulator Substrat chauffage dope

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59169126A (ja) * 1983-03-16 1984-09-25 Ushio Inc 半導体ウエハ−の加熱方法
JPS6027115A (ja) * 1983-07-25 1985-02-12 Ushio Inc 光照射炉による半導体ウエハ−の熱処理法
JPS60137027A (ja) * 1983-12-26 1985-07-20 Ushio Inc 光照射加熱方法
JPH0770474B2 (ja) * 1985-02-08 1995-07-31 株式会社東芝 化合物半導体装置の製造方法
JPH03278524A (ja) * 1990-03-28 1991-12-10 Nec Corp 半導体基板加熱装置

Also Published As

Publication number Publication date
WO1997033306A1 (fr) 1997-09-12
EP0831519A1 (en) 1998-03-25
US5913974A (en) 1999-06-22
JPH09246202A (ja) 1997-09-19

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