KR980005597A - 반도체 장치의 콘택홀 형성방법 - Google Patents

반도체 장치의 콘택홀 형성방법 Download PDF

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Publication number
KR980005597A
KR980005597A KR1019960025388A KR19960025388A KR980005597A KR 980005597 A KR980005597 A KR 980005597A KR 1019960025388 A KR1019960025388 A KR 1019960025388A KR 19960025388 A KR19960025388 A KR 19960025388A KR 980005597 A KR980005597 A KR 980005597A
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South Korea
Prior art keywords
forming
contact
etching
contact hole
semiconductor device
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KR1019960025388A
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English (en)
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KR100223766B1 (ko
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임태정
남기원
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김주용
현대전자산업 주식회사
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Priority to KR1019960025388A priority Critical patent/KR100223766B1/ko
Publication of KR980005597A publication Critical patent/KR980005597A/ko
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Publication of KR100223766B1 publication Critical patent/KR100223766B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야 반도체 장치의 콘택 형성방법.
2. 발명이 해결하려고 하는 기술적 과제 반도체 장치의 콘택 형성방법, 특히 전도층에 대한 고밀도 플라즈마를 사용한 콘택식각으로 전도층이 손상되어 전기적 특성을 저하시켜 소자의 신뢰성을 감소시키는 문제점이 있었음.
3. 발명의 해결방법의 요지 실리콘기판에 대한 콘택식각을 1번의 습식식각으로 하부 전도층에 대한 콘택식각으로 기판 손상을 최대한 방지하고자 하는 방법을 제공함.
4. 발명의 중요한 용도 미세 콘택식각하며 소자 특성을 향상시킬수 있는 방법에 이용됨.

Description

반도체 장치의 콘택홀 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a도 내지 제2c도는 본 발명의 반도체 장치의 콘택홀 형성 단면도.

Claims (3)

  1. 반도체 기판상에 소정의 하부층 및 층간절연막이 형성된 전체구조 상부에 콘택홀 형성하기 위한 포토레지스트패턴을 형성하는 단계: 상기 포토레지스트 패턴을 식각장벽으로하여 상기 층간절연막의 일부가 잔유하도록 건식식각하는 단계: 상기 잔류 포토레지스트를 제거하고 상기 전체구조상에 소정두께로 질화막을 형성하는 단계: 상기 질화막을 전면성식각하여 콘택홀 내 측벽에 질화막 스페이서를 형성하는 단계: 및 상기 콘택홀 내에 소정두께 잔류된 층간절연막을 습식식각으로 제거하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 장치의 콘택홀 형성방법.
  2. 제1항에 있어서, 상기 콘택 영역내의 층간절연막은 약 500Å이하의 두께로 잔류하는 것을 특징으로 하는 반도체 장치의 콘택홀 형성방법.
  3. 제1항에 있어서, 상기 습식식각은 비오이(BOE)용액을 이용하여 수행된 것을 특징으로 하는 반도체 장치의 콘택홀 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960025388A 1996-06-28 1996-06-28 반도체 장치의 콘택홀 형성방법 KR100223766B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960025388A KR100223766B1 (ko) 1996-06-28 1996-06-28 반도체 장치의 콘택홀 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960025388A KR100223766B1 (ko) 1996-06-28 1996-06-28 반도체 장치의 콘택홀 형성방법

Publications (2)

Publication Number Publication Date
KR980005597A true KR980005597A (ko) 1998-03-30
KR100223766B1 KR100223766B1 (ko) 1999-10-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960025388A KR100223766B1 (ko) 1996-06-28 1996-06-28 반도체 장치의 콘택홀 형성방법

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KR100223766B1 (ko) 1999-10-15

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