KR970077329A - 강유전체막 및 그의 형성방법 - Google Patents

강유전체막 및 그의 형성방법 Download PDF

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Publication number
KR970077329A
KR970077329A KR1019960017880A KR19960017880A KR970077329A KR 970077329 A KR970077329 A KR 970077329A KR 1019960017880 A KR1019960017880 A KR 1019960017880A KR 19960017880 A KR19960017880 A KR 19960017880A KR 970077329 A KR970077329 A KR 970077329A
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South Korea
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gas
ferroelectric film
ferroelectric
forming
time
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KR1019960017880A
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KR0183868B1 (ko
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강창석
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김광호
삼성전자 주식회사
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Priority to KR1019960017880A priority Critical patent/KR0183868B1/ko
Priority to JP08219597A priority patent/JP4031552B2/ja
Priority to US08/843,506 priority patent/US6127218A/en
Publication of KR970077329A publication Critical patent/KR970077329A/ko
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Publication of KR0183868B1 publication Critical patent/KR0183868B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/1057—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components comprising charge coupled devices [CCD] or charge injection devices [CID]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

강유전체막을 제1가스로 소정의 시간동안 강유전체막의 일부를 형성하는 제1단계, 및 제2가스를 사용하여 잔여 공정시간 동안 상기 강유전체막의 나머지를 형성하는 제2단계에 걸쳐 형성함으로써, 박막의 표면이 균일하며, 유전률이 높고 누설전류가 감소된 억제된 강유전체막을 얻을 수 있다. 더 나아가, 상기 강유전체막 형성시에 사용되는 가스의 종류에 따라 강유전체의 결정구조를 임의로 조절 할 수 있다.

Description

강유전체막 및 그의 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5a도 내지 제5d도는 본 발명에 따른 강유전체막을 채용한 캐패시터의 제조단계를 나타내는 단면들이다.

Claims (10)

  1. 제1가스로 소정의 시간동안 강유전체막의 일부를 형성하는 제1단계, 및 제2가스를 사용하여 잔여 공정시간 동안 상기 강유전체막의 나머지를 형성하는 제2단계로 구성됨을 특징으로 하는 강유전체막의 증착방법.
  2. 제1항에 있어서, 상기 제2가스는 상기 제1가스를 일부 포함하는 혼합가스임을 특징으로 하는 강유전체막의 증착방법.
  3. 제1항에 있어서, 상기 제1가스는 N2O, O2, O3, NOX중의 어느 하나임을 특징으로 하는 강유전체막의 증착방법.
  4. 제2항에 있어서, 상기 제1가스는 O2이고, 상기 제2가스는 상기 제1가스와 N2O와의 혼합가스임을 특징으로 하는 강유전체막의 증착방법.
  5. 제1항에 있어서, 상기 제1단계에 요구되는 시간은 전체 공정시간의 1 내지 50%임을 특징으로 하는 강유전체막의 증착방법.
  6. 제1항에 있어서, 상기 강유전체는 SrTiO3, (Ba, Sr)TiO3, PbZrTiO3, SrBi2Ta2O9, (Pb, La)(Zr, Ti)O3, Bi4Ti3O12중의 어느 하나임을 특징으로 하는 강유전체막의 증착방법.
  7. 제1가스로 소정의 시간동안 강유전체 박막의 일부를 형성하는 제1단계 및 제2가스를 사용하여 잔여 공정 시간 동안 상기 강유전체 박막의 나머지를 형성하는 제2단계로 구성된 방법에 의해 형성됨을 특징으로 하는 강유전체막.
  8. 제7항에 있어서, 상기 제2가스는 상기 제1가스를 일부 포함하는 혼합가스임을 특징으로 하는 강유전체막.
  9. 제7항에 있어서, 상기 제1가스는 N2O, O2, O3, NOX중의 어느 하나임을 특징으로 하는 강유전체막.
  10. 제7항에 있어서, 상기 제1단계에 요구되는 시간은 전체 공정시간의 1 내지 50%임을 특징으로 하는 강유전체막.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960017880A 1996-05-25 1996-05-25 강유전체막 및 그의 형성방법 KR0183868B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019960017880A KR0183868B1 (ko) 1996-05-25 1996-05-25 강유전체막 및 그의 형성방법
JP08219597A JP4031552B2 (ja) 1996-05-25 1997-03-14 半導体装置の膜形成方法
US08/843,506 US6127218A (en) 1996-05-25 1997-04-16 Methods for forming ferroelectric films using dual deposition steps

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960017880A KR0183868B1 (ko) 1996-05-25 1996-05-25 강유전체막 및 그의 형성방법

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KR970077329A true KR970077329A (ko) 1997-12-12
KR0183868B1 KR0183868B1 (ko) 1999-04-15

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US6838122B2 (en) * 2001-07-13 2005-01-04 Micron Technology, Inc. Chemical vapor deposition methods of forming barium strontium titanate comprising dielectric layers
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US6617178B1 (en) 2002-07-02 2003-09-09 Agilent Technologies, Inc Test system for ferroelectric materials and noble metal electrodes in semiconductor capacitors
US20040023416A1 (en) * 2002-08-05 2004-02-05 Gilbert Stephen R. Method for forming a paraelectric semiconductor device
JP2010267925A (ja) * 2009-05-18 2010-11-25 Hitachi Kokusai Electric Inc 半導体装置の製造方法及び基板処理装置
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KR0183868B1 (ko) 1999-04-15
JPH1041486A (ja) 1998-02-13
JP4031552B2 (ja) 2008-01-09
US6127218A (en) 2000-10-03

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