KR970052841A - 반도체장치 제조방법 - Google Patents

반도체장치 제조방법 Download PDF

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Publication number
KR970052841A
KR970052841A KR1019950058898A KR19950058898A KR970052841A KR 970052841 A KR970052841 A KR 970052841A KR 1019950058898 A KR1019950058898 A KR 1019950058898A KR 19950058898 A KR19950058898 A KR 19950058898A KR 970052841 A KR970052841 A KR 970052841A
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KR
South Korea
Prior art keywords
forming
photoresist
interlayer insulating
substrate
insulating film
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Application number
KR1019950058898A
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English (en)
Inventor
고상기
Original Assignee
문정환
Lg 반도체 주식회사
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Priority to KR1019950058898A priority Critical patent/KR970052841A/ko
Publication of KR970052841A publication Critical patent/KR970052841A/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치 제조방법에 관한 것으로, 반도체 메모리장치의 평탄화공정 및 콘택 공정을 용이하게 행하기 위한 것이다.
본 발명은 반도체기판상에 트랜지스터 및 커패시터로 이루어진 메모리셀 어레이 및 주변회로를 형성하는 공정과, 기판 전면에 층간절연막을 형성하는 공정, 상기 층간절연막위에 포토레지스트를 도포하는 공정, 상기 포토레지스트를 선택적으로 노광 및 현상하여 소정의 콘택 형성을 위한 패턴을 형성하는 공정, 및 상기 포토레지스트패턴을 마스크로 이용한 건식식각에 의해 상기 층간절연막 및 그 하부의 층들을 식각하여 콘택을 형성함과 동시에 기판 표면을 평탄화시키는 공정을 포함하는 반도체장치 제조방법을 제공한다.

Description

반도체장치 제조방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 의한 반도체 메모리장치의 평탄화 및 콘택 형성방법을 도시한 공정 순서도.

Claims (2)

  1. 반도체기판상에 트랜지스터 및 커패시터로 이루어진 메모리셀 어레이 및 주변회로를 형성하는 공정과, 기판 전면에 층간절연막을 형성하는 공정, 상기 층간절연막위에 포토레지스트를 도포하는 공정, 상기 포토레지스트를 선택적으로 노광 및 현상하여 소정의 콘택 형성을 위한 패턴을 형성하는 공정, 및 상기 포토레지스트패턴을 마스크로 이용한 건식식각에 의해 상기 층간절연막 및 그 하부의 층들을 식각하여 콘택을 형성함과 동시에 기판 표면을 평탄화시키는 공정을 포함하는 것을 특징으로 하는 반도 체장치 제조방법.
  2. 제1항에 있어서, 상기 콘택 형성을 위한 건식식각 공정은 상기 층간절연막과 포토레지스트간의 선택비와 상기 포토레지스트의 두께를 적절히 조절하여 행하는 것을 특징으로 하는 반도체장치 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950058898A 1995-12-27 1995-12-27 반도체장치 제조방법 KR970052841A (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950058898A KR970052841A (ko) 1995-12-27 1995-12-27 반도체장치 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950058898A KR970052841A (ko) 1995-12-27 1995-12-27 반도체장치 제조방법

Publications (1)

Publication Number Publication Date
KR970052841A true KR970052841A (ko) 1997-07-29

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ID=66619778

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950058898A KR970052841A (ko) 1995-12-27 1995-12-27 반도체장치 제조방법

Country Status (1)

Country Link
KR (1) KR970052841A (ko)

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