KR970049621A - Serial Time Division Multiplexing (TDM) interrupt handler - Google Patents

Serial Time Division Multiplexing (TDM) interrupt handler Download PDF

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Publication number
KR970049621A
KR970049621A KR1019950067184A KR19950067184A KR970049621A KR 970049621 A KR970049621 A KR 970049621A KR 1019950067184 A KR1019950067184 A KR 1019950067184A KR 19950067184 A KR19950067184 A KR 19950067184A KR 970049621 A KR970049621 A KR 970049621A
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KR
South Korea
Prior art keywords
interrupt
control unit
division multiplexing
time division
tdm
Prior art date
Application number
KR1019950067184A
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Korean (ko)
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KR100208195B1 (en
Inventor
박성영
Original Assignee
정장호
Lg 정보통신주식회사
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Priority to KR1019950067184A priority Critical patent/KR100208195B1/en
Publication of KR970049621A publication Critical patent/KR970049621A/en
Application granted granted Critical
Publication of KR100208195B1 publication Critical patent/KR100208195B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

본 발명은 감시 제어부에 인터럽트 신호를 전송하는 신호라인을 단일선으로 하여 회로설계의 용이성 및 제품코스트 절감을 도모코자 한 직렬 시분할 다중화 인터럽트 처리장치에 관한 것이다.The present invention relates to a serial time division multiplexing interrupt processing apparatus designed to facilitate circuit design and reduce product cost by using a signal line for transmitting an interrupt signal to a monitoring controller as a single line.

종래 기술은 다수개의 인터럽트 신호라인이 가압자부터의 가입자 카드에서 감시 제어부에 해당하는 갯수만큼 개별적으로 연결되기 때문에 가입자 카드의 갯수가 중설되면 이에 수분하여 감시제어부에서 필요로 하는 인터럽트 단자수가 증가되므로 이로 인해 회로 설계가 용이하지 못할뿐만 아니라 제품코스트가 상승되는 문제점이 있었다.In the prior art, since a plurality of interrupt signal lines are individually connected to the monitoring control unit in the subscriber card from the pressurizer, the number of the subscriber cards is neutralized so that the number of interrupt terminals required by the monitoring control unit increases. Due to the circuit design is not easy, but the product cost was raised.

이를 해결코자 하여 본 발명은 감시제어부에 전송되는 인터럽트 신호라인을 단일선으로 하여 감시제어부가 수용할 수 있는 가입자수를 증가시킬 수가 있고 또한 감시제어부 및 마더보드(Mother Board)의 설계가 용이하도록 한 것이다.In order to solve this problem, the present invention can increase the number of subscribers that can be accommodated by the supervisory control unit by using an interrupt signal line transmitted to the supervisory control unit, and also facilitate the design of the supervisory control unit and the motherboard. will be.

Description

직렬 시분할 다중화(TDM) 인터럽트 처리장치Serial Time Division Multiplexing (TDM) interrupt handler

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 인터럽트 처리 장치의 블럭 구성도,3 is a block diagram of an interrupt processing apparatus according to the present invention;

제4도는 제3도의 상세 회로 구성도,4 is a detailed circuit diagram of FIG.

제5도는 본 발명에 의한 직력 TDM 신호 파형도.5 is a linear TDM signal waveform diagram according to the present invention.

Claims (2)

각 가입자부의 동작을 감시하여 총괄적으로 제어하는 감시제어부(1)와, 상기 감시제어부(1)에 어드레스버스(Address Bus), 데이터버스(Data Bus) 및 제어신호(CON)를 통해 연결되는 각 가입자부(21,22,…,2n)의 인터럽트 신호를 단일의 인터럽트 라인(INT)에 의해 전송하도록 구성된 것을 특징으로 하는 직렬 시분할 다중화(TDM) 인터럽트 처리장치.A supervisory control unit 1 which monitors the operation of each subscriber unit and controls it collectively, and is connected to the supervisory control unit 1 through an address bus, a data bus, and a control signal CON. A serial time division multiplexing (TDM) interrupt processing apparatus characterized in that it is configured to transmit an interrupt signal of a subscriber part (2 1 , 2 2 ,..., 2 n ) by a single interrupt line (INT). 제1항에 있어서, 상기 가입자부(21,22,…,2n)는 각각 소정시간(T)마다 생성되는 스타트신호(START)와 소정클럭펄스(CLOCK)를 입력 받아 미리 설정된 인에이블 신호(EN)를 출력하는 타임 슬롯 제어부(210)와, 상기 타임슬롯 제어부(210)에서 출력되는 인에이블 신호(EN)에 따라 제어되어 인터럽트 입력 신호(INTERRUPT)를 버퍼링하여 감시제어부(1)에 출력하는 3상태 버퍼(211)로 구성된 직력 시분할 다중화(TDM)인터럽트 처리장치.2. The subscriber unit (2) according to claim 1, wherein the subscriber unit (2 1 , 2 2 , ..., 2 n ) receives a start signal (START) and a predetermined clock pulse (CLOCK) generated for each predetermined time (T), respectively. It is controlled according to the time slot controller 210 for outputting the signal EN and the enable signal EN output from the time slot controller 210 to buffer the interrupt input signal INTERRUPT to the monitoring controller 1. A serial time division multiplexing (TDM) interrupt processing apparatus comprising a three-state buffer 211 for outputting. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950067184A 1995-12-29 1995-12-29 Serial tdm interrupt processing apparatus KR100208195B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950067184A KR100208195B1 (en) 1995-12-29 1995-12-29 Serial tdm interrupt processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950067184A KR100208195B1 (en) 1995-12-29 1995-12-29 Serial tdm interrupt processing apparatus

Publications (2)

Publication Number Publication Date
KR970049621A true KR970049621A (en) 1997-07-29
KR100208195B1 KR100208195B1 (en) 1999-07-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950067184A KR100208195B1 (en) 1995-12-29 1995-12-29 Serial tdm interrupt processing apparatus

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KR100208195B1 (en) 1999-07-15

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