KR960025129A - Control signal regulator between two processors with different pulse rates - Google Patents

Control signal regulator between two processors with different pulse rates Download PDF

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Publication number
KR960025129A
KR960025129A KR1019940038743A KR19940038743A KR960025129A KR 960025129 A KR960025129 A KR 960025129A KR 1019940038743 A KR1019940038743 A KR 1019940038743A KR 19940038743 A KR19940038743 A KR 19940038743A KR 960025129 A KR960025129 A KR 960025129A
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South Korea
Prior art keywords
control signal
signal
output
synchronization
inputting
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KR1019940038743A
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Korean (ko)
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KR0135008B1 (en
Inventor
설확조
정영삼
김태완
김영철
이상현
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손기락
Lg 정밀주식회사
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Priority to KR1019940038743A priority Critical patent/KR0135008B1/en
Publication of KR960025129A publication Critical patent/KR960025129A/en
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Publication of KR0135008B1 publication Critical patent/KR0135008B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G06F15/17325—Synchronisation; Hardware support therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Communication Control (AREA)
  • Multi Processors (AREA)

Abstract

본 발명은 멀티프로세싱의 고속신호처리를 위한 병렬처리시스템에 관한 것으로, 더욱 상세하게는 펄스속도가 다른 두프로세서간의 제어신호의 타이밍 특서을 조절할 수 있는 제어신호조절장치에 관한 것이다. 이 장치는 상기 제어신호조절부는,상기 링크어뎁터에서 출력하는 데이타출력준비완료 신호를 입력하고, 클럭신호에 동기하여 상기 고속처리프로세서로 8비트의 데이타 입력이 이루어지도록 읽기 시작제어신호를 출력하는 제1수단과; 상기 제1수단의 출력신호에 동기하여 상기 고속처리프로세서에서 출력되는 제2제어신호를 입력하고, 상기 링크어뎁터로 데이타가 읽고 있는 중임을 인식시키기위한 제어신호를 출력하는 제2수단과; 상기 제1수단의 출력신호를 입력하고, 다음 클럭신호에 동기하여 데이타의 읽기완료 제어신호를 출력하는 제3수단과; 상기 제2수단의 출력신호를 입력하고, 상기 제3수단의출력신호에 동기하여,상기 링크어뎁터로 데이타 전송완료 제어신호를 출력하는 제4수단을 구비한 것을 특징으로 한다.The present invention relates to a parallel processing system for high-speed signal processing of multiprocessing, and more particularly, to a control signal adjusting apparatus capable of adjusting timing characteristics of a control signal between two processors having different pulse rates. The apparatus may include: a control signal adjusting unit configured to input a data output ready signal output from the link adapter, and output a read start control signal to input a 8-bit data to the high speed processor in synchronization with a clock signal; 1 means; Second means for inputting a second control signal output from the high speed processor in synchronization with the output signal of the first means, and outputting a control signal for recognizing that data is being read by the link adapter; Third means for inputting an output signal of said first means and outputting a data read completion control signal in synchronization with a next clock signal; And a fourth means for inputting an output signal of the second means and outputting a data transmission completion control signal to the link adapter in synchronization with the output signal of the third means.

Description

펄스속도가 다른 두 프로세서 간에 제어신호조절장치Control signal regulator between two processors with different pulse rates

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 장치를 도시한 블럭도, 제4도는 제3도에 도시된 제어신호조절부의 상세회로도.3 is a block diagram showing an apparatus according to the present invention, and FIG. 4 is a detailed circuit diagram of the control signal adjusting unit shown in FIG.

Claims (1)

고속처리프로세서와 병렬처리프로세서 사이에 상기 고속처리프로세서 보다 펄스속도가 늦은 링크어뎁터를 접속하고, 상기 고속처리프로세서와 링크 어뎁터 사이에 제어신호의 타이밍을 조절하기 위한 제어신호조절부를 접속한 병렬처리시스템에 있어서; 상기 제어신호조절부는, 상기 링크어뎁터에서 출력하는 데이타 출력준비 완료신호를 입력하고, 클럭신호에 동기하여 상기고속처리프로세서로 8비트의 데이타 입력이 이루어지도록읽기시작제어신호를 출력하는 제1수단과; 상기 제1수단의 출력신호에 동기하여 상기 고속처리프로세서에서 출력되는 제2제어신호를 입력하고, 상기 링크어뎁터로 데이타가 읽고 있는 중임을 인식시키기 위한 제어신호를출력하는 제2수단과; 상기 제1수단의 출력신호를 입력하고, 다음 클럭신호에 동기하여 데이타의 읽기완료 제어신호를 출력하는 제3수단과; 상기 제2수단의 출력신호를 입력하고, 상기 제3수단의 출력신호에 동기하여, 상기링크어뎁터로 데이타 전송완료 제어신호를 출력하는 제4수단을 구비한 것을 특징으로 하는 펄스속도가 다른두 프로세서 간에 제어신호조절장치.A parallel processing system between a high speed processor and a parallel processor connected to a link adapter having a slower pulse rate than the high speed processor and a control signal adjusting unit for adjusting timing of a control signal between the high speed processor and the link adapter. To; The control signal adjusting unit may include: first means for inputting a data output preparation completion signal output from the link adapter, and outputting a read start control signal for inputting 8-bit data to the high speed processor in synchronization with a clock signal; ; Second means for inputting a second control signal output from said high speed processor in synchronization with an output signal of said first means, and outputting a control signal for recognizing that data is being read by said link adapter; Third means for inputting an output signal of said first means and outputting a data read completion control signal in synchronization with a next clock signal; And a fourth means for inputting an output signal of the second means and outputting a data transmission completion control signal to the link adapter in synchronization with the output signal of the third means. Control signal control device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038743A 1994-12-29 1994-12-29 Parallel processor system KR0135008B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038743A KR0135008B1 (en) 1994-12-29 1994-12-29 Parallel processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038743A KR0135008B1 (en) 1994-12-29 1994-12-29 Parallel processor system

Publications (2)

Publication Number Publication Date
KR960025129A true KR960025129A (en) 1996-07-20
KR0135008B1 KR0135008B1 (en) 1998-05-15

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KR1019940038743A KR0135008B1 (en) 1994-12-29 1994-12-29 Parallel processor system

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