KR960025131A - Control signal regulator between two processors with different pulse rates - Google Patents

Control signal regulator between two processors with different pulse rates Download PDF

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Publication number
KR960025131A
KR960025131A KR1019940038745A KR19940038745A KR960025131A KR 960025131 A KR960025131 A KR 960025131A KR 1019940038745 A KR1019940038745 A KR 1019940038745A KR 19940038745 A KR19940038745 A KR 19940038745A KR 960025131 A KR960025131 A KR 960025131A
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South Korea
Prior art keywords
control signal
inputting
signal
high speed
output signal
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KR1019940038745A
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Korean (ko)
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KR0135006B1 (en
Inventor
설확조
정영삼
김태완
김영철
이상현
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손기락
Lg 정밀주식회사
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Priority to KR1019940038745A priority Critical patent/KR0135006B1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G06F15/17325—Synchronisation; Hardware support therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Information Transfer Systems (AREA)

Abstract

본 발명은 펄스속도가 다른 두 프로세서 간의 제어신호의 타이밍 특성을 조절할 수 있는 제어신호조절장치에 관한 것이다. 이 장치는 상기 링크 어뎁터에서 출력되는 제1제어신호를 입력하고, 저항과 콘덴서에 의해 결정된 시간동안 펄스신호를출력하는 펄스발생기(60)와; 상기 펄스발생기의 출력신호를 제1입력단자로 입력하고, 출력신호를 상기 고속처리프로세서의 제1제어신호 입력단자로 출력하는 래치회로(65)와; 상기 고속처리프로세서의 제1제어신호에 동기하여 발생되는 프로세서의 제2제어신호를 입력하고, 신호를 출력하는 제1낸드게이트(70)와; 상기 제1낸드게이트의 출력신호와 상기 펄스발생기의 출력신호를 입력하는 제2낸드게이트(73)와; 상기 제2낸드게이트의 출력신호를 입력하고, 출력신호를 상기 래치회로(65)의 제2입력단자로 출력하는 앤드게이트(75)와; 상기 고속처리프로세서의 제2제어신호를 입력하고, 소정시간 동안 상기 링크 어뎁터의 제2제어신호 입력단자로 펄스신호를 출력하는 지연소자로 구성한 것을 특징으로 한다.The present invention relates to a control signal adjusting apparatus capable of adjusting timing characteristics of a control signal between two processors having different pulse rates. The apparatus includes a pulse generator (60) for inputting a first control signal output from the link adapter and outputting a pulse signal for a time determined by a resistor and a capacitor; A latch circuit (65) which inputs an output signal of the pulse generator to a first input terminal and outputs an output signal to a first control signal input terminal of the high speed processor; A first NAND gate 70 for inputting a second control signal of the processor generated in synchronization with the first control signal of the high speed processor and outputting a signal; A second NAND gate 73 for inputting an output signal of the first NAND gate and an output signal of the pulse generator; An AND gate 75 for inputting an output signal of the second NAND gate and outputting an output signal to a second input terminal of the latch circuit 65; And a delay element for inputting a second control signal of the high speed processor and outputting a pulse signal to the second control signal input terminal of the link adapter for a predetermined time.

Description

펄스속도가 다른 두 프로세서 간에 제어신호조절장치Control signal regulator between two processors with different pulse rates

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 장치를 도시한 블럭도, 제4도는 제3도에 도시된 제어신호조절부의 상세회로도.3 is a block diagram showing an apparatus according to the present invention, and FIG. 4 is a detailed circuit diagram of the control signal adjusting unit shown in FIG.

Claims (2)

고속처리프로세서와 병렬처리프로세서 사이에 상기 고속처리프로세서 보다 펄스속도가 늦은 링크 어뎁터를 접속하고, 상기 고속처리프로세서와 링크 어뎁터 사이에 제어신호의 타이밍을 조절하기 위한 제어신호조절부를 접속한 병령처리시스템에 있어서; 상기 제어신호조절부는, 상기 링크 어뎁터에서 출력되는 제1제어신호를 입력하고, 저항과 콘덴서에 의해 결정된 시간동안펄스신호를 출력하는 펄스발생기(60)와; 상기 펄스발생기의 출력신호를 제1입력단자로 입력하고, 출력신호를 상기 고속처리프로세서의 제1제어신호 입력단자로 출력하는 래치회로(65)와; 상기 고속처리프로세서의 제1제어신호에 동기하여 발생되는 프로세서의 제2제어신호를 입력하고, 신호를 출력하는 제1낸드게이트(70)와; 상기 제1낸드게이트의 출력신호와 상기 펄스발생기의 출력신호를 입력하는 제2낸드게이트(73)와; 상기 제2낸드게이트의 출력신호를 입력하고, 출력신호를 상기 래치회로(65)의 제2입력단자로 출력하는 앤드게이트(75)와; 상기 고속처리프로세서의 제2제어신호를 입력하고, 소정시간 동안 상기 링크 어뎁터의 제2제어신호 입력단자로 펄스신호를 출력하는 지연소자로 구성한 것을 특징으로 하는 펄스속도가 다른 두 프로세서 간에 제어신호조절장치.A parallel processing system is connected between a high speed processor and a parallel processor with a link adapter having a slower pulse speed than the high speed processor and a control signal controller for controlling timing of a control signal between the high speed processor and the link adapter. To; The control signal adjusting unit may include a pulse generator 60 inputting a first control signal output from the link adapter and outputting a pulse signal for a time determined by a resistor and a capacitor; A latch circuit (65) which inputs an output signal of the pulse generator to a first input terminal and outputs an output signal to a first control signal input terminal of the high speed processor; A first NAND gate 70 for inputting a second control signal of the processor generated in synchronization with the first control signal of the high speed processor and outputting a signal; A second NAND gate 73 for inputting an output signal of the first NAND gate and an output signal of the pulse generator; An AND gate 75 for inputting an output signal of the second NAND gate and outputting an output signal to a second input terminal of the latch circuit 65; Control signal control between two processors having a different pulse rate, comprising: a delay element for inputting a second control signal of the high speed processor and outputting a pulse signal to a second control signal input terminal of the link adapter for a predetermined time; Device. 제1항에 있어서; 상기 지연소자는, 고속처리프로세서의 제2제어신호를 입력하는 제1플립플롭(63)과, 상기 제1플립플롭의 출력신호를 입력하는 제2플립플롭(67)과, 상기 제1, 2플립플롭의 출력을 입력하는 제3낸드게이트(77)를 포함한 것을 특징으로 하는 펄스속도가 다른 두 프로세서 간에 제어신호조절장치.The method of claim 1; The delay element includes: a first flip flop 63 for inputting a second control signal of a high speed processor; a second flip flop 67 for inputting an output signal of the first flip flop; And a third NAND gate (77) for inputting the output of the flip-flop. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038745A 1994-12-29 1994-12-29 Parallel processor system KR0135006B1 (en)

Priority Applications (1)

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KR1019940038745A KR0135006B1 (en) 1994-12-29 1994-12-29 Parallel processor system

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Application Number Priority Date Filing Date Title
KR1019940038745A KR0135006B1 (en) 1994-12-29 1994-12-29 Parallel processor system

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KR960025131A true KR960025131A (en) 1996-07-20
KR0135006B1 KR0135006B1 (en) 1998-05-15

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