KR970030382A - 반도체 소자 제조방법 - Google Patents

반도체 소자 제조방법 Download PDF

Info

Publication number
KR970030382A
KR970030382A KR1019950041446A KR19950041446A KR970030382A KR 970030382 A KR970030382 A KR 970030382A KR 1019950041446 A KR1019950041446 A KR 1019950041446A KR 19950041446 A KR19950041446 A KR 19950041446A KR 970030382 A KR970030382 A KR 970030382A
Authority
KR
South Korea
Prior art keywords
film
semiconductor device
etching process
bpsg
dry etching
Prior art date
Application number
KR1019950041446A
Other languages
English (en)
Other versions
KR100338091B1 (ko
Inventor
남기원
백인혁
배영헌
이정석
김상익
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950041446A priority Critical patent/KR100338091B1/ko
Publication of KR970030382A publication Critical patent/KR970030382A/ko
Application granted granted Critical
Publication of KR100338091B1 publication Critical patent/KR100338091B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 금속 스텝 커버리지 및 소자의 전기적 특성을 향상시키기 위하여 실리콘기판상에 증착된 임의의 박막을 식각비의 차이를 이용한 건식 및 습식 식각 공정으로 콘택홀을 형성시키는 반도체 소자 제조 방법이 개시된다.

Description

반도체 소자 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a 내지 2d도는 본 발명의 제1 실시예에 따른 반도체 소자 제조방법을 설명하기 위한 도면도.
제3c도는 본 발명의 제2실시예에 따른 반도체 소자 제조방법을 설명하기 위한 단면도.

Claims (5)

  1. 반도체 소자의 제조 방법에 있어서, 실리콘기판상에 BPSG막 및 TEOS막을 증착하고, 패터닝 된 감광막을 마스크를 이용하여 등방성 습식 식각 공정으로 TEOS막 및 BPSG막을 일정한 비율로 소정 깊이 식각하는 단계와, 상기 노출된 잔류 BPSG막을 건식 식각하여, 콘택홀을 형성하는 단계로 이루어진 것을 특징으로 하는 반도체 소자 제조 방법.
  2. 제1항에 있어서, 상기 BPSG 및 TEOS막을 7:3의 두계의 비율로 증착하는 것을 특징으로 하는 반도체 소자 제조 방법.
  3. 반도체 소자의 제조 방법에 있어서, 실리콘기판상에 산화막 및 폴리 실리콘을 순차적으로 증착하고, 패터닝 된 김광막을 마스크로 이용하여 건식 식각공정으로 플리 실리콘층을 식각 하는 단계와, 상기 감광막을 제거한 후, 산화막을 등방성 습식 식각 공정으로 일정한 비율로 소정 깊이 식각하는 단계와, 상기 건식식각공정으로 산화막을 식각하여 콘택홀을 형성하는 단계로 이루어진 것을 특징으로 하는 반도체 소자 제조 방법.
  4. 제3항에 있어서, 상기 산화막상에 폴리 실리콘을 800℃이상의 온도에서 1000Å 내지 2000Å의 두께로 증착하는 것을 특징으로 하는 반도체 소자 제조 방법.
  5. 제3항에 있어서, 상기 건식 식각 공정시 감광막 대신 폴리 실리콘층을 마스크로 이용하는 것을 특징으로 하는 반도체 소자 제조 방법.
KR1019950041446A 1995-11-15 1995-11-15 반도체소자제조방법 KR100338091B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950041446A KR100338091B1 (ko) 1995-11-15 1995-11-15 반도체소자제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950041446A KR100338091B1 (ko) 1995-11-15 1995-11-15 반도체소자제조방법

Publications (2)

Publication Number Publication Date
KR970030382A true KR970030382A (ko) 1997-06-26
KR100338091B1 KR100338091B1 (ko) 2002-11-04

Family

ID=37480071

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950041446A KR100338091B1 (ko) 1995-11-15 1995-11-15 반도체소자제조방법

Country Status (1)

Country Link
KR (1) KR100338091B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240003535A (ko) 2022-07-01 2024-01-09 정민우 중장비용 유압 펌프

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536652A (ja) * 1991-07-29 1993-02-12 Oki Electric Ind Co Ltd スルーホールの形成方法
JPH0745551A (ja) * 1993-07-27 1995-02-14 Matsushita Electron Corp コンタクトホールの形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240003535A (ko) 2022-07-01 2024-01-09 정민우 중장비용 유압 펌프

Also Published As

Publication number Publication date
KR100338091B1 (ko) 2002-11-04

Similar Documents

Publication Publication Date Title
KR950009740B1 (ko) 메모리 캐패시터 제조방법 및 그 구조
JP2519819B2 (ja) コンタクトホ―ルの形成方法
KR970008597A (ko) 원통형 캐패시터의 제조방법
KR970030382A (ko) 반도체 소자 제조방법
KR100248626B1 (ko) 반도체소자의 제조 방법
KR980006092A (ko) 반도체 소자의 소자분리막 제조방법
JP2597424B2 (ja) 半導体装置の製造方法
KR100357174B1 (ko) 반도체소자의 캐패시터 제조방법
KR100328824B1 (ko) 커패시터 제조방법
KR100400763B1 (ko) 반도체소자의 캐패시터 제조방법
KR970000220B1 (ko) 디램(dram)셀 커패시터 제조방법
KR0174645B1 (ko) 커패시터 제조방법
KR100268896B1 (ko) 커패시터및그의제조방법
KR0172249B1 (ko) 반도체소자의 콘택홀 형성방법
KR930008893B1 (ko) 메모리 셀의 캐패시터 제조방법
KR960030327A (ko) 반도체 소자의 콘택홀 형성방법
KR960002739A (ko) 반도체 소자의 필드 산화막 형성방법
KR970052343A (ko) 반도체 소자의 층간 콘택방법
KR20000003342A (ko) 반도체 장치의 자기정렬 콘택홀 형성방법
KR20000028894A (ko) 캐패시터콘택홀을 갖는 반도체장치 제조방법
JPH05114713A (ja) 半導体装置およびその製造方法
KR930020580A (ko) 반도체 소자의 콘택제조방법
KR960026473A (ko) 박막 트랜지스터 제조방법
KR970030404A (ko) 반도체 장치의 층간절연막 평탄화 방법
JPH05304302A (ja) 導電膜のパターン形成方法及びこの方法によって製造した不揮発性半導体記憶装置

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110429

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee