KR970013253A - 반도체 패키지 - Google Patents
반도체 패키지 Download PDFInfo
- Publication number
- KR970013253A KR970013253A KR1019950025657A KR19950025657A KR970013253A KR 970013253 A KR970013253 A KR 970013253A KR 1019950025657 A KR1019950025657 A KR 1019950025657A KR 19950025657 A KR19950025657 A KR 19950025657A KR 970013253 A KR970013253 A KR 970013253A
- Authority
- KR
- South Korea
- Prior art keywords
- package
- semiconductor chip
- terminal
- semiconductor package
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 반도체 패키지에 관한 것으로, 종래의 반도체 패키지는 금속 와이어를 사용하고, 아웃 리드가 외부로 돌출되어 있어 패키지를 박형화시키는데 한계가 있을뿐 아니라 와이어 본딩을 필수적으로 수행하여야 하므로 공정을 단순화하는데 한계가 있는 문제점이 있었다. 본 발명은 반도체 칩(10)의 패드(10a)에 각각 단자핀(11)을 설치하고, 그 단자핀(11)의 상면이 외부로 노출이 되도록 에폭시로 몰딩한 몸체부(12)로 구성하여 종래의 금속 와이어와 아웃 리드를 배제하는데 따른 박형화를 이룰 수 있고, 와이어 본딩 공정을 배제하고 반도체 칩과 단자핀의 연결을 리플로우로 일시에 마칠 수 있도록 함으로써 공정의 단순화에 EK른 원가절감의 효과가 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명 반도체 패키지의 구성을 보인 사시도
제3도는 본 발명 반도체 패키지의 칩을 보인 사시도.
Claims (2)
- 수개의 패드가 형성되어 있는 반도체 칩과, 상기 패드에 각각 대응이 되도록 설치되는 단자핀과, 그 단자핀의 상면이 패키지의 상면에 노출이 되도록 반도체 칩과 단자핀을 포함한 일정면적을 에폭시로 몰딩한 몸체부로 구성된 것을 특징으로 하는 반도체 패키지.
- 제1항에 있어서, 상기 패드의 상면에는 단자핀의 얼라인이 용이하도록 단자홈이 형성되어 있는 것을 특징으로 하는 반도체 패키지.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950025657A KR0152934B1 (ko) | 1995-08-21 | 1995-08-21 | 반도체 패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950025657A KR0152934B1 (ko) | 1995-08-21 | 1995-08-21 | 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970013253A true KR970013253A (ko) | 1997-03-29 |
KR0152934B1 KR0152934B1 (ko) | 1998-10-01 |
Family
ID=19423876
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950025657A KR0152934B1 (ko) | 1995-08-21 | 1995-08-21 | 반도체 패키지 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0152934B1 (ko) |
-
1995
- 1995-08-21 KR KR1019950025657A patent/KR0152934B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0152934B1 (ko) | 1998-10-01 |
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