KR970003879A - Bga i/o 포맷과 2금속 충전된 경로를 구비한 단층 세라믹 기판기술을 사용하는 고성능 디지탈 패키지 - Google Patents

Bga i/o 포맷과 2금속 충전된 경로를 구비한 단층 세라믹 기판기술을 사용하는 고성능 디지탈 패키지 Download PDF

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Publication number
KR970003879A
KR970003879A KR1019960020252A KR19960020252A KR970003879A KR 970003879 A KR970003879 A KR 970003879A KR 1019960020252 A KR1019960020252 A KR 1019960020252A KR 19960020252 A KR19960020252 A KR 19960020252A KR 970003879 A KR970003879 A KR 970003879A
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South Korea
Prior art keywords
integrated circuit
circuit package
digital integrated
thickness
package
Prior art date
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KR1019960020252A
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English (en)
Korean (ko)
Inventor
엘. 그린맨 노먼
엠. 헤르난데즈 조지
피. 라마찬드라 파닉커 엠.
Original Assignee
엘. 그린맨 노먼
서키트 콤포넌츠 인코퍼레이티드
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Publication of KR970003879A publication Critical patent/KR970003879A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
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    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/161—Disposition
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Wire Bonding (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
KR1019960020252A 1995-06-06 1996-06-07 Bga i/o 포맷과 2금속 충전된 경로를 구비한 단층 세라믹 기판기술을 사용하는 고성능 디지탈 패키지 Withdrawn KR970003879A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47109595A 1995-06-06 1995-06-06
US08/471,095 1995-06-06

Publications (1)

Publication Number Publication Date
KR970003879A true KR970003879A (ko) 1997-01-29

Family

ID=23870234

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960020252A Withdrawn KR970003879A (ko) 1995-06-06 1996-06-07 Bga i/o 포맷과 2금속 충전된 경로를 구비한 단층 세라믹 기판기술을 사용하는 고성능 디지탈 패키지

Country Status (6)

Country Link
JP (1) JPH09213829A (enrdf_load_stackoverflow)
KR (1) KR970003879A (enrdf_load_stackoverflow)
DE (1) DE19622650A1 (enrdf_load_stackoverflow)
GB (1) GB2301937A (enrdf_load_stackoverflow)
MX (1) MXPA96002171A (enrdf_load_stackoverflow)
TW (1) TW299487B (enrdf_load_stackoverflow)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6140708A (en) * 1996-05-17 2000-10-31 National Semiconductor Corporation Chip scale package and method for manufacture thereof
US5783866A (en) * 1996-05-17 1998-07-21 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
US6284566B1 (en) 1996-05-17 2001-09-04 National Semiconductor Corporation Chip scale package and method for manufacture thereof
JPH11219984A (ja) * 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
GB9818474D0 (en) * 1998-08-26 1998-10-21 Hughes John E Multi-layer interconnect package for optical devices & standard semiconductor chips
US6198166B1 (en) * 1999-07-01 2001-03-06 Intersil Corporation Power semiconductor mounting package containing ball grid array
DE10010461A1 (de) * 2000-03-03 2001-09-13 Infineon Technologies Ag Vorrichtung zum Verpacken elektronischer Bauteile mittels Spritzgußtechnik
GB2377080B (en) * 2001-09-11 2003-05-07 Sendo Int Ltd Integrated circuit package and printed circuit board arrangement
JP6397806B2 (ja) 2015-09-11 2018-09-26 東芝メモリ株式会社 半導体装置の製造方法および半導体装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
TW272311B (enrdf_load_stackoverflow) * 1994-01-12 1996-03-11 At & T Corp

Also Published As

Publication number Publication date
TW299487B (enrdf_load_stackoverflow) 1997-03-01
DE19622650A1 (de) 1996-12-12
JPH09213829A (ja) 1997-08-15
GB2301937A (en) 1996-12-18
MXPA96002171A (es) 2002-04-19
GB9611726D0 (en) 1996-08-07

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