KR970003879A - High performance digital package using single layer ceramic substrate technology with BGA I / O format and bimetal filled path - Google Patents

High performance digital package using single layer ceramic substrate technology with BGA I / O format and bimetal filled path Download PDF

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Publication number
KR970003879A
KR970003879A KR1019960020252A KR19960020252A KR970003879A KR 970003879 A KR970003879 A KR 970003879A KR 1019960020252 A KR1019960020252 A KR 1019960020252A KR 19960020252 A KR19960020252 A KR 19960020252A KR 970003879 A KR970003879 A KR 970003879A
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South Korea
Prior art keywords
integrated circuit
circuit package
digital integrated
thickness
package
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KR1019960020252A
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Korean (ko)
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엘. 그린맨 노먼
엠. 헤르난데즈 조지
피. 라마찬드라 파닉커 엠.
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엘. 그린맨 노먼
서키트 콤포넌츠 인코퍼레이티드
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Publication of KR970003879A publication Critical patent/KR970003879A/en

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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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  • Engineering & Computer Science (AREA)
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Abstract

소형 밑넓이를 유지하면서 고성능 및 큰 입력/출력(I/O) 능력을 나타내는 디지탈 집적회로 패키지가 개시된다. 이 패키지는 볼 그리드 어레이(BGA)포맷과 2금속 충전되고 정확히 위치된 경로를 갖는 단층 세라믹 기판을 이용한다.A digital integrated circuit package is disclosed that exhibits high performance and large input / output (I / O) capabilities while maintaining a small footprint. The package uses a single-layer ceramic substrate with a ball grid array (BGA) format and a bimetal filled, precisely positioned path.

Description

BGA I/O 포맷과 2금속 충전된 경로를 구비한 단층 세라믹 기판기술을 사용하는 고성능 디지탈 패키지High performance digital package using single layer ceramic substrate technology with BGA I / O format and bimetal filled path

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 일실시예의 분해 사시도.2 is an exploded perspective view of one embodiment of the present invention.

Claims (58)

a) 소정 패턴의 경로를 갖는 단층기판; b) 그들 사이에 전기적 접점을 형성하기 위해 복수의 와이어 본딩패드 및 복수의 플립칩 부착패드중 적어도 하나로부터 복수의 경로를 뻗어 있고, 상기 단층기판상에 모두 배치되어 있는 복수의 트래에스; c) 상기 경로, 트레이스, 와이어본딩 패드, 적어도 하나의 와이어본드 및 적어도 하나의 다이를 환경영향으로부터 보호하기 위해 배치된 적어도 하나의 보호구조물; d) 그위에 상기 적어도 하나의 다이가 배치되는 상기 기판의 제1표면에 대향되는 상기 기판의 제2기판상에 배치되는 복수의 전기 전도성 볼로 구성되어 있는 것을 특징으로 하는 디지탈 집적회로 패키지.a) a single layer substrate having a path of a predetermined pattern; b) a plurality of traces extending in a plurality of paths from at least one of the plurality of wire bonding pads and the plurality of flip chip attachment pads to form electrical contacts therebetween, all disposed on the monolayer substrate; c) at least one protective structure arranged to protect said path, trace, wirebonding pad, at least one wirebond and at least one die from environmental impacts; d) a digital integrated circuit package comprising a plurality of electrically conductive balls disposed on a second substrate of the substrate opposite the first surface of the substrate on which the at least one die is disposed. 제1항에 있어서, 상기 단층은 완전 소결된 세라믹 재료로 이루어진 것을 특징으로 하는 디지탈 집적회로 패키지.The digital integrated circuit package of claim 1, wherein the monolayer is made of a fully sintered ceramic material. 제2항에 있어서, 상기 세라믹재료는 산화알루미늄(Al2O3)재료인 것을 특징으로 하는 디지탈 집적회로 패키지. 3. The digital integrated circuit package of claim 2, wherein the ceramic material is an aluminum oxide (Al 2 O 3 ) material. 제2항에 있어서, 상기 세라믹은 질화알루미늄(AIN)재료인 것을 특징으로 하는 디지탈 집적회로 패키지.3. The digital integrated circuit package of claim 2, wherein the ceramic is an aluminum nitride (AIN) material. 제1항에 있어서, 상기 패턴의 경로는 열전도를 위한 조밀하게 패터닝된 중심부 및 신호/전력을 위한 주변패턴을 포함하는 것을 특징으로 하는 디지탈 집적회로 패키지.The digital integrated circuit package of claim 1, wherein the path of the pattern comprises a densely patterned central portion for thermal conduction and a peripheral pattern for signal / power. 제5항에 있어서, 상기 신호/전력 경로는 약 0.050 내지 0.025인치의 범위에서의 각각의 경로간 열 및 행거리를 유지하는 것을 특징으로 하는 디지탈 집적회로 패키지.6. The digital integrated circuit package of claim 5, wherein the signal / power paths maintain columns and rows between each path in the range of about 0.050 to 0.025 inches. 제5항에 있어서, 상기 신호/전력 경로는 약 0.050인치의 각각의 경로간 열 및 행 거리를 유지하고 열간의 틈새 간격은 약 0.025인치인 것을 특징으로 하는 디지탈 집적회로 패키지.6. The digital integrated circuit package of claim 5, wherein the signal / power path maintains a column and row distance between each path of about 0.050 inches and the gap spacing between the columns is about 0.025 inches. 제1항에 있어서, 상기 트레이스는 접착프로모터, 전류캐리어, 버퍼 및 보호층을 포함한 층으로 된 메탈라이제이션으로 이루어진 것을 특징으로 하는 디지탈 집적회로 패키지.The digital integrated circuit package according to claim 1, wherein the trace is made of a metallization of a layer including an adhesion promoter, a current carrier, a buffer, and a protective layer. 제8항에 있어서, 상기 트레이스의 폭은 약 0.002인치인 것을 특징으로 하는 디지탈 집적회로 패키지.9. The digital integrated circuit package of claim 8 wherein the trace is about 0.002 inches wide. 제1항에 있어서, 상기 와이어 본딩패드는 접착 프로모터, 전류캐리어, 버퍼, 및 보호층을 포함한 층으로 된 메탈라이제이션으로 이루어진 것을 특징으로 하는 디지탈 집적회로 패키지.The digital integrated circuit package of claim 1, wherein the wire bonding pad is formed of a layered metallization including an adhesion promoter, a current carrier, a buffer, and a protective layer. 제1항에 있어서, 상기 경로는 2금속 합성물로 충전되는 것을 특징으로 하는 디지탈 집적회로 패키지.The digital integrated circuit package of claim 1, wherein the path is filled with a bimetallic composite. 제11항에 있어서, 상기 2금속 합성물은 구리-텅스텐인 것을 특징으로 하는 디지탈 집적회로 패키지.12. The digital integrated circuit package of claim 11, wherein the bimetallic composite is copper-tungsten. 제1항에 있어서, 상기 경로는 3금속 합성물로 충전되는 것을 특징으로 하는 디지탈 집적회로 패키지.The digital integrated circuit package of claim 1, wherein the path is filled with a trimetallic composite. 제11항에 있어서, 상기 3금속 합성물은 구리-은-텅스텐인 것을 특징으로 하는 디지탈 집적회로 패키지.12. The digital integrated circuit package of claim 11, wherein the trimetal composite is copper-silver-tungsten. 제1항에 있어서, 상기 트레이스는 적어도 약 0.002인치 만큼 다른 트레이스로부터 이격되어 있는 것을 특징으로 하는 디지탈 집적회로 패키지.4. The digital integrated circuit package of claim 1, wherein the traces are spaced apart from other traces by at least about 0.002 inches. 제1항에 있어서, 상기 보호구조물은 상기 기판의 주변에지로부터 상기 와이어본딩패드에 근접하여 뻗어있는 보호피복재로 이루어지고, 커버가 상기 보호피복재에 본딩되고 상기 와이어본딩패드, 와이어본드 및 적어도 하나의 다이위에 뻗어 있는 것을 특징으로 하는 디지탈 집적회로 패키지.The protective structure of claim 1, wherein the protective structure is made of a protective coating extending from a peripheral edge of the substrate in proximity to the wire bonding pad, wherein a cover is bonded to the protective coating and the wire bonding pad, the wire bond and at least one of them. A digital integrated circuit package, which extends over a die. 제1항에 있어서, 상기 보호구조물은 상기 기판의 외부 주변부에 본딩되고 상기 패키지 전체위에 뻗어있는 커버로 구성되는 것을 특징으로 하는 디지탈 집적회로 패키지.The digital integrated circuit package of claim 1, wherein the protective structure comprises a cover bonded to an outer periphery of the substrate and extending over the entire package. 제1항에 있어서, 상기 보호구조물은 상기 기판의 외부 주변부로부터 상기 와이어본딩 패드의 부근내에 뻗어 있는 보호피복재로 이루어지고, 에폭시로 된 블로브가 상기 보호피복재의 패키지 커버부 및 상기 와이어 본딩패드, 와이어본드 및 적어도 하나의 다이 모드에 인가되는 것을 특징으로 하는 디지탈 집적회로 패키지.According to claim 1, wherein the protective structure is made of a protective coating material extending from the outer peripheral portion of the substrate in the vicinity of the wire bonding pad, the epoxy blob is the package cover portion of the protective coating and the wire bonding pad, A digital integrated circuit package characterized in that it is applied to a wirebond and at least one die mode. 제16항에 있어서, 상기 커버는 금속 및 코바로 구성된 군으로부터 선택되는 것을 특징으로 하는 디지탈 집적회로 패키지.17. The digital integrated circuit package of claim 16, wherein the cover is selected from the group consisting of metal and cobar. 제19항에 있어서, 상기 커버는 전도성 금속으로 도금되는 것을 특징으로 하는 디지탈 집적회로 패키지.20. The digital integrated circuit package of claim 19, wherein the cover is plated with a conductive metal. 제20항에 있어서, 상기 전도성 금속은 금인 것을 특징으로 하는 디지탈 집적회로 패키지.21. The digital integrated circuit package of claim 20, wherein the conductive metal is gold. 제17항에 있어서, 상기 커버는 세라믹 재료로 구성되는 것을 특징으로 하는 디지탈 집적회로 패키지.18. The digital integrated circuit package of claim 17, wherein the cover is comprised of a ceramic material. 제22항에 있어서, 상기 세라믹재료는 Al2O3인 것을 특징으로 하는 디지탈 집적회로 패키지.23. The digital integrated circuit package of claim 22, wherein the ceramic material is Al 2 O 3 . 제22항에 있어서, 상기 세라믹재료는 AlN인 것을 특징으로 하는 디지탈 집적회로 패키지.23. The digital integrated circuit package of claim 22, wherein the ceramic material is AlN. 제17항에 있어서, 상기 커버는 금속 및 코바로 구성된 군으로부터 선택되는 것을 특징으로 하는 디지탈 집적회로 패키지.18. The digital integrated circuit package of claim 17, wherein the cover is selected from the group consisting of metal and cobar. 제25항에 있어서, 상기 커버는 전도성 금속으로 도금되는 것을 특징으로 하는 디지탈 집적회로 패키지.26. The digital integrated circuit package of claim 25, wherein the cover is plated with a conductive metal. 제26항에 있어서, 상기 전도성 금속은 금인 것을 특징으로 하는 디지탈 집적회로 패키지.27. The digital integrated circuit package of claim 26, wherein the conductive metal is gold. 제16항에 있어서, 상기 보호피복재는 유리인 것을 특징으로 하는 디지탈 집적회로 패키지.17. The digital integrated circuit package of claim 16, wherein the protective coating is glass. 제16항에 있어서, 상기 보호피복재는 폴리마이드 또는 에폭시인 것을 특징으로 하는 디지탈 집적회로 패키지.17. The digital integrated circuit package of claim 16, wherein the protective coating is polyamide or epoxy. 제16항에 있어서, 상기 보호피복재는 절연재료인 것을 특징으로 하는 디지탈 집적회로 패키지.17. The digital integrated circuit package of claim 16, wherein the protective coating material is an insulating material. 제18항에 있어서, 상기 보호피복재는 유리인 것을 특징으로 하는 디지탈 집적회로 패키지.19. The digital integrated circuit package of claim 18, wherein the protective coating is glass. 제18항에 있어서, 상기 보호피복재는 폴리마이드인 것을 특징으로 하는 디지탈 집적회로 패키지.19. The digital integrated circuit package of claim 18, wherein the protective coating is polyamide. 제18항에 있어서, 상기 보호피복재는 절연재료인 것을 특징으로 하는 디지탈 집적회로 패키지.19. The digital integrated circuit package according to claim 18, wherein the protective coating material is an insulating material. 제1항에 있어서, 상기 제1표면은 접착 프로모터, 전류캐리어, 버퍼 및 보호마무리층을 포함한 일련의 메탈라이제이션을 지원하는 것을 특징으로 하는 디지탈 집적회로 패키지.The digital integrated circuit package of claim 1, wherein the first surface supports a series of metallizations including an adhesion promoter, a current carrier, a buffer, and a protective layer. 제34항에 있어서, 상기 프로모터는 티단, 크롬, 티탄/텅스텐 합금, 및 티탄/몰리브덴 합금으로 구성된 군으로부터 선택되는 것을 특징으로 하는 디지탈 집적회로 패키지.35. The digital integrated circuit package of claim 34, wherein the promoter is selected from the group consisting of titanium, chromium, titanium / tungsten alloys, and titanium / molybdenum alloys. 제35항에 있어서, 상기 프로모터의 두께는 약 500 내지 약 2000Å 인 것을 특징으로 하는 디지탈 집적회로 패키지.36. The digital integrated circuit package of claim 35 wherein the promoter has a thickness of about 500 to about 2000 microseconds. 제35항에 있어서, 상기 전류캐리어는 구리인 것을 특징으로 하는 디지탈 집적회로 패키지.36. The digital integrated circuit package of claim 35, wherein the current carrier is copper. 제37항에 있어서, 상기 구리의 두께는 약 5 내지 약 10㎛인 것을 특징으로 하는 디지탈 집적회로 패키지.38. The digital integrated circuit package of claim 37, wherein the copper has a thickness of about 5 to about 10 microns. 제34항에 있어서, 상기 버퍼는 니켈인 것을 특징으로 하는 디지탈 집적회로 패키지.35. The digital integrated circuit package of claim 34, wherein the buffer is nickel. 제39항에 있어서, 상기 니켈의 두께는 약 1 내지 3.5㎛인 것을 특징으로 하는 디지탈 집적회로 패키지.40. The digital integrated circuit package of claim 39, wherein the nickel has a thickness of about 1 to 3.5 mu m. 제34항에 있어서, 상기 보호마무리층은 금인 것을 특징으로 하는 디지탈 집적회로 패키지.35. The digital integrated circuit package of claim 34, wherein the protective layer is gold. 제41항에 있어서, 상기 금의 두께는 약 2 내지 3.5㎛인 것을 특징으로 하는 디지탈 집적회로 패키지.42. The digital integrated circuit package of claim 41 wherein the gold has a thickness of about 2 to 3.5 [mu] m. 제1항에 있어서, 상기 제2표면은 접착 프로모터, 전류캐리어, 및 보호층을 포함한 일련의 메탈라이제이션을 지원하는 것을 특징으로 하는 디지탈 집적회로 패키지.The digital integrated circuit package of claim 1, wherein the second surface supports a series of metallizations including an adhesion promoter, a current carrier, and a protective layer. 제43항에 있어서, 상기 접착 프로모터는 티단, 크롬, 티탄/텅스텐 합금 및 티탄/몰리브덴 합금으로 구성된 군으로부터 선택되는 것을 특징으로 하는 디지탈 집적회로 패키지.44. The digital integrated circuit package of claim 43, wherein the adhesion promoter is selected from the group consisting of tidan, chromium, titanium / tungsten alloy and titanium / molybdenum alloy. 제44항에 있어서, 상기 프로모터의 두께는 약 500 내지 약 2000Å 인 것을 특징으로 하는 디지탈 집적회로 패키지.45. The digital integrated circuit package of claim 44, wherein the promoter has a thickness of about 500 to about 2000 microseconds. 제43항에 있어서, 상기 전류캐리어는 구리인 것을 특징으로 하는 디지탈 집적회로 패키지.44. The digital integrated circuit package of claim 43, wherein the current carrier is copper. 제46항에 있어서, 상기 구리의 두께는 약 3~5㎛인 것을 특징으로 하는 디지탈 집적회로 패키지.47. The digital integrated circuit package of claim 46, wherein the copper has a thickness of about 3-5 microns. 제39항에 있어서, 상기 버퍼는 니켈인 것을 특징으로 하는 디지탈 집적회로 패키지.40. The digital integrated circuit package of claim 39, wherein the buffer is nickel. 제48항에 있어서, 상기 니켈의 두께는 약 2.0~5㎛인 것을 특징으로 하는 디지탈 집적회로 패키지.49. The digital integrated circuit package of claim 48, wherein the nickel has a thickness of about 2.0-5 microns. 제43항에 있어서, 상기 보호마무리층은 금인 것을 특징으로 하는 디지탈 집적회로 패키지.44. The digital integrated circuit package of claim 43, wherein the protective layer is gold. 제50항에 있어서, 상기 금의 두께는 약 300~2000Å 인 것을 특징으로 하는 디지탈 집적회로 패키지.51. The digital integrated circuit package of claim 50, wherein the gold has a thickness of about 300 to 2000 microns. 제1항에 있어서, 상기 제1표면은 접착 프로모터, 전류캐리어, 및 최상부 메탈라이제이션을 포함한 일련의 메탈라이제이션을 지원하는 것을 특징으로 하는 디지탈 집적회로 패키지.The digital integrated circuit package of claim 1, wherein the first surface supports a series of metallizations including an adhesion promoter, a current carrier, and a top metallization. 제52항에 있어서, 상기 프로모터는 티단, 크롬, 티탄/텅스텐 합금, 및 티탄/몰리브덴 합금으로 구성된 군으로부터 선택되는 것을 특징으로 하는 디지탈 집적회로 패키지.53. The digital integrated circuit package of claim 52, wherein the promoter is selected from the group consisting of tidan, chromium, titanium / tungsten alloy, and titanium / molybdenum alloy. 제53항에 있어서, 상기 프로모터의 두께는 약 500 내지 약 2000Å 인 것을 특징으로 하는 디지탈 집적회로 패키지.54. The digital integrated circuit package of claim 53 wherein the promoter has a thickness of about 500 to about 2000 microseconds. 제52항에 있어서, 상기 전류캐리어는 구리인 것을 특징으로 하는 디지탈 집적회로 패키지.53. The digital integrated circuit package of claim 52 wherein the current carrier is copper. 제55항에 있어서, 상기 구리의 두께는 약 5 내지 약 10㎛인 것을 특징으로 하는 디지탈 집적회로 패키지.56. The digital integrated circuit package of claim 55, wherein the copper has a thickness of about 5 to about 10 microns. 제52항에 있어서, 상기 최상부 메탈라이제이션은 크롬인 것을 특징으로 하는 디지탈 집적회로 패키지.53. The digital integrated circuit package of claim 52 wherein the top metallization is chromium. 제57항에 있어서, 상기 크롬의 두께는 약 300~1000Å 인 것을 특징으로 하는 디지탈 집적회로 패키지.58. The digital integrated circuit package of claim 57, wherein the chromium has a thickness of about 300 to 1000 microns. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960020252A 1995-06-06 1996-06-07 High performance digital package using single layer ceramic substrate technology with BGA I / O format and bimetal filled path KR970003879A (en)

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US6140708A (en) * 1996-05-17 2000-10-31 National Semiconductor Corporation Chip scale package and method for manufacture thereof
US6284566B1 (en) 1996-05-17 2001-09-04 National Semiconductor Corporation Chip scale package and method for manufacture thereof
US5783866A (en) * 1996-05-17 1998-07-21 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
JPH11219984A (en) * 1997-11-06 1999-08-10 Sharp Corp Semiconductor device package, its manufacture and circuit board therefor
GB9818474D0 (en) * 1998-08-26 1998-10-21 Hughes John E Multi-layer interconnect package for optical devices & standard semiconductor chips
US6198166B1 (en) * 1999-07-01 2001-03-06 Intersil Corporation Power semiconductor mounting package containing ball grid array
DE10010461A1 (en) * 2000-03-03 2001-09-13 Infineon Technologies Ag Process for packing electronic components comprises injection molding components into ceramic substrate having conducting pathways, contact connection surfaces and pressure contacts
GB2377080B (en) 2001-09-11 2003-05-07 Sendo Int Ltd Integrated circuit package and printed circuit board arrangement
JP6397806B2 (en) 2015-09-11 2018-09-26 東芝メモリ株式会社 Semiconductor device manufacturing method and semiconductor device

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US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
TW272311B (en) * 1994-01-12 1996-03-11 At & T Corp

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MXPA96002171A (en) 2002-04-19
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JPH09213829A (en) 1997-08-15
GB2301937A (en) 1996-12-18
DE19622650A1 (en) 1996-12-12

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