KR960042374A - 단속제어회로를 구비한 반도체 메모리 장치와 제어방법 - Google Patents

단속제어회로를 구비한 반도체 메모리 장치와 제어방법 Download PDF

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KR960042374A
KR960042374A KR1019950013265A KR19950013265A KR960042374A KR 960042374 A KR960042374 A KR 960042374A KR 1019950013265 A KR1019950013265 A KR 1019950013265A KR 19950013265 A KR19950013265 A KR 19950013265A KR 960042374 A KR960042374 A KR 960042374A
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signal
output
data
semiconductor memory
sense amplifier
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KR1019950013265A
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KR0146530B1 (ko
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조호열
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김광호
삼성전자 주식회사
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Priority to JP8129721A priority patent/JPH08335393A/ja
Priority to US08/655,200 priority patent/US5654936A/en
Publication of KR960042374A publication Critical patent/KR960042374A/ko
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

1. 청구범위에 개재된 발명이 속하는 기술 분야
메모리 셀 어레이의 데이타를 효율적으로 출력하는 데이타선 단속 제어회로를 구비하는 반도체 메모리 장치.
2. 발명이 해결하려고 하는 기술적 과제
무효한 컬럼 어드레스 입력으로 인한 무효한 데이타 출력을 방지하여 안정된 데이타 출력 특성을 얻기 위하여 컬럼 어드레스 천이를 감지한 신호와 컬럼 어드레스 스트로우브 신호를 시간지연한 신호 ØCD 를 앤드게이트로 결합하여 입출력 센스증폭기와데이타 출력버퍼사이의 데이타선 단속수단을 제어하는 데이타선 단속제어회로를 제공한다.
3. 발명의 해결방법의 요지
본 발명은 본발명에 따른 반도체 메모리 장치에 있어서, 독출된 데이타를 센싱, 증폭하여 데이타선에 전달하는 입출력 센스증폭기와, 컬럼 어드레스 천이를 감지하여 감지신호를 발생하는 어드레스 천이 감지기와, 상기 입출력 센스증폭기를 통하여 증폭된 데이타를 선택하여 전송하는 데이타선 단속수단과, 컬럼 어드레스 스트로우브 신호를 시간지연시키는 제1지연회로와, 상기를 시간지연시키는 제2지연회로와, 상기 제1지연회로의 출력신호와 상기 제2지연회로의 출력신호를 논리게이트로 논리조합하여 출력된 신호가 상기 데이타선 단속수단을 게이팅하는 데이타선 단속제어회로를 구비함을 특징으로하는 반도체 메모리 장치를 포함한다.
4. 발명의 중요한 용도
본 발명에 따른 단속제어회로의 구성과 제어방법은 반도체 메모리 장치에 적합하게 사용된다.

Description

단속제어회로를 구비한 반도체 메모리 장치와 제어방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 따른 데이타선 단속제어회로의 구성과 제어방법을 보여주는 블럭도.

Claims (4)

  1. 메모리 어레이 셀과 상기 메모리 어레이 셀의 행을 지정하는 로우 디코더와 열을 지정하는 컬럼 디코더와비트라인의 신호를 센싱하여 증폭하는 비트라인 센스증폭기와 상기 비트라인 센스증폭기의 출력신호가 상기 입컬럼디코더의 출력신호로서 게이팅된 모오스트랜지스터를 경유하여 입출력라인에 선택적으로 인가되는 컬럼 선택 게이트수단을 구비한 반도체 메모리 장치에 있어서, 독출된 데이타를 센싱, 증폭하여 데이타선에 전달하는 입출력 센스증폭기와, 컬럼 어드레스 천이를 감지하여 감지신호를 발생하는 어드레스 천이 감지기와, 상기 입출력 센스증폭기를 통하여 증폭된 데이타를 선택하여 전송하는 데이타선 단속수단과, 컬럼 어드레스 스트로우브 신호를 시간지연시키는 제1지연회로와, 상기를 시간지연시키는 제2지연회로와, 상기 제1지연회로의 출력신호와 상기 제2지연회로의 출력신호를 논리게이트로 논리조합하여출력된 신호가 상기 데이타선 단속수단을 게이팅하는 데이타선 단속제어회로를 구비함을 특징으로하는 반도체 메모리 장치.
  2. 제1항에 있어서, 상기 논리게이트는 앤드게이트임을 특징으로 하는 반도체 메모리 장치.
  3. 메모리 어레이 셀과 상기 메모리 어레이 셀의 행을 지정하는 로우 디코더와 열을 지정하는 컬럼 디코더와비트라인의 신호를 센싱하여 증폭하는 비트라인 센스증폭기와 상기 비트라인 센스증폭기의 출력신호가 상기 컬럼 디코더의 출력신호로서 게이팅된 모오스트랜지스터를 경유하여 입출력라인에 선택적으로 인가되는 컬럼 선택 게이트수단을 구비한 반도체 메모리 장치의 데이타선 단속제어방법에 있어서, 어드레스 천이 감지기가 컬럼 어드레스 천이를 감지하여 감지신호를 발생하는 과정과, 독출된 데이타를 상기 감지신호에 적응하여 입출력 센스증폭기가 센싱, 증폭하는 과정과, 상기 입출력 센스증폭기에 의해 센싱, 증폭된 데이타를 데이타선 단속수단이 선택하여 데이타 출력단으로 출력하는 과정과, 제1지연회로가 컬럼 어드레스 스트로우브 신호를 시간지연시키는 과정과, 제2지연회로가 상기를 시간지연시키는 과정과, 상기 제1지연회로에서 시간지연된 출력신호 ØCD와를 논리게이트로 이루어진 데이타선 단속제어회로에서 논리조합하여 상기 데이타선 단속회로도 출력하는 과정과, 논리조합된 신호가 상기 데이타선 단속회로를 게이팅하여 제어하는 과정을 특징으로 하는 반도체 메모리 장치의 단속제어방법.
  4. 제3항에 있어서, 상기 논리게이트의 논리조합이 논리곱임을 특징으로 하는 반도체 메모리 장치의 단속제어방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950013265A 1995-05-25 1995-05-25 단속제어회로를 구비한 반도체 메모리 장치와 제어방법 KR0146530B1 (ko)

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KR1019950013265A KR0146530B1 (ko) 1995-05-25 1995-05-25 단속제어회로를 구비한 반도체 메모리 장치와 제어방법
JP8129721A JPH08335393A (ja) 1995-05-25 1996-05-24 半導体メモリ装置の出力制御方法とその回路
US08/655,200 US5654936A (en) 1995-05-25 1996-05-28 Control circuit and method for controlling a data line switching circuit in a semiconductor memory device

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KR1019950013265A KR0146530B1 (ko) 1995-05-25 1995-05-25 단속제어회로를 구비한 반도체 메모리 장치와 제어방법

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