KR960039439A - 폴리실리콘막의 제조방법 - Google Patents

폴리실리콘막의 제조방법 Download PDF

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Publication number
KR960039439A
KR960039439A KR1019950008995A KR19950008995A KR960039439A KR 960039439 A KR960039439 A KR 960039439A KR 1019950008995 A KR1019950008995 A KR 1019950008995A KR 19950008995 A KR19950008995 A KR 19950008995A KR 960039439 A KR960039439 A KR 960039439A
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KR
South Korea
Prior art keywords
polysilicon film
ion
argon gas
argon
polysilicon
Prior art date
Application number
KR1019950008995A
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English (en)
Inventor
이주형
한재종
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950008995A priority Critical patent/KR960039439A/ko
Priority to US08/632,840 priority patent/US5821157A/en
Publication of KR960039439A publication Critical patent/KR960039439A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

이 발명은 액정디스플레이용 박막트랜지스터의 폴리실리콘막 제조 방법.에 있어서, 폴리실리콘막의 특성을 향상시키기 위한 폴리실리콘막 이온주입 공정시 이온물질로 아르곤 가스를 사용하는 폴리실리콘막의 제조 방법.에 관한 것으로서, 기판위에 폴리실리콘막을 증착하는 단계와, 상기 폴리실리콘막에 아르곤 가스를 주입하여 상기 폴리실리콘막을 선택적으로 비정질화시키는 단계와,; 상기 비정질화된 실리콘층을 열처리 하여 폴리실리콘막으로 재결정화하는 단계로 이루어져 있다.

Description

폴리실리콘막의 제조 방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도의(가) ∼(라)는 이 발명의 실시예에 따른 폴리 실리콘막의 제조공정을 나타낸 단면도이고, 제4도는 이 발명의 실시예에 다른 아르곤 이온 주입 에너지에 다른 결정화 정도를 나타낸 도표이다.

Claims (5)

  1. 기판위에 폴리실리콘막을 증착하는 단계와,. 상기 폴리실리콘막에 아르곤이온을 주입하여 상기 폴리실리콘막을 선택적으로 비정질화시키는 단계와,. 상기 비정질화된 실리콘층을 열처리하여 폴리실리콘막으로 재결정화 하는 단계로 이루어져 있는 것을 특징으로 하는 폴리실리콘막의 제조 방법.
  2. 제1항에 있어서, 상기 아르곤가스의 이온주입은 80KeV 로 이온주입하는 것을 특징으로 하는 폴리실리콘막의 제조 방법.
  3. 제1항에 있어서, 상기 아르곤가스의 이온주입은 3.0 × 1014/㎠ 내지 8.0 × 1014/㎠로 이온주입하는 것을 특징으로 하는 폴리실리콘막의 제조 방법.
  4. 제1항에 있어서, 상기 아르곤가스 이온주입시, 아르곤이온의 투사이온영역은 상기 폴리실리콘막 밑의 기판에 놓이게 함으로써 상기 아르곤이 실리콘 내에 남아 결정성장을 방해하는 것을 방지하는 것을 특징으로 하는 폴리실리콘막의제조 방법.
  5. 제1항에 있어서, 상기 열처리 단계는 650℃이하에서 이루어지는 것을 특징으로 하는 폴리실리콘막의 제조 방법.
    ※참고사항: 최초출원내용에 의하여 공개하는 것임.
KR1019950008995A 1995-04-17 1995-04-17 폴리실리콘막의 제조방법 KR960039439A (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019950008995A KR960039439A (ko) 1995-04-17 1995-04-17 폴리실리콘막의 제조방법
US08/632,840 US5821157A (en) 1995-04-17 1996-04-16 Argon amorphizing polysilicon layer fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950008995A KR960039439A (ko) 1995-04-17 1995-04-17 폴리실리콘막의 제조방법

Publications (1)

Publication Number Publication Date
KR960039439A true KR960039439A (ko) 1996-11-25

Family

ID=19412345

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950008995A KR960039439A (ko) 1995-04-17 1995-04-17 폴리실리콘막의 제조방법

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US (1) US5821157A (ko)
KR (1) KR960039439A (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW399235B (en) * 1998-12-04 2000-07-21 United Microelectronics Corp Selective semi-sphere silicon grain manufacturing method
US6177326B1 (en) * 1998-12-08 2001-01-23 United Microelectronics Corp. Method to form bottom electrode of capacitor
DE10006378C2 (de) * 2000-02-12 2001-12-06 Rossendorf Forschzent Verfahren zur Herstellung Ohmscher Kontakte auf Siliziumkarbid-Halbleiterbereichen
DE10231407B4 (de) * 2002-07-11 2007-01-11 Infineon Technologies Ag Bipolartransistor
TWI291310B (en) * 2005-12-01 2007-12-11 Au Optronics Corp Organic light emitting diode (OLED) display panel and method of forming polysilicon channel layer thereof
FR2907965B1 (fr) * 2006-10-27 2009-03-06 Soitec Silicon On Insulator Procede de traitement d'un substrat donneur pour la fabrication d'un substrat.
US11676961B2 (en) 2020-11-01 2023-06-13 Texas Instruments Incorporated Semiconductor device with low noise transistor and low temperature coefficient resistor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate
JPH07106512A (ja) * 1993-10-04 1995-04-21 Sharp Corp 分子イオン注入を用いたｓｉｍｏｘ処理方法

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US5821157A (en) 1998-10-13

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