KR960035912A - 반도체 소자의 트랜지스터 제조방법 - Google Patents

반도체 소자의 트랜지스터 제조방법 Download PDF

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KR960035912A
KR960035912A KR1019950006092A KR19950006092A KR960035912A KR 960035912 A KR960035912 A KR 960035912A KR 1019950006092 A KR1019950006092 A KR 1019950006092A KR 19950006092 A KR19950006092 A KR 19950006092A KR 960035912 A KR960035912 A KR 960035912A
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South Korea
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film
gate electrode
semiconductor device
layer
implanting
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KR1019950006092A
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KR0146522B1 (ko
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황준
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김주용
현대전자산업 주식회사
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Priority to KR1019950006092A priority Critical patent/KR0146522B1/ko
Priority to TW085103300A priority patent/TW301035B/zh
Priority to US08/621,731 priority patent/US5681771A/en
Priority to CN96105950A priority patent/CN1077330C/zh
Publication of KR960035912A publication Critical patent/KR960035912A/ko
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Publication of KR0146522B1 publication Critical patent/KR0146522B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, P형 MOS 트랜지스터를 제조함에 있어, 쇼트채널효과(Short Channel Effect)를 억제시키기 위하여 실리콘기판에 N+영역을 형성하고 BSG(Bor-on Silicate Glass)막을 이용하여 상기 N+영역 상부에 P--층이 형성되도록 하므로써 얕은 접합깊이 (Shallow Junction Depth)를 갖는 접합영역을 형성하며 높은 전달콘덕턴스(Trans Conductance)를 이룰 수 있도록 한 반도체 소자의 트랜지스터 제조방법에 관한 것이다.

Description

반도체 소자의 트랜지스터 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2A 내지 제 2E 도는 본발명의 제 1실시예를 설명하기 위한 소자의 단면도.

Claims (3)

  1. 반도체 소자의 트랜지스터 제조방법에 있어서, N웰이 형성된 실리콘기판상에 산화막을 성장시킨후 N+형 불순물이온을 주입하고 열처리하여 상기 실리콘기판에 N+영역을 형성시키는 단계와, 상기 단계로부터 상기 산화막을 제거한 후 전체면에 제1 BSG막을 증착하고 급속열처리공정을 실시하여 상기 N+영역의 상부에 P- -층을 형성시키는 단계와, 상기 단계로 부터 상기 제 1 BSG막을 제거한 후 게이트산화막 및 폴리실리콘층을 순차적으로 형성하고 상기 폴리실리콘층에 P+형 불순물이온을 주입한 후 게이트전극용 마스트를 이용한 사진 및 식각공정을 통해 상기 폴리실리콘층 및 게이트산화막을 순차적으로 패터닝하여 게이트전극을 형성한 다음 상기 게이트전극의 양측부에 산화막스페이서를 형성하는 단계와, 상기 단계로 부터 전체면에 제2 BSG막을 증착한 후 P+형 불순물이온을 주입하여 접합영역을 형성하고 급속열처리공정을 실시하는 단계와, 상기 단계로 부터 상기 제 2 BSG막을 제거하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  2. 제 1항에 있어서, 상기 N+영역의 불순물농도는 상기 N웰의 불순물농도보다 높게 주입되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  3. 반도체 소자의 트랜지스터 제조방법에 있어서, 실리콘기판상에 산화막을 성장시킨후 N형 불순물이 온을 주입하고 드라이브-인하여 N웰을 형성하는 단계와, 상기 단계로 부터 상기 산화막을 제거한 후 전체면에 BSG막을 증착하고 급속열처리공정을 실시하여 상기 N웰의 상부에 P- -층을 형성시키는 단계와 상기 단계로 부터 상기 BSG막을 제거한 후 게이트산화막 및 폴리실리콘층을 순차적으로 형성하고 상기 폴리실리콘층에 P+형 불순물이온을 주입한 후 게이트전극용 마스크를 이용한 사진 및 식각공정을 통해 상기 폴리실리콘층 및 게이트산화막을 순차적으로 패터닝하에 게이트전극을 형성하는 단계와, 상기 단계로 부터 상기 게이트전극의 양측부에 산화막스페이서를 형성하고 P+형 불순물이온을 주입하여 접합영역을 형성한 후 열처리하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950006092A 1995-03-22 1995-03-22 반도체 소자의 트랜지스터 제조방법 KR0146522B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950006092A KR0146522B1 (ko) 1995-03-22 1995-03-22 반도체 소자의 트랜지스터 제조방법
TW085103300A TW301035B (en) 1995-03-22 1996-03-19 Method of manufacturing a transistor in a semiconductor device
US08/621,731 US5681771A (en) 1995-03-22 1996-03-21 Method of manufacturing a LDD transistor in a semiconductor device
CN96105950A CN1077330C (zh) 1995-03-22 1996-03-22 制造半导体器件中晶体管的方法

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KR1019950006092A KR0146522B1 (ko) 1995-03-22 1995-03-22 반도체 소자의 트랜지스터 제조방법

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KR0146522B1 KR0146522B1 (ko) 1998-11-02

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KR (1) KR0146522B1 (ko)
CN (1) CN1077330C (ko)
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW388087B (en) * 1997-11-20 2000-04-21 Winbond Electronics Corp Method of forming buried-channel P-type metal oxide semiconductor
US5880006A (en) * 1998-05-22 1999-03-09 Vlsi Technology, Inc. Method for fabrication of a semiconductor device
US6274467B1 (en) 1999-06-04 2001-08-14 International Business Machines Corporation Dual work function gate conductors with self-aligned insulating cap
US6927137B2 (en) * 2003-12-01 2005-08-09 Texas Instruments Incorporated Forming a retrograde well in a transistor to enhance performance of the transistor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3095564B2 (ja) * 1992-05-29 2000-10-03 株式会社東芝 半導体装置及び半導体装置の製造方法
US5024959A (en) * 1989-09-25 1991-06-18 Motorola, Inc. CMOS process using doped glass layer
JP3131436B2 (ja) * 1990-02-26 2001-01-31 株式会社東芝 半導体装置の製造方法
US5340770A (en) * 1992-10-23 1994-08-23 Ncr Corporation Method of making a shallow junction by using first and second SOG layers
US5338698A (en) * 1992-12-18 1994-08-16 International Business Machines Corporation Method of fabricating an ultra-short channel field effect transistor
JPH07297400A (ja) * 1994-03-01 1995-11-10 Hitachi Ltd 半導体集積回路装置の製造方法およびそれにより得られた半導体集積回路装置

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Publication number Publication date
CN1077330C (zh) 2002-01-02
KR0146522B1 (ko) 1998-11-02
CN1136709A (zh) 1996-11-27
US5681771A (en) 1997-10-28
TW301035B (en) 1997-03-21

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