KR960030367A - 반도체 장치의 소자분리방법 - Google Patents

반도체 장치의 소자분리방법 Download PDF

Info

Publication number
KR960030367A
KR960030367A KR1019950000770A KR19950000770A KR960030367A KR 960030367 A KR960030367 A KR 960030367A KR 1019950000770 A KR1019950000770 A KR 1019950000770A KR 19950000770 A KR19950000770 A KR 19950000770A KR 960030367 A KR960030367 A KR 960030367A
Authority
KR
South Korea
Prior art keywords
film
forming
antioxidant
polysilicon
polysilicon film
Prior art date
Application number
KR1019950000770A
Other languages
English (en)
Other versions
KR0144934B1 (ko
Inventor
구본립
이재경
박찬식
류세형
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950000770A priority Critical patent/KR0144934B1/ko
Publication of KR960030367A publication Critical patent/KR960030367A/ko
Application granted granted Critical
Publication of KR0144934B1 publication Critical patent/KR0144934B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

Abstract

반도체장치의 소자 분리 방법이 개시되어 있다. 본 발명은 반도체기판 상에 산화막을 형성하는 단계와, 상기 산화막 상에 폴리실리콘막을 형성하는 단계와, 상기 폴리실리콘막 상에 PECVD방법으로 산화방지막을 형성하는 단계와, 상기 산화방지막을 패터닝하여 산화방지막 패턴을 형성하는 단계와, 상기 산화방지막 패턴을 마스크로 하여 상기 폴리실리콘막 및 기판에 열산화를 실시하여 소자분리막을 형성하는 단계와, 및 상기 산화방지막 및 폴리실리콘막을 제거하는 단계를 포함한다. 본 발명에 의하면, 소자분리의 산화방지막으로 사용되는 실리콘질화막을 PECVD방법으로 형성함으로써 폴리실리콘막내에 핀홀의 발생을 억제할 수 있다. 이에 따라, 반도체기판에 핏팅(홈)의 발생을 억제할 수 있어, 반도체 장치의 불량을 방지할 수 있다.

Description

반도체 장치의 소자분리방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제8도 내지 제11도는 본 발명의 소자분리방법을 설명하기 위하여 도시한 단면도들이다.

Claims (2)

  1. 반도체기판 상에 산화막을 형성하는 단계; 상기 산화막 상에 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막 상에 PECVD방법으로 산화방지막을 형성하는 단계; 상기 산화방지막을 패터닝하여 산화방지막 패턴을 형성하는 단계; 상기 산화방지막 패턴을 마스크로 하여 상기 폴리실리콘막 및 기판에 열산화를 실시하여 소자분리막을 형성하는 단계; 및 상기 산화방지막 및 폴리실리콘막을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 소자분리방법.
  2. 제1항에 있어서, 상기 산화방지막은 실리콘질화막으로 형성하는 것을 특징으로 하는 반도체장치의 소자분리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950000770A 1995-01-18 1995-01-18 반도체 장치의 소자분리방법 KR0144934B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950000770A KR0144934B1 (ko) 1995-01-18 1995-01-18 반도체 장치의 소자분리방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950000770A KR0144934B1 (ko) 1995-01-18 1995-01-18 반도체 장치의 소자분리방법

Publications (2)

Publication Number Publication Date
KR960030367A true KR960030367A (ko) 1996-08-17
KR0144934B1 KR0144934B1 (ko) 1998-08-17

Family

ID=19406876

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950000770A KR0144934B1 (ko) 1995-01-18 1995-01-18 반도체 장치의 소자분리방법

Country Status (1)

Country Link
KR (1) KR0144934B1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6981901B2 (ja) * 2018-03-13 2021-12-17 アズビル株式会社 ピエゾ抵抗型センサ

Also Published As

Publication number Publication date
KR0144934B1 (ko) 1998-08-17

Similar Documents

Publication Publication Date Title
KR950015715A (ko) 반도체 장치의 소자 분리막 형성방법
KR960030367A (ko) 반도체 장치의 소자분리방법
KR940022794A (ko) 반도체 장치의 제조방법
KR970054532A (ko) 반도체소자의 소자분리막 제조방법
KR970077456A (ko) 반도체 소자의 콘택 홀 형성 방법
KR970053462A (ko) 반도체 소자의 필드 산화막 형성 방법
KR960002744A (ko) 반도체 소자의 소자분리막 형성방법
KR970052208A (ko) 반도체 소자의 비아홀 형성방법
KR950025954A (ko) 반도체장치의 소자분리방법
KR980005304A (ko) 반도체 소자의 감광막 형성방법
KR950015711A (ko) 반도체 장치의 소자격리영역 형성방법
KR920013731A (ko) 반도체장치의 소자격리방법
KR970052901A (ko) 반도체 소자의 필드 산화막 형성방법
KR970053372A (ko) 반도체소자의 소자분리막 제조방법
KR970023737A (ko) 반도체장치의 금속배선 형성방법
KR970053120A (ko) 반도체장치의 제조방법
KR970053424A (ko) 반도체소자의 소자분리막 형성방법
KR960026576A (ko) 반도체 소자의 필드산화막 형성방법
KR970052660A (ko) 반도체 소자의 아이솔레이션 방법
KR940016589A (ko) 필드산화막 제조방법
KR920010745A (ko) 반도체 장치의 저항소자 형성방법
KR970030629A (ko) 소자격리영역의 형성방법
KR970051889A (ko) 반도체 소자의 자기 정렬 마스크 형성방법
KR970072094A (ko) 반도체 장치의 콘택 식각 방법
KR970016829A (ko) 난반사막을 이용한 산화막 사진식각방법

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100413

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee