KR960009248B1 - Clock-synchronous semiconductor memory device and the access method thereof - Google Patents

Clock-synchronous semiconductor memory device and the access method thereof Download PDF

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Publication number
KR960009248B1
KR960009248B1 KR93004252A KR930004252A KR960009248B1 KR 960009248 B1 KR960009248 B1 KR 960009248B1 KR 93004252 A KR93004252 A KR 93004252A KR 930004252 A KR930004252 A KR 930004252A KR 960009248 B1 KR960009248 B1 KR 960009248B1
Authority
KR
South Korea
Prior art keywords
clock
memory device
semiconductor memory
access method
synchronous semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR93004252A
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English (en)
Korean (ko)
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KR930020279A (ko
Inventor
Haruki Toda
Hitoshi Kuyama
Original Assignee
Toshiba Kk
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Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of KR930020279A publication Critical patent/KR930020279A/ko
Application granted granted Critical
Publication of KR960009248B1 publication Critical patent/KR960009248B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
KR93004252A 1992-03-19 1993-03-19 Clock-synchronous semiconductor memory device and the access method thereof Expired - Lifetime KR960009248B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP92-063844 1992-03-19
JP6384492 1992-03-19

Publications (2)

Publication Number Publication Date
KR930020279A KR930020279A (ko) 1993-10-19
KR960009248B1 true KR960009248B1 (en) 1996-07-16

Family

ID=13241051

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93004252A Expired - Lifetime KR960009248B1 (en) 1992-03-19 1993-03-19 Clock-synchronous semiconductor memory device and the access method thereof

Country Status (4)

Country Link
US (3) US5818793A (https=)
EP (1) EP0561370B1 (https=)
KR (1) KR960009248B1 (https=)
DE (1) DE69325119T2 (https=)

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US6310821B1 (en) * 1998-07-10 2001-10-30 Kabushiki Kaisha Toshiba Clock-synchronous semiconductor memory device and access method thereof
JP3579461B2 (ja) 1993-10-15 2004-10-20 株式会社ルネサステクノロジ データ処理システム及びデータ処理装置
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US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
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US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
JP3406790B2 (ja) * 1996-11-25 2003-05-12 株式会社東芝 データ転送システム及びデータ転送方法
JP3523004B2 (ja) * 1997-03-19 2004-04-26 株式会社東芝 同期式ランダムアクセスメモリ
KR100481828B1 (ko) * 1997-05-19 2005-07-05 삼성전자주식회사 가변어드레스제어장치를이용한메모리제어방법
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
JPH1116349A (ja) * 1997-06-26 1999-01-22 Mitsubishi Electric Corp 同期型半導体記憶装置
US6401167B1 (en) 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
AU9604698A (en) 1997-10-10 1999-05-03 Rambus Incorporated Method and apparatus for two step memory write operations
US6147546A (en) * 1998-03-11 2000-11-14 International Business Machines Corporation Zero volt/zero current fuse arrangement
JP4060442B2 (ja) * 1998-05-28 2008-03-12 富士通株式会社 メモリデバイス
JP4540137B2 (ja) * 1998-07-24 2010-09-08 ルネサスエレクトロニクス株式会社 同期型半導体記憶装置
EP1122887A1 (en) 2000-01-31 2001-08-08 STMicroelectronics S.r.l. Pre-charging circuit of an output buffer
US6624679B2 (en) 2000-01-31 2003-09-23 Stmicroelectronics S.R.L. Stabilized delay circuit
EP1122733A1 (en) 2000-01-31 2001-08-08 STMicroelectronics S.r.l. Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and relative circuit
EP1122739A3 (en) 2000-01-31 2003-12-17 STMicroelectronics S.r.l. Accelerated carry generation.
US6452864B1 (en) 2000-01-31 2002-09-17 Stmicroelectonics S.R.L. Interleaved memory device for sequential access synchronous reading with simplified address counters
EP1122735B1 (en) 2000-01-31 2010-09-01 STMicroelectronics Srl Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data
EP1122734B1 (en) * 2000-01-31 2005-03-30 STMicroelectronics S.r.l. Burst interleaved memory with burst mode access in synchronous read phases wherein the two sub-arrays are independently readable with random access during asynchronous read phases
EP1122736B1 (en) 2000-01-31 2009-10-28 STMicroelectronics S.r.l. ATD generation in a synchronous memory
EP1122737A1 (en) 2000-01-31 2001-08-08 STMicroelectronics S.r.l. Circuit for managing the transfer of data streams from a plurality of sources within a system
EP1130517B1 (en) 2000-03-02 2004-05-26 STMicroelectronics S.r.l. Redundancy architecture for an interleaved memory
JP4741122B2 (ja) * 2001-09-07 2011-08-03 富士通セミコンダクター株式会社 半導体装置及びデータ転送方法
KR100520178B1 (ko) * 2003-03-28 2005-10-10 주식회사 하이닉스반도체 반도체 메모리 장치의 입력 버퍼

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US4330852A (en) * 1979-11-23 1982-05-18 Texas Instruments Incorporated Semiconductor read/write memory array having serial access
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US5142637A (en) * 1988-11-29 1992-08-25 Solbourne Computer, Inc. Dynamic video RAM incorporating single clock random port control
DE68928840T2 (de) * 1988-11-29 1999-04-01 Matsushita Electric Ind Co Ltd Synchroner dynamischer Speicher
US5148523A (en) * 1988-11-29 1992-09-15 Solbourne Computer, Inc. Dynamic video RAM incorporationg on chip line modification
US5148524A (en) * 1988-11-29 1992-09-15 Solbourne Computer, Inc. Dynamic video RAM incorporating on chip vector/image mode line modification
CA2010122A1 (en) * 1989-06-21 1990-12-21 Makoto Sakamoto Integrated circuit including programmable circuit
KR100214435B1 (ko) * 1990-07-25 1999-08-02 사와무라 시코 동기식 버스트 엑세스 메모리
JP2740063B2 (ja) * 1990-10-15 1998-04-15 株式会社東芝 半導体記憶装置
TW198135B (https=) * 1990-11-20 1993-01-11 Oki Electric Ind Co Ltd
US5235545A (en) * 1991-03-29 1993-08-10 Micron Technology, Inc. Memory array write addressing circuit for simultaneously addressing selected adjacent memory cells
JP3992757B2 (ja) * 1991-04-23 2007-10-17 テキサス インスツルメンツ インコーポレイテツド マイクロプロセッサと同期するメモリ、及びデータプロセッサ、同期メモリ、周辺装置とシステムクロックを含むシステム
US5305277A (en) * 1991-04-24 1994-04-19 International Business Machines Corporation Data processing apparatus having address decoder supporting wide range of operational frequencies
JPH0574167A (ja) * 1991-09-17 1993-03-26 Nec Corp 半導体記憶装置
KR950000504B1 (ko) * 1992-01-31 1995-01-24 삼성전자 주식회사 복수개의 로우 어드레스 스트로브 신호를 가지는 반도체 메모리 장치
EP0561370B1 (en) * 1992-03-19 1999-06-02 Kabushiki Kaisha Toshiba A clock-synchronous semiconductor memory device and access method thereof
JP2740097B2 (ja) * 1992-03-19 1998-04-15 株式会社東芝 クロック同期型半導体記憶装置およびそのアクセス方法
JP2830594B2 (ja) * 1992-03-26 1998-12-02 日本電気株式会社 半導体メモリ装置

Also Published As

Publication number Publication date
US5986968A (en) 1999-11-16
EP0561370B1 (en) 1999-06-02
EP0561370A3 (https=) 1994-12-21
DE69325119T2 (de) 1999-11-04
EP0561370A2 (en) 1993-09-22
DE69325119D1 (de) 1999-07-08
US5818793A (en) 1998-10-06
KR930020279A (ko) 1993-10-19
US5798979A (en) 1998-08-25

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